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s12 microcontrollers freescale.com mc9s12xhy256 reference manual covers mc9s12xhy family mc9s12xhy256rmv1 rev. 1.01 03/2011 data sheet: advance information this document contains information on a new product. speci?ations and information here in are subject to change without notice .
to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ a full list of family members and options is included in the appendices. the following revision history table summarizes changes contained in this document. this document contains information for all constituent modules, with the exception of the cpu. for cpu information please refer to cpu12-1 in the cpu12 & cpu12x reference manual . revision history date revision level description jun,3,2010 0.11 update block: tim sci pim chapter1 update table a-6., ?-v i/o characteristics , item 11/12,unit is k ? and ua update a.1.10.1, ?ypical run current measurement conditions update table a-6., ?-v i/o characteristics , 4(a) , remove v c contitions update table a-6., ?-v i/o characteristics ,4(b), remove temperature update table a-10., ?un and wait current characteristics , remove item update table a-11., ?seudo stop and full stop current , -10a/10b/11/12/13/14,remove temperature except -40/25/150 -15, change to fsp mode remove typeical run supply table update table a-11., ?seudo stop and full stop current , add lcp fsp mode jun,11,2010 0.12 update appendix electrical parameter - table a-6., ?-v i/o characteristics 4a 9 10 11 12 table a-11., ?seudo stop and full stop current ,10a,11a,12a,14,15 - table a-4./a-721 lcd/motor driver pad can only be work under >4.5v - a.1.3.1/a-718 , change to 4.5v to 5.5v -remove 12 bit resolution at table table a-12./a-731 update chapter mmc to ver04.11 3.1/3-157 update chapter mscan to ver03.12 update table d-2./d-768 ,all parts has 2x can and sci mar,25,2011 1.01 update appendix electrical parameter value table a-11., ?seudo stop and full stop current , table a-9., ?odule run supply currents table a-6., ?-v i/o characteristics , item 4b update appendix, change classi?ations or conditions table a-6., ?-v i/o characteristics , item 4b, change from 80c to 150c table a-11., ?seudo stop and full stop current ,item 11b,change from p to c ? typo table a-6., ?-v i/o characteristics , 11 and 12, resistance not current
how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution p.o. box 5405, denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: freescale semiconductor japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/paci?: freescale semiconductor h.k. ltd. 2 dai king street tai po industrial estate tai po, n.t. hong kong 852-26668334 learn more: for more information about freescale semiconductor products, please visit http://www.freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters which may be provided in freescale semiconductor data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by customers technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ?freescale semiconductor, inc. 2006
mc9s12xhy-family reference manual, rev. 1.01 4 freescale semiconductor
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 5 chapter 1 device overview mc9s12xhy-family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 chapter 2 port integration module (s12xhypimv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 chapter 3 memory mapping control (s12xmmcv4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 chapter 4 interrupt (s12xintv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 chapter 5 background debug module (s12xbdmv2) . . . . . . . . . . . . . . . . . . . . . . . . . 197 chapter 6 s12x debug (s12xdbgv3) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 chapter 7 s12xe clocks and reset generator (s12xecrgv2) . . . . . . . . . . . . . . . . . 259 chapter 8 pierce oscillator (s12xosclcpv2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 chapter 9 voltage regulator (s12vregl3v3v1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 chapter 10 analog-to-digital converter (adc12b12cv1) . . . . . . . . . . . . . . . . . . . . . . . 315 chapter 11 freescale? scalable controller area network (s12mscanv3) . . . . . . . . . 341 chapter 12 inter-integrated circuit (iicv3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 chapter 13 pulse-width modulator (s12pwm8b8cv1) . . . . . . . . . . . . . . . . . . . . . . . . . . 423 chapter 14 serial communication interface (s12sciv5) . . . . . . . . . . . . . . . . . . . . . . . . 455 chapter 15 serial peripheral interface (s12spiv5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 chapter 16 timer module (tim16b8cv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
mc9s12xhy-family reference manual, rev. 1.01 6 freescale semiconductor chapter 17 liquid crystal display (lcd40f4bv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 chapter 18 256 kbyte flash module (s12xftmr256k1v1) . . . . . . . . . . . . . . . . . . . . . . 569 chapter 19 128 kbyte flash module (s12xftmr128k1v1) . . . . . . . . . . . . . . . . . . . . . . 619 chapter 20 motor controller (mc10b8cv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 chapter 21 stepper stall detector (ssdv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 appendix a electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 appendix b package and die information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 appendix c pcb layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 appendix d derivative differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 appendix e detailed register address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 appendix f ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 7 chapter 1 device overview mc9s12xhy-family 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.6 part id assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.7 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.8 system clock description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1.9 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1.10 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.11 resets and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.12 cop con?uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 1.13 atd external trigger input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 1.14 atd channel[17] connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.15 vreg con?uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1.16 oscillator con?uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1.17 documentation note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 chapter 2 port integration module (s12xhypimv1) 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 2.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 2.5 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 chapter 3 memory mapping control (s12xmmcv4) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 3.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 3.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 3.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 3.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 chapter 4 interrupt (s12xintv2) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 4.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 4.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 85 4.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 4.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
mc9s12xhy-family reference manual, rev. 1.01 8 freescale semiconductor chapter 5 background debug module (s12xbdmv2) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 5.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 5.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 00 5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 chapter 6 s12x debug (s12xdbgv3) module 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 6.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 chapter 7 s12xe clocks and reset generator (s12xecrgv2) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 7.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 7.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 7.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 7.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 chapter 8 pierce oscillator (s12xosclcpv2) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 8.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 8.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 92 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 chapter 9 voltage regulator (s12vregl3v3v1) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 9.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 9.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 01 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 chapter 10 analog-to-digital converter (adc12b12cv1) block description 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 10.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 10.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 9 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 10.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 10.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 chapter 11 freescale? scalable controller area network (s12mscanv3) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 11.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 11.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 11.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 chapter 12 inter-integrated circuit (iicv3) block description 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 12.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 12.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 12.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 12.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 12.7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 chapter 13 pulse-width modulator (s12pwm8b8cv1) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 13.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 13.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 13.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 13.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 chapter 14 serial communication interface (s12sciv5) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 14.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 14.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 14.5 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 chapter 15 serial peripheral interface (s12spiv5) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 15.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 15.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
mc9s12xhy-family reference manual, rev. 1.01 10 freescale semiconductor 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 chapter 16 timer module (tim16b8cv2) block description 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 16.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 16.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 16.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 16.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 chapter 17 liquid crystal display (lcd40f4bv2) block description 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 17.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 17.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 17.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 17.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 chapter 18 256 kbyte flash module (s12xftmr256k1v1) 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 18.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 18.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 18.5 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 18.6 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 chapter 19 128 kbyte flash module (s12xftmr128k1v1) 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 19.2 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 19.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 19.4 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 19.5 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 chapter 20 motor controller (mc10b8cv1) 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 20.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 20.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 20.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 20.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 11 20.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 20.7 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 chapter 21 stepper stall detector (ssdv1) block description 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 21.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701 21.3 memory map and register de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702 21.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 appendix a electrical characteristics a.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 a.1.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 17 a.1.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 a.1.3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 a.1.4 current injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 a.1.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 a.1.6 esd protection and latch-up immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 a.1.7 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 a.1.8 power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 a.1.9 i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 a.1.10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 a.2 atd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 a.2.1 atd operating characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 a.2.2 factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 a.2.3 atd accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 a.3 nvm, flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 a.3.1 timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 a.3.2 nvm reliability parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 a.4 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 a.5 output loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 a.5.1 resistive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 a.5.2 capacitive loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 a.5.3 chip power-up and voltage drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 a.6 reset, oscillator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 a.6.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 a.6.2 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 a.6.3 phase locked loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 a.7 lcd driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 a.8 mscan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 a.9 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 a.9.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 a.9.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
mc9s12xhy-family reference manual, rev. 1.01 12 freescale semiconductor appendix b package and die information b.1 112-pin lqfp mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9 b.2 100-pin lqfp mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2 appendix c pcb layout guidelines c.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 c.1.1 112-pin lqfp recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 c.1.2 100-pin qfp recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 appendix d derivative differences d.1 memory sizes and package options 9s12xhy family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 appendix e detailed register address map e.1 detailed register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 appendix f ordering information f.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 13 chapter 1 device overview mc9s12xhy-family 1.1 introduction the mc9s12xhy family is an optimized, automotive, 16-bit microcontroller product line that is speci?ally designed for entry level instrument clusters. this family also services generic automotive applications requiring can, lcd, motor driver control or lin/sae j2602. typical examples of these applications include instrument clusters for automobiles and 2 or 3 wheelers, hvac displays, general purpose motor control and body controllers. the mc9s12xhy family uses many of the same features found on the mc9s12xs family and mc9s12hy/ha family, including error correction code (ecc) on ?sh memory, a separate data-?sh module for diagnostic or data storage, a fast analog-to-digital converter (atd) and a frequency modulated phase locked loop (ipll) that improves the emc performance. the mc9s12xhy family features a 40x4 liquid crystal display (lcd) controller/driver and a motor pulse width modulator (mc) consisting of up to 16 high current outputs. the device is capable of stepper motor stall detection (ssd) via hardware or software, please contact freescale sales of?e for detailed information on software ssd. the mc9s12xhy family deliver all the advantages and ef?iencies of a 16-bit mcu while retaining the low cost, power consumption, emc, and code-size ef?iency advantages currently enjoyed by users of freescales existing 8-bit and 16-bit mcu families. like the mc9s12hy/ha family, the mc9s12xhy family run 16-bit wide accesses without wait states for all peripherals and memories. the mc9s12xhy family is available in 112-pin lqfp and 100-pin lqfp package options. in addition to the i/o ports available in each module, further i/o ports are available with interrupt capability allowing wake-up from stop or wait modes. 1.2 features this section describes the key features of the mc9s12xhy family.
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 14 freescale semiconductor 1.2.1 mc9s12xhy family comparison table 1-1 provides a summary of different members of the mc9s12xhy family and their proposed features. this information is intended to provide an understanding of the range of functionality offered by this microcontroller family. table 1-1. mc9s12xhy family feature mc9s12xhy128 mc9s12xhy256 cpu hcs12x v1 flash memory (ecc) 128kbytes 256 kbytes data ?sh (ecc) 8 kbytes ram 8 kbytes 12kbyte pin quantity 100 112 100 112 can 2 sci 2 spi 1 iic 1 timer 0 8 ch x 16-bit timer 1 8 ch x 16-bit pwm 8 ch x 8-bit or 4ch x16-bit adc (10-bit) 8 ch 12ch 8ch 12 ch stepper motor controller 4 stepper stall detecter 4 lcd driver (fpxbp) 38x4 40x4 38x4 40x4 key wakeup pins 23 25 23 25 frequency modu- lated pll yes external osc (4?6 mhz pierce with loop control) yes
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 15 1.2.2 chip-level features on-chip modules available within the family include the following features: cpu12xv1 cpu core up to 256 kbyte on-chip ?sh with ecc 8kbyte data ?sh with ecc up to 12kbyte on-chip sram phase locked loop (ipll) frequency multiplier with internal ?ter 4?6 mhz amplitude controlled pierce oscillator two timer modules (tim0 and tim1) supporting input/output channels that provide a range of 16- bit input capture, output compare, counter and pulse accumulator functions pulse width modulation (pwm) module with up to 8 x 8-bit channels up to 12-channel, 10-bit resolution successive approximation analog-to-digital converter (atd) up to 40x4 lcd driver pwm motor controller (mc) with up to 16 high current drivers output slew rate control on motor driver pad one serial peripheral interface (spi) module one inter-ic bus interface (iic) module two serial communication interface (sci) module supporting lin communications two multi-scalable controller area network (mscan) module (supporting can protocol 2.0a/b) on-chip voltage regulator (vreg) for regulation of input supply and all internal voltages autonomous periodic interrupt (api) stepper motor controller with up to drivers for up to 4 motors four stepper stall detector modules (one for each motor) up to 25 key wakup inputs 1.3 module features the following sections provide more details of the modules implemented on the mc9s12xhy family. internal 1 mhz rc osc no supply voltage 4.5 v ?5.5 v rti, lvi, crg, rst, cop, dbg, por, api yes execution speed static-40mhz table 1-1. mc9s12xhy family feature mc9s12xhy128 mc9s12xhy256
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 16 freescale semiconductor 1.3.1 s12 16-bit central processor unit (cpu) the cpu12x is a high-speed, 16-bit processing unit that has a programming model identical to that of the industry standard m68hc11 central processor unit (cpu). upward compatible with s12 instruction set, with the exception of ve fuzzy instructions (mem, wav, wavr, rev, revw) which have been removed enhanced indexed addressing access to large data segments independent of ppage 1.3.2 on-chip flash with ecc on-chip ?sh memory on the mc9s12xhy features the following: up to 256kbyte of program ?sh memory 64data bits plus 8 syndrome ecc (error correction code) bits allow single bit error correction and double fault bit detection erase sector size 1024bytes automated program and erase algorithm protection scheme to prevent accidental program or erase security option to prevent unauthorized access sense-amp margin level setting for reads 8kbyte data ?sh space 16 data bits plus 6 syndrome ecc (error correction code) bits allow single bit error correction and double fault detection erase sector size 256 bytes automated program and erase algorithm 1.3.3 on-chip sram up to 12kbytes of general-purpose ram 1.3.4 main external oscillator (xosc) loop control pierce oscillator using a 4 mhz to 16 mhz crystal current gain control on amplitude output signal with low harmonic distortion low power good noise immunity eliminates need for external current limiting resistor transconductance sized for optimum start-up margin for typical crystals
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 17 1.3.5 internal phase-locked loop (ipll) phase-locked-loop clock frequency multiplier no external components required reference divider and multiplier allow large variety of clock rates automatic bandwidth control mode for low-jitter operation automatic frequency lock detector con?urable option to spread spectrum for reduced emc radiation (frequency modulation) 1.3.6 clocks and reset generation(crg) cop watchdog real time interrupt clock monitor fast wake up from stop in self clock mode 1.3.7 system integrity support power-on reset (por) system reset generation illegal address detection with reset low-voltage detection with interrupt or reset real time interrupt (rti) computer operating properly (cop) watchdog con?urable as window cop for enhanced failure detection initialized out of reset using option bits located in ?sh memory clock monitor supervising the correct function of the oscillator temperature sensor 1.3.8 timer (tim0) 8x 16-bit channels for input capture 8x 16-bit channels for output compare 16-bit free-running counter with 8-bit precision prescaler 1 x 16-bit pulse accumulator 1.3.9 timer (tim1) 8x 16-bit channels for input capture 8x 16-bit channels for output compare
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 18 freescale semiconductor 16-bit free-running counter with 8-bit precision prescaler 1 x 16-bit pulse accumulator 1.3.10 liquid crystal display driver (lcd) con?urable for up to 40 frontplanes and 4 backplanes or general-purpose input or output 5 modes of operation allow for different display sizes to meet application requirements unused frontplane and backplane pins can be used as general-purpose i/o 1.3.11 motor controller (mc) pwm motor controller (mc) with up to 16 high current drivers each pwm channel switchable between two drivers in an h-bridge configuration left, right and center aligned outputs support for sine and cosine drive dithering output slew rate control 1.3.12 pulse width modulation module (pwm) 8channel x 8-bit or 4channel x 16-bit pulse width modulator programmable period and duty cycle per channel center-aligned or left-aligned outputs programmable clock select logic with a wide range of frequencies 1.3.13 inter-ic bus module (iic) 1 inter-ic (iic) bus module which has following feature multi-master operation soft programming for one of 256 different serial clock frequencies general call(broadcast) mode support 10-bit address support 1.3.14 controller area network module (mscan) 1 mbit per second, can 2.0 a, b software compatible standard and extended data frames 0? bytes data length programmable bit rate up to 1 mbps five receive buffers with fifo storage scheme three transmit buffers with internal prioritization flexible identi?r acceptance ?ter programmable as:
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 19 2 x 32-bit 4 x 16-bit 8 x 8-bit wakeup with integrated low pass ?ter option loop back for self test listen-only mode to monitor can bus bus-off recovery by software intervention or automatically 16-bit time stamp of transmitted/received messages 1.3.15 serial communication interface module (sci) full-duplex or single-wire operation standard mark/space non-return-to-zero (nrz) format selectable irda 1.4 return-to-zero-inverted (rzi) format with programmable pulse widths 13-bit baud rate selection programmable character length programmable polarity for transmitter and receiver active edge receive wakeup break detect and transmit collision detect supporting lin 1.3.16 serial peripheral interface module (spi) con?urable 8- or 16-bit data size full-duplex or single-wire bidirectional double-buffered transmit and receive master or slave mode msb-?st or lsb-?st shifting serial clock phase and polarity options 1.3.17 analog-to-digital converter module (atd) up to 12-channel, 10-bit analog-to-digital converter 3 us single conversion time 8-/10 bit resolution left or right justi?d result data internal oscillator for conversion in stop modes wakeup from low power modes on analog comparison > or <= match continuous conversion mode multiple channel scans pins can also be used as digital i/o
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 20 freescale semiconductor 1.3.18 on-chip voltage regulator (vreg) linear voltage regulator with bandgap reference low-voltage detect (lvd) with low-voltage interrupt (lvi) power-on reset (por) circuit low-voltage reset (lvr) 1.3.19 background debug (bdm) background debug module (bdm) with single-wire interface non-intrusive memory access commands supports in-circuit programming of on-chip nonvolatile memory 1.3.20 debugger (dbg) three comparators a, b, c, and d to monitor cpu buses trace buffer with depth of 64 entries comparator a and c compares full address bus and 16-bit data bus with mask register three modes: simple address/data match, inside address range, or outside address range 1.3.21 ssd programmable full step state programmable integration polarity blanking (recirculation) state 16-bit integration accumulator register 16-bit modulus down counter with interrupt multiplex two stepper motors 1.3.22 int (interrupt module) seven levels of nested interrupts flexible assignment of interrupt sources to each interrupt level. external non-maskable high priority interrupt (xirq) the following inputs can act as wake-up interrupts irq and non-maskable xirq can receive pins sci receive pins depending on the package option up to 25 pins on ports r, s, t and ad, con?urable as rising or falling edge sensitive
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 21
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 22 freescale semiconductor 1.4 block diagram figure 1-1 shows a block diagram of the mc9s12xhy-family devices figure 1-1. mc9s12xhy-family 112 lqfp block diagram 12k/8k bytes ram reset extal xtal 8k bytes data flash bkgd vddr periodic interrupt clock monitor single-wire background test voltage regulator debug module atd multilevel interrupt module ptad(kwu) sci0 ss sck mosi miso spi an[7:0] pad[11:0] 10-bit 12-channel analog-digital converter tim1 asynchronous serial if 8-bit 8channel pulse width modulator pwm irq xirq eclk pa 4 pa 3 pa 2 pa 1 pa 0 pa 7 pa 6 pa 5 pta 256k/128k bytes flash cpu12x-v1 amplitude controlled low power pierce or full drive pierce oscillator cop watchdog pll with frequency modulation option debug module 3 address breakpoints 1 data breakpoints 64 byte trace buffer reset generation and test entry rxd txd pr3 pr0 pr1 pr2 ptr(kwu) pr4 pr5 synchronous serial if auto. periodic int. pt3 pt0 pt1 pt2 ptt(kwu) pt7 pt4 pt5 pt6 pp3 pp0 pp1 pp2 ptp pp7 pp4 pp5 pwm3 pwm0 pwm1 pwm2 pwm4 pwm5 pwm6 ioc1_3 ioc1_0 ioc1_1 ioc1_2 ioc1_7 ioc1_4 ioc1_5 ioc1_6 vdda/vrh vssa/vrl vddx/vssx vddm2/vssm2 5v io supply vss3 vsspll pp6 pwm7 vddm1/vssm1 pu4 pu3 pu2 pu1 pu0 pu7 pu6 pu5 ptu motor driver0 pv4 pv3 pv2 pv1 pv0 pv7 pv6 pv5 ptv motor driver1 motor driver2 motor driver3 pb3 pb0 pb1 pb2 ptb pb4 pb5 ph3 ph0 ph1 ph2 40 x 4 lcd display ph4 ph5 iic sda scl ph6 ph7 vlcd pr6 pr7 ps3 ps0 ps1 ps2 pts(kwu) ps4 ps5 ps6 ps7 pb6 pb7 pth tim0 ioc0_3 ioc0_0 ioc0_1 ioc0_2 ioc0_7 ioc0_4 ioc0_5 ioc0_6 vdda/vssa can0 rxcan txcan mscan 2.0b sci1 asynchronous serial if rxd txd can1 rxcan txcan mscan 2.0b pm3 pm0 pm1 pm2 ptm vdd vddf vddpll ssd 0 ssd 1 ssd 2 ssd 3
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 23 1.5 device memory map table 1-2 shows the device register memory map. table 1-2. device register memory map address module size (bytes) reference pages 0x0000?x0009 pim (port integration module ) 10 768 0x000a?x000b mmc (memory map control) 2 769 0x000c?x000d pim (port integration module) 2 769 0x000e?x000f reserved 2 0x0010?x0017 mmc (memory map control) 8 769 0x0018?x0019 reserved 2 0x001a?x001b device id register 2 770 0x001c?x001f pim (port integration module) 4 770 0x0020?x002f dbg (debug module) 16 771 0x0030?x0033 reserved 4 0x0034?x003f ecrg (clock and reset generator) 12 772 0x0040?x006f tim0 (timer module) 48 773 0x0070?x009f atd (analog-to-digital converter 10 bit 8-channel) 48 775 0x00a0?x00c7 pwm (pulse-width modulator 8 channels) 40 776 0x00c8?x00cf sci0 (serial communications interface) 8 778 0x00d0?x00d7 sci1 (serial communications interface) 8 779 0x00d8?x00df spi (serial peripheral interface) 8 779 0x00e0?x00e7 iic (inter ic bus) 8 780 0x00e8?x00ff reserved 24 0x0100?x0113 ftmr control registers 20 781 0x0114?x011f reserved 12 0x0120-0x012f int (interrupt module) 16 782 0x0130?x013f reserved 16 0x0140?x017f can0 64 783 0x0180?x01bf can1 64 785 0x1c0?x1ff mc(motor controller) 64 786 0x0200?x021f lcd 32 788 0x0220?x0227 stepper stall detector 0 (ssd0) 8 789 0x0228?x022f stepper stall detector 1 (ssd1) 8 790 0x0230?x0237 stepper stall detector 2 (ssd2) 8 790 0x0238?x023f stepper stall detector 3 (ssd3) 8 791
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 24 freescale semiconductor note reserved register space shown in table 1-2 is not allocated to any module. this register space is reserved for future use. writing to these locations have no effect. read access to these locations returns zero. figure 1-2 shows mc9s12xhy family cpu and bdm local address translation to the global memory map. it indicates also the location of the internal resources in the memory map. accessing the reserved area in the range of 0x0c00 to 0x0fff will return unde?ed data values. a cpu access to any unimplemented space causes an illegal address reset. the range between 0x10_0000 and 0x13_ffff is mapped to dflash (data flash). the dflash block sizes are listed in table 1-3 . 0x0240?x029f pim (port integration module) 96 791 0x02a0?x02cf tim1(timer module) 48 795 0x02d0?x02ef reserved 32 0x02f0?x02f7 voltage regulator 8 797 0x02f8?x02ff reserved 8 0x0300?x03ff reserved 256 0x0400?x07ff reserved 1024 address module size (bytes) reference pages
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 25 table 1-3. derivative dependent memory parameters of device internal resources device flash_low size/ ppage (1) 1. number of 16k pages addressable via ppage register ram_low size/ rpage (2) 2. number of 4k pages addressing the ram. df_high size/ epage (3) 3. number of 1k pages addressing the dflash s12xhy256 0x7c_0000 256k / 16 0x0f_d000 12k / 3 0x10_1fff 8k / 8 s12xhy128 0x7e_0000 128k / 8 0x0f_e000 8k / 2 0x10_1fff 8k / 8
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 26 freescale semiconductor figure 1-2. mc9s12xhy-family global memory map 0x7f_ffff 0x00_0000 0x13_ffff 0x0f_ffff dflash ram 0x00_07ff rpage ppage 0x3f_ffff cpu and bdm local memory map flash flashsize unimplemented flash 0xffff vectors 0xc000 0x8000 unpaged 0x4000 0x1000 0x0000 16k flash window 0x2000 0x0800 8k ram 4k ram window 2k registers 16k flash unpaged 16k flash 2k registers unimplemented ram unimplemented space ram_low flash_low ramsize df_high dflash resources reserved epage 1k dflash window 0x0c00
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 27 note mc9s12xhy-family memory map is difference with mcu9s12hy64 family device 1.6 part id assignments the part id is located in two 8-bit registers partidh and partidl (addresses 0x001a and 0x001b). the read-only value is a unique part id for each revision of the chip. table 1-4 shows the assigned part id number and mask set number. the version id in table 1-4. is a word located in a ?sh information row at address 0x40_00e8. the version id number indicates a speci? version of internal nvm controller. 1.7 signal description this section describes signals that connect off-chip. it includes a pinout diagram, a table of signal properties, and detailed discussion of signals. it is built from the signal description sections of the individual ip blocks on the device. 1.7.1 device pinout table 1-4. assigned part id numbers device mask set number part id (1) 1. the coding is as follows: bit 15-12: major family identi?r bit 11-6: minor family identi?r bit 5-4: major mask set revision number including fab transfers bit 3-0: minor ?non full ?mask set revision version id mc9s12xhy256 0m23y $e010 $ffff mc9s12xhy128 0m23y $e010 $ffff
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 28 freescale semiconductor figure 1-3. mc9s12xhy-family 112 lqfp pinout ph7 /fp26 ph6 /fp25 vddpll xtal extal vsspll vss3 vddr ph5 /fp24 ph4 /fp23 vddx1 vssx1 pm3 /pwm7 /ioc1_3 pm2 /pwm6 /ioc1_2 pm1 /pwm5 /ioc0_3 /txd1 pm0 /pwm4 /ioc0_2 /rxd1 vss1 vddf ph3 / ss/ fp22 ph2 /eclk /sck /fp21 ph1 /mosi /txd1 /fp20 ph0 /miso /rxd1 /fp19 pr6 /scl /fp18 pr5 /sda /fp17 pt7 /ioc0_7 /kwt7 /fp16 pt6 /ioc0_6 /kwt6 /fp15 pt5 /ioc0_5 /kwt5 /fp14 pt4 /ioc0_4 /kwt4 /fp13 pad04 /an04 /kwad4 pad03 /an03 /kwad3 pad02 /an02 /kwad2 pad01 /an01 /kwad1 pad00 /an00 /kwad0 vdda /vrh vssa /vrl bkgd /modc vlcd pb7 /bp3 pb6 /bp2 pb5 /bp1 pb4 /bp0 vdd vss2 pb3 /fp39 pb2 /fp38 pb1 /fp37 pa7 /fp36 pa6 /fp35 pa5 /fp34 pa4 /fp33 pa3 /api_extclk /xclks /fp32 pa2 /fp31 pa1 / xirq /fp30 pa0 / irq /fp29 pb0 /fp28 pr7 /fp27 kwad5 /an05 /pad05 kwad6 /an06 /pad06 kwad7 /an07 /pad07 an08 /pad08 an09 /pad09 an10 /pad10 an11 /pad11 test m0cosm /m0c0m /ioc0_0 /pu0 m0cosp /m0c0p /pu1 m0sinm /m0c1m /ioc0_1 /pu2 m0sinp /m0c1p /pu3 vddm1 vssm1 m1cosm /m1c0m /ioc0_2 /pu4 m1cosp /m1c0p /pu5 m1sinm /m1c1m /ioc0_3 /pu6 m1sinp /m1c1p /pu7 m2cosm /m2c0m /ioc0_4 /ioc1_0 /scl /pwm4 /miso /pv0 m2cosp /m2c0p /mosi /pwm5 /pv1 m2sinm /m2c1m /ioc0_5 /ioc1_1 /sck /pwm6 /pv2 m2sinp /m2c1p /sda /pwm7 /ss /pv3 vddm2 vssm2 m3cosm /m3c0m /ioc0_6 /ioc1_2 /pv4 m3cosp /m3c0p /pv5 m3sinm /m3c1m /ioc0_7 /ioc1_3 /pv6 m3sinp /m3c1p /pv7 fp0 /pwm0 /pp0 fp1 /pwm1 /pp1 fp2 /pwm2 /pp2 fp3 /pwm3 /pp3 fp4 /pwm4 /pp4 fp5 /pwm5 /pp5 fp6 /pwm6 /pp6 fp7 /pwm7 /pp7 kwr2 /ioc1_6 /pr2 kwr3 /ioc1_7 /pr3 rxd0 /pwm6 /ps0 txd0 /pwm7 /ps1 vssx2 vddx2 kws2 /rxcan0 /pwm4 /ps2 kws3 /txcan0 /pwm5 /ps3 kwr0 /rxcan1 /ioc0_6 /pr0 kwr1 /txcan1 /ioc0_7 /pr1 miso /scl /pwm0 /ps4 kws5 /mosi /pwm1 /ps5 kws6 /sck /pwm2 /ps6 ss /sda /pwm3 /ps7 reset fp8 /kwt0 /ioc1_4 /pt0 fp9 /kwt1 /ioc1_5 /pt1 fp10 /kwt2 /ioc1_6 /pt2 fp11 /kwt3 /ioc1_7 /pt3 fp12 /kwr4 /pr4 pins shown in bold are not available on the 100 lqfp package mc9s12xhy-family 112lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 29 figure 1-4. mc9s12xhy-family 100lqfp pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pr7 /fp27 ph7 /fp26 ph6 /fp25 vddpll xtal extal vsspll vss3 vddr ph5 /fp24 ph4 /fp23 vddx1 vssx1 vss1 vddf ph3 / ss/ fp22 ph2 /eclk /sck /fp21 ph1 /mosi / txd1 /fp20 ph0 /miso / rxd1 /fp19 pr6 /scl /fp18 pr5 /sda /fp17 pt7 /ioc0_7 /kwt7 /fp16 pt6 /ioc0_6 /kwt6 /fp15 pt5 /ioc0_5 /kwt5 /fp14 pt4 /ioc0_4 /kwt4 /fp13 fp1 /pwm1 /pp1 fp2 /pwm2 /pp2 fp3 /pwm3 /pp3 fp4 /pwm4 /pp4 fp5 /pwm5 /pp5 fp6 /pwm6 /pp6 fp7 /pwm7 /pp7 rxd0 /pwm6 /ps0 txd0 /pwm7 /ps1 vssx2 vddx2 kws2 /rxcan0 / pwm4 /ps2 kws3 /txcan0 / pwm5 /ps3 kwr0 / rxcan1 /ioc0_6 /pr0 kwr1 / txcan1 /ioc0_7 /pr1 miso /scl /pwm0 /ps4 kws5 /mosi /pwm1 /ps5 kws6 /sck /pwm2 /ps6 ss /sda /pwm3 /ps7 reset fp8 /kwt0 /ioc1_4 /pt0 fp9 /kwt1 /ioc1_5 /pt1 fp10 /kwt2 /ioc1_6 /pt2 fp11 /kwt3 /ioc1_7 /pt3 fp12 / kwr4 /pr4 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 mc9s12xhy-family 100 lqfp kwad5 /an05 /pad05 kwad6 /an06 /pad06 kwad7 /an07 /pad07 test m0cosm /m0c0m /ioc0_0 /pu0 m0cosp /m0c0p /pu1 m0sinm /m0c1m /ioc0_1 /pu2 m0sinp /m0c1p /pu3 vddm1 vssm1 m1cosm /m1c0m /ioc0_2 /pu4 m1cosp /m1c0p /pu5 m1sinm /m1c1m /ioc0_3 /pu6 m1sinp /m1c1p /pu7 m2 cosm/m2c0m/ioc0_4/ioc1_0/scl/pwm4/miso/pv0 m2cosp /m2c0p /mosi /pwm5 /pv1 m2sinm /m2c1m /ioc0_5 /ioc1_1 /sck /pwm6 /pv2 m2sinp /m2c1p /sda /pwm7 /ss /pv3 vddm2 vssm2 m3cosm /m3c0m /ioc0_6 /ioc1_2 /pv4 m3cosp /m3c0p /pv5 m3sinm /m3c1m /ioc0_7 /ioc1_3 /pv6 m3sinp /m3c1p /pv7 fp0 /pwm0 /pp0 pad04 /an04 /kwad4 pad03 /an03 /kwad3 pad02 /an02 /kwad2 pad01 /an01 /kwad1 pad00 /an00 /kwad0 vdda /vrh vssa /vrl bkgd /modc vlcd pb7 /bp3 pb6 /bp2 pb5 /bp1 pb4 /bp0 vdd vss2 pb1 /fp37 pa7 /fp36 pa6 /fp35 pa5 /fp34 pa4 /fp33 pa3 /api_extclk /xclks /fp32 pa2 /fp31 pa1 / xirq /fp30 pa0 / irq /fp29 pb0 /fp28
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 30 freescale semiconductor 1.7.2 pin assignment overview table 1-5 provides a summary of which ports are available for each package option. routing of pin functions is summarized in table 1-6 . table 1-5. port availability by package option port 112 lqfp 100 lqfp port ad/adc channels 12/12 8/8 port a 8 8 port b 8 6 port h 8 8 port p 8 8 port r 8 6 port s 8 8 port t 8 8 port u 8 8 port v 8 8 port m 4 0 sum of ports 88 76 i/o power pairs vddm/vssm 2/2 2/2 i/o power pairs vddx/vssx 2/2 2/2 i/o power pairs vdda/vssa (1) 1. vrh/vrl are sharing with vdda/vssa pins 1/1 1/1 vreg power pairs vddr/vss3 1/1 1/1 vdd/vss2 1/1 1/1 vddf/vssf 1/1 1/1 i/o power pair vddpll/vsspll 1/1 1/1 vlcd power 1 1 sum of power pins 19 19 osc pairs xtal/extal 1/1 1/1 other pins reset/test/bkgd 1/1/1 1/1/1
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 31 table 1-7 provides a pin out summary listing the availability and functionality of individual pins for each package option. table 1-6. peripheral - port routing options (1) iic tim0 [7:6] tim0 [5:4] tim0 [3:2] tim1 [7:6] tim1 [3:2] spi pwm [7:4] pwm [3:0] sci1 pr[6:5] o pv[3,0] o ps[7,4] x 2-23 pt[7:6] x 2-16 pr[1:0] o pv6,pv4 o pt[5:4] x 2-16 pv2,pv0 o pu6,pu4 x 2-72 pm[1:0] o pt[3:2] x 2-16 pr[3:2] o pv6,pv4 x 2-79 pm[3:2] o ps[7:4] x 2-23 pv[3:0] o ph[3:0] o pp[7:4] x 2-36 ps[1:0,3:2] o pv[3:0] o pm[3:0] o pp[3:0] x 2-37 ps[7:4] o ph[1:0] x 2-45 pm[1:0] o 1. ??denotes a possible rerouting under software control, ??denotes as default routing option
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 32 table 1-7. pin-out summary (1) package pin function power supply internal pull resistor description lq fp 100 lq fp 64 pin 2nd func. 3rd func . 4th func . 5th func . 6th func . 7th func . 8th func . ctrl reset state 1 1 pad05 an05 kwa d5 vdda perad dis- abled port ad i/o, analog input of atd, key wakeup 2 2 pad06 an06 kwa d6 vdda perad dis- abled port ad i/o, analog input of atd, key wakeup 3 3 pad07 an07 kwa d7 vdda perad dis- abled port ad i/o, analog input of atd, key wakeup 4 - pad08 an08 vdda perad dis- abled port ad i/o, analog input of at d 5 - pad09 an09 vdda perad dis- abled port ad i/o, analog input of at d 6 - pad10 an10 vdda perad dis- abled port ad i/o, analog input of at d 7 - pad11 an11 vdda perad dis- abled port ad i/o, analog input of at d 8 4 test vdda reset pin dow n test input 9 5 pu0 ioc0 _0 m0c 0m m0c osm vddm peru/p psu dis- abled port u i/o, motor0 coil nodes of mc,tim0 channel 10 6 pu1 m0c 0p m0c osp vddm peru/p psu dis- abled port u i/o, motor0 coil nodes of mc 11 7 pu2 ioc0 _1 m0c 1m m0si nm vddm peru/p psu dis- abled port u i/o, motor0 coil nodes of mc,tim0 channel 12 8 pu3 m0c 1p m0si np vddm peru/p psu dis- abled port u i/o, motor0 coil nodes of mc
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 33 13 9 vddm1 14 10 vssm1 15 11 pu4 ioc0 _2 m1c 0m m1c osm vddm peru/p psu dis- abled port u i/o, motor1 coil nodes of mc,tim0 channel 16 12 pu5 m1c 0p m1c osp vddm peru/p psu dis- abled port u i/o, motor1 coil nodes of mc 17 13 pu6 ioc0 _3 m1c 1m m1si nm vddm peru/p psu dis- abled port u i/o, motor1 coil nodes of mc,tim0 channel 18 14 pu7 m1c 1p m1si np vddm peru/p psu dis- abled port u i/o, motor1 coil nodes of mc 19 15 pv0 miso pw m4 scl ioc1 _0 ioc0 _4 m2c 0m m2c osm vddm perv/p psv dis- abled port v i/o, motor2 coil nodes of mc, miso of spi, scl of iic, pwm channel 4,tim0/1 channel 20 16 pv1 pwm5 mos i m2c 0p m2c osp vddm perv/p psv dis- abled port v i/o, motor2 coil nodes of mc, mosi of spi, pwm channel 5 21 17 pv2 pwm6 sck ioc1 _1 ioc0 _5 m2c 1m m2si nm vddm perv/p psv dis- abled port v i/o, motor2 coil nodes of mc, sck of spi, pwm channel 6,tim0/1 channel 22 18 pv3 ss pw m7 sda m2c 1p m2si np vddm perv/p psv dis- abled port v i/o, motor2 coil nodes of mc, ss of spi sda of iic, pwm channel 7 23 19 vddm2 24 20 vssm2 table 1-7. pin-out summary (1) package pin function power supply internal pull resistor description lq fp 100 lq fp 64 pin 2nd func. 3rd func . 4th func . 5th func . 6th func . 7th func . 8th func . ctrl reset state
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 34 25 21 pv4 ioc1 _2 ioc0 _6 m3c 0m m3c osm vddm perv/p psv dis- abled port v i/o, motor3 coil nodes of mc,tim0/1 chan- nel 26 22 pv5 m3c 0p m3c osp vddm perv/p psv dis- abled port v i/o, motor3 coil nodes of mc 27 23 pv6 ioc1 _3 ioc0 _7 m3c 1m m3si nm vddm perv/p psv dis- abled port v i/o, motor3 coil nodes of mc,tim0/1 chan- nel 28 24 pv7 m3c 1p m3si np vddm perv/p psv dis- abled port v i/o, motor3 coil nodes of mc 29 25 pp0 pwm0 fp0 vddx perp/p psp down port r i/o, timer1 channel, key wakeup 30 26 pp1 pwm1 fp1 vddx perp/p psp down port r i/o, timer1 channel, key wakeup 31 27 pp2 pwm2 fp2 vddx perp/p psp down port p i/o, lcd frontplane driver, pwm channel 32 28 pp3 pwm3 fp3 vddx perp/p psp down port p i/o, lcd frontplane driver, pwm channel 33 29 pp4 pwm4 fp4 vddx perp/p psp down port p i/o, lcd frontplane driver, pwm channel 34 30 pp5 pwm5 fp5 vddx perp/p psp down port p i/o, lcd frontplane driver, pwm channel 35 31 pp6 pwm6 fp6 vddx perp/p psp down port p i/o, lcd frontplane driver, pwm channel 36 32 pp7 pwm7 fp7 vddx perp/p psp down port p i/o, lcd frontplane driver, pwm channel table 1-7. pin-out summary (1) package pin function power supply internal pull resistor description lq fp 100 lq fp 64 pin 2nd func. 3rd func . 4th func . 5th func . 6th func . 7th func . 8th func . ctrl reset state
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 35 37 - pr2 ioc1_ 6 kwr 2 vddx perr/p psr down port r i/o, timer1 channel, key wakeup 38 - pr3 ioc1_ 7 kwr 3 vddx perr/p psr down port r i/o, timer1 channel, key wakeup 39 33 ps0 pwm6 rxd 0 vddx pers/p pss up port s i/o, rxd of sci0, pwm channel6 40 34 ps1 pwm7 txd 0 vddx pers/p pss up port s i/o, txd of sci0, pwm channel 7 41 35 vssx2 42 36 vddx2 43 37 ps2 pwm4 rxc an0 kws 2 vddx pers/p pss up port s i/o, pwm channel 4,rx of can0 , key wakeup 44 38 ps3 pwm5 txc an0 kws 3 vddx pers/p pss up port s i/o,pwm channel 5, tx of can0 , key wakeup 45 39 pr0 ioc0_ 6 rxc an1 kwr 0 vddx perr/p psr down port r i/o, timer0 chan- nel,rx of can1,key wakeup 46 40 pr1 ioc0_ 7 txc an1 kwr 1 vddx perr/p psr down port r i/o, timer0 chan- nel,tx of can1 ,key wakeup 47 41 ps4 pwm0 scl mis o vddx pers/p pss up port s i/o, miso of spi, scl of iic, pwm channel 0 48 42 ps5 pwm1 mos i kws 5 vddx pers/p pss up port s i/o, mosi of spi, pwm channel 1, key wakeup table 1-7. pin-out summary (1) package pin function power supply internal pull resistor description lq fp 100 lq fp 64 pin 2nd func. 3rd func . 4th func . 5th func . 6th func . 7th func . 8th func . ctrl reset state
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 36 49 43 ps6 pwm2 sck kws 6 vddx pers/p pss up port s i/o, sck of spi, pwm channel2 , key wakeup 50 44 ps7 pwm3 sda ss vddx pers/p pss up port s i/o, ss of spi, sda of iic, pwm channel 3 51 45 reset vddx pullup external reset 52 46 pt0 ioc1_ 4 kwt 0 fp8 vddx pert/p pst down port t i/o, lcd frontplane driver, timer1 channel, key wakeup 53 47 pt1 ioc1_ 5 kwt 1 fp9 vddx pert/p pst down port t i/o, lcd frontplane driver, timer1 channel, key wakeup 54 48 pt2 ioc1_ 6 kwt 2 fp10 vddx pert/p pst down port t i/o, lcd frontplane driver, timer1 channel, key wakeup 55 49 pt3 ioc1_ 7 kwt 3 fp11 vddx pert/p pst down port t i/o, lcd frontplane driver, timer1 channel, key wakeup 56 50 pr4 kwr4 fp12 vddx perr/p psr down port r i/o, lcd frontplane driver , key wakeup 57 51 pt4 ioc0_ 4 kwt 4 fp13 vddx pert/p pst down port t i/o, lcd frontplane driver, timer0 channel, key wakeup 58 52 pt5 ioc0_ 5 kwt 5 fp14 vddx pert/p pst down port t i/o, lcd frontplane driver, timer0 channel, key wakeup table 1-7. pin-out summary (1) package pin function power supply internal pull resistor description lq fp 100 lq fp 64 pin 2nd func. 3rd func . 4th func . 5th func . 6th func . 7th func . 8th func . ctrl reset state
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 37 59 53 pt6 ioc0_ 6 kwt 6 fp15 vddx pert/p pst down port t i/o, lcd frontplane driver, timer0 channel,key wakeup 60 54 pt7 ioc0_ 7 kwt 7 fp16 vddx pert/p pst down port t i/o, lcd frontplane driver, timer0 channel, key wakeup 61 55 pr5 sda fp17 vddx perr/p psr down port r i/o, lcd frontplane driver, sda of iic 62 56 pr6 scl fp18 vddx perr/p psr down port r i/o, lcd frontplane driver, scl of iic 63 57 ph0 miso rxd 1 fp19 vddx perh/p psh down port h i/o, lcd frontplane driver, miso of spi, rxd of sci1 64 58 ph1 mosi txd 1 fp20 vddx perh/p psh down port hi/o, lcd frontplane driver, mosi of spi ,txd of sci1 65 59 ph2 eclk sck fp21 vddx perh/p psh down port hi/o, lcd frontplane driver, sck of spi, bus clock output 66 60 ph3 ss fp22 vddx perh/p psh down port h i/o, lcd frontplane driver, ss of spi 67 61 vddf 0 68 62 vss1 0 69 - pm0 pwm4 ioc0 _2 rxd 1 vddx perm/p psm up port m i/o, pwm channel4 , timer0 channe 2, rxd of sci1 table 1-7. pin-out summary (1) package pin function power supply internal pull resistor description lq fp 100 lq fp 64 pin 2nd func. 3rd func . 4th func . 5th func . 6th func . 7th func . 8th func . ctrl reset state
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 38 70 - pm1 pwm5 ioc0 _3 txd 1 vddx perm/p psm up port m i/o, pwm channel5 , timer0 channe 3, txd of sci1 71 - pm2 pwm6 ioc1 _2 vddx perm/p psm up port m i/o, pwm channel6 , timer1 channe 2 72 - pm3 pwm7 ioc1 _3 vddx perm/p psm up port m i/o, pwm channel7 , timer1 channe 3 73 63 vssx1 74 64 vddx1 75 65 ph4 fp23 vddx perh/p psh down port hi/o, lcd frontplane driver 76 66 ph5 fp24 vddx perh/p psh down port h i/o, lcd frontplane driver 77 67 vddr 78 68 vss3 79 69 vss- pll 80 70 extal vddp ll osci0llator pin 81 71 xtal vddp ll osci0llator pin 82 72 vddpl l table 1-7. pin-out summary (1) package pin function power supply internal pull resistor description lq fp 100 lq fp 64 pin 2nd func. 3rd func . 4th func . 5th func . 6th func . 7th func . 8th func . ctrl reset state
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 39 83 73 ph6 fp25 vddx perh/p psh down port h i/o, lcd frontplane driver 84 74 ph7 fp26 vddx perh/p psh down port h i/o, lcd frontplane driver 85 75 pr7 fp27 vddx perr/p psr down port r i/o, lcd frontplane driver 86 76 pb0 fp28 vddx pucr down port b i/o, lcd frontplane driver 87 77 pa0 irq fp29 vddx pucr down port a i/o, lcd frontplane driver, api output 88 78 pa1 xirq fp30 vddx pucr down port a i/o, lcd frontplane driver 89 79 pa2 fp31 vddx pucr down port a i/o, lcd frontplane driver 90 80 pa3 api_e xtcl k xcl ks fp32 vddx pucr down port a i/o, lcd frontplane driver 91 81 pa4 fp33 vddx pucr down port a i/o, lcd frontplane driver 92 82 pa5 fp34 vddx pucr down port a i/o, lcd frontplane driver 93 83 pa6 fp35 vddx pucr down port a i/o, lcd frontplane driver 94 84 pa7 fp36 vddx pucr down port a i/o, lcd frontplane driver table 1-7. pin-out summary (1) package pin function power supply internal pull resistor description lq fp 100 lq fp 64 pin 2nd func. 3rd func . 4th func . 5th func . 6th func . 7th func . 8th func . ctrl reset state
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 40 95 85 pb1 fp37 vddx pucr down port bi/o, lcd frontplane driver 96 - pb2 fp38 vddx pucr down port b i/o, lcd frontplane driver 97 - pb3 fp39 vddx pucr down port b i/o, lcd frontplane driver 98 86 vss2 99 87 vdd 100 88 pb4 bp0 vddx pucr down port b i/o, lcd backplane driver 101 89 pb5 bp1 vddx pucr down port b i/o, lcd backplane driver 102 90 pb6 bp2 vddx pucr down port b i/o, lcd backplane driver 103 91 pb7 bp3 vddx pucr down port b i/o, lcd backplane driver 104 92 vlcd vddx voltage reference pin for the lcd driver. 105 93 bkgd modc vddx always on up background debug, mode selection pin 106 94 vssa vrl 107 95 vdda vrh 108 96 pad00 an00 kwa d0 vdda perad dis- abled port ad i/o, analog input of atd, key wakeup table 1-7. pin-out summary (1) package pin function power supply internal pull resistor description lq fp 100 lq fp 64 pin 2nd func. 3rd func . 4th func . 5th func . 6th func . 7th func . 8th func . ctrl reset state
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 41 note for devices assembled in 100-pin package all non-bonded out pins should be con?ured as outputs after reset in order to avoid current drawn from ?ating inputs. refer to table 1-7 for affected pins. 109 97 pad01 an01 kwa d1 vdda perad dis- abled port ad i/o, analog input of atd, key wakeup 110 98 pad02 an02 kwa d2 vdda perad dis- abled port ad i/o, analog input of atd, key wakeup 111 99 pad03 an03 kwa d3 vdda perad dis- abled port ad i/o, analog input of atd, key wakeup 112 10 0 pad04 an04 kwa d4 vdda perad dis- abled port ad i/o, analog input of atd, key wakeup 1. table shows a superset of pin functions. not all functions are available on all derivatives 2. when routing the iic to pr/ph port, in order to overwrite the internal pull-down during reset, the external iic pull-up resi stor should be < =4.7k 3. when irq/xirq is enabled, the internal pulldown function will be disabled, the external pullup resistor is required table 1-7. pin-out summary (1) package pin function power supply internal pull resistor description lq fp 100 lq fp 64 pin 2nd func. 3rd func . 4th func . 5th func . 6th func . 7th func . 8th func . ctrl reset state
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 42 freescale semiconductor 1.7.3 detailed signal descriptions 1.7.3.1 extal, xtal ?oscillator pins extal and xtal are the crystal driver and external clock pins. on reset all the device clocks are derived from the internal reference clock. xtal is the oscillator output. 1.7.3.2 reset ?external reset pin the reset pin is an active low bidirectional control signal. it acts as an input to initialize the mcu to a known start-up state, and an output when an internal mcu function causes a reset. the reset pin has an internal pull-up device. 1.7.3.3 test ?test pin this input only pin is reserved for factory test. this pin has an internal pull-down device. note the test pin must be tied to v ssa in all applications. 1.7.3.4 bkgd / modc ?background debug and mode pin the bkgd/modc pin is used as a pseudo-open-drain pin for the background debug communication. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modc bit at the rising edge of reset. the bkgd pin has an internal pull-up device. 1.7.3.5 pad[7:0] / an[7:0] / kwad[7:0]?port ad input pins of atd [7:0] pad[7:0] are a general-purpose input or output pins and analog inputs an[7:0] of the analog-to-digital converter atd. they can be con?ured as keypad wakeup inputs. 1.7.3.6 pa[7:4] / fp[36:33]?port a i/o pins [7:4] pa[7:4] are a general-purpose input or output pins. they can be con?ured as frontplane segment driver outputs fp[36:33]. 1.7.3.7 pa[3:2] / api_extclk / xclks / fp[32:31]?port a i/o pins [3:2] pa[3:2] are a general-purpose input or output pins. they can be con?ured as frontplane segment driver outputs fp[32:31]. pa3 can also be con?ure as api_extclk.the xclks is an input signal which controls whether a crystal in combination with the internal loop controlled pierce oscillator is used or whether full swing pierce oscillator/external clock circuitry is used (refer to section 1.16, ?scillator con?uration ). an internal pull-down is enabled during reset.
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 43 1.7.3.8 pa1 / xirq / fp[30]?port a i/o pin 1 pa1 is a general-purpose input or output pin. it can be con?ured as frontplane segment driver outputs fp[30]. it also provide the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. the xirq interrupt is level sensitive and active low. as xirq is level sensitive, while this pin is low the mcu will not enter stop mode. after reset, the xirq default is not enabled. 1.7.3.9 pa0 / irq / fp[29]?port a i/o pin 0 pa0 is a general-purpose input or output pin. it can be con?ured as frontplane segment driver outputs fp[29].tthe maskable interrupt request input that provides a means of applying asynchronous interrupt requests. 1.7.3.10 pb[7:4] / bp[3:0] ?port b i/o pins [7:4] pb[7:4] are a general-purpose input or output pins. they can be con?ured as backplane segment driver output bp[3:0]. 1.7.3.11 pb[3:0] / fp[39:37,28] ?port b i/o pins [3:0] pb[3:0] are a general-purpose input or output pins. they can be con?ured as frontplane segment driver output fp[ 39:37,28 ]. 1.7.3.12 ps7 / pwm3 / sda / ss ?port s i/o pin 7 ps7 is a general-purpose input or output pin. it can be con?ured as the slave selection pin ss for the serial peripheral interface (spi). it can be con?ured as the serial data pin sda as iic module. it can be con?ured as pwm channel 3. 1.7.3.13 ps6 / pwm2 / sck / kws6 ?port s i/o pin 6 ps6 is a general-purpose input or output pin. it can be con?ured as the serial clock sck of the serial peripheral interface (spi). it can be con?ured as pwm channel 2. it can be con?ured as keypad wakeup input. 1.7.3.14 ps5 / pwm1 / mosi / kws5 ?port s i/o pin 5 ps5 is a general-purpose input or output pin. it can be con?ured as the master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface (spi). it can be con?ured as pwm channel1. it can con?ured as keypad wakeup input. 1.7.3.15 ps4 / pwm0 / scl / miso ?port s i/o pin 4 ps4 is a general-purpose input or output pin. it can be con?ured as the master input (during master mode) or slave output pin (during slave mode) miso for the serial peripheral interface (spi).it can be con?ured as the serial clock pin scl as iic module.it can be con?ured as pwm channel0
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 44 freescale semiconductor 1.7.3.16 ps3 / pwm5 / txcan / kws3 ?port s i/o pin 3 ps3 is a general-purpose input or output pin. it can be con?ured as the transmit pin txcan of the scalable controller area network controller (can). it can be con?ured as pwm channel5. it can con?ured as keypad wakeup input. 1.7.3.17 ps2 / pwm4 / rxcan / kws2 ?port s i/o pin 2 ps3 is a general-purpose input or output pin. it can be con?ured as the receive pin rxcan of the scalable controller area network controller (can). it can be con?ured as pwm channel4. it can con?ured as keypad wakeup input. 1.7.3.18 ps1 / pwm7 / txd ?port s i/o pin 1 ps1 is a general-purpose input or output pin. it can be con?ured as the transmit pin txd of serial communication interface(sci). it can be con?ured as pwm channel 7. 1.7.3.19 ps0 / pwm6 / rxd ?port s i/o pin 0 ps0 is a general-purpose input or output pin. it can be con?ured as the receive pin rxd of serial communication interface(sci). it can be con?ured as pwm channel 6. 1.7.3.20 pr7 / fp[27] ?port r i/o pin 7 pr7 is a general-purpose input or output pin. it can be con?ured as frontplane segment driver output fp[27]. 1.7.3.21 pr6 / scl / fp[18]?port r i/o pin 6 pr6 is a general-purpose input or output pin. it can be con?ured as frontplane segment driver output fp[18]. it can be con?ured as the serial clock pin scl of iic. 1.7.3.22 pr5 / sda / fp[17]?port r i/o pin 5 pr5 is a general-purpose input or output pin. it can be con?ured as frontplane segment driver output fp[17]. it can be con?ured as the serial data pin sda of iic. 1.7.3.23 pr4 / kwr4 / fp[12] ?port r i/o pin 4 pr4 is a general-purpose input or output pin. it can be con?ured as frontplane segment driver output fp[12].they can be con?ured as keypad wakeup inputs. 1.7.3.24 pr[3:2] / ioc1[7:6] / kwr[3:2] ?port r i/o pins [3:2] pr[3:2] are a general-purpose input or output pins. they can be con?ured as timer (tim1) channel 7-6. they can be con?ured as keypad wakeup inputs.
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 45 1.7.3.25 pr1 / ioc0_7 / txcan1 / kwr1 ?port r i/o pins 1 pr[1:0] are a general-purpose input or output pins. they can be con?ured as timer (tim0) channel 7-6. it can be con?ured as the transmit pin txcan of the scalable controller area network controller (can1).they can be con?ured as keypad wakeup inputs. 1.7.3.26 pr0 / ioc0_6 / rxcan1 / kwr0 ?port r i/o pins 0 pr[1:0] are a general-purpose input or output pins. they can be con?ured as timer (tim0) channel 7-6. it can be con?ured as the receive pin rxcan of the scalable controller area network controller (can1).they can be con?ured as keypad wakeup inputs. 1.7.3.27 pp[7:0] / pwm[7:0] / fp[7:0] ?port p i/o pins [7:0] pp[7:0] are a general-purpose input or output pins. they can be con?ured as frontplane segment driver output fp[7:0]. they can be con?ured as pulse width modulator (pwm) channel 7-0 output. 1.7.3.28 ph[7:4] / fp[26:23] ?port h i/o pins [7:4] ph[7:4] are a general-purpose input or output pins. they can be con?ured as frontplane segment driver output fp[26:23]. 1.7.3.29 ph3 / ss / fp[22]?port h i/o pin 3 ph3 is a general-purpose input or output pin. it can be con?ured as frontplane segment driver output fp[22]. it can be con?ured as the slave selection pin ss for the serial peripheral interface (spi). 1.7.3.30 ph2 / eclk / sck / fp[21] ?port h i/o pin 2 ph2 is a general-purpose input or output pin. it can be con?ured as frontplane segment driver output fp[21]. it can be con?ured as the serial clock sck of the serial peripheral interface (spi). it can be con?ured to drive the internal bus clock eclk. eclk can be used as a timing reference. the eclk output has a programmable prescaler. 1.7.3.31 ph1 / mosi / txd1 / fp[20] ?port h i/o pin 1 ph1 is a general-purpose input or output pin. it can be con?ured as frontplane segment driver output fp[20]. it can be con?ured as the master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface (spi).it can be con?ured as the transmitpin txd of serial communication interface(sci1). 1.7.3.32 ph0 / miso / rxd1 / fp[19] ?port h i/o pin 0 ph0 is a general-purpose input or output pin. it can be con?ured as frontplane segment driver output fp[19]. it can be con?ured as the master input (during master mode) or slave output pin (during slave mode) miso for the serial peripheral interface (spi).it can be con?ured as the receive pin rxd of serial communication interface(sci1).
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 46 freescale semiconductor 1.7.3.33 pt[7:4] / ioc0[7:4] / kwt[7:4] / fp[16:13] ?port t i/o pins [7:4] pt[7:4] are a general-purpose input or output pins. they can be con?ured as frontplane segment driver output fp[16:13]. they can be con?ured as timer (tim0) channel 7-4. they can be con?ured as key wakeup inputs. 1.7.3.34 pm3 / pmw7 / ioc1_3 ?port m i/o pins [3] pm3 is a general-purpose input or output pin. . it can be con?ured as timer (tim1) channels 3.it can be con?ured as pwm channel7. 1.7.3.35 pm2 / pmw6 / ioc1_2 ?port m i/o pins [2] pm2 is a general-purpose input or output pin. .it can be con?ured as timer (tim1) channels 2. it can be con?ured as pwm channel6. 1.7.3.36 pm1 / pmw5 / ioc0_3 / txd1?port m i/o pins [1] pm1 is a general-purpose input or output pin. it can be con?ured as the transmitpin txd of serial communication interface(sci). it can be con?ured as timer (tim0) channels 3.it can be con?ured as pwm channel5. 1.7.3.37 pm0 / pmw4 / ioc0_2 / rxd1?port m i/o pins [0] pm0 is a general-purpose input or output pin. it can be con?ured as the receive pin rxd of serial communication interface(sci).it can be con?ured as timer (tim0) channels 2. it can be con?ured as pwm channel4. 1.7.3.38 pt[3:0] / ioc1[7:4] /kwt [3:0] / fp[11:8] ?port t i/o pin [3:0] pt[3:0] are a general-purpose input or output pins. they can be con?ured as frontplane segment driver output fp[11:8]. they can be con?ured as timer (tim1) channels 7-4. they can be con?ured as key wakeup inputs. 1.7.3.39 pu[7] / m1c1p / m1sinp ?port u i/o pin [7] pu[7] is a general-purpose input or output pin. it can be configured as high current pwm output pin which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. the pin interfaces to the coils of motor 1. 1.7.3.40 pu[6] / ioc0_3 / m1c1m / m1sinm ?port u i/o pin [6] pu[6] is a general-purpose input or output pin. it can be configured as high current pwm output pin which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. the pin interfaces to the coils of motor 1. it can aslo be configured as timer (tim0) channel 3
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 47 1.7.3.41 pu[5] / m1c0p / m1cosp?port u i/o pin [5] pu[5] is a general-purpose input or output pin. it can be configured as high current pwm output pin which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. the pin interfaces to the coils of motor 1. 1.7.3.42 pu[4] / ioc0_2 / m1c0m / m1sinp?port u i/o pin [4] pu[4] is a general-purpose input or output pin. it can be configured as high current pwm output pin which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. the pin interfaces to the coils of motor 1. it can aslo be configured as timer (tim0) channel 2 1.7.3.43 pu[3] / m0c1p / m0sinp?port u i/o pin [3] pu[3] is a general-purpose input or output pin. it can be configured as high current pwm output pin which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. the pin interfaces to the coils of motor 0. 1.7.3.44 pu[2] / ioc0_1 / m0c1m / m0sinm ?port u i/o pin [2] pu[2] is a general-purpose input or output pin. it can be configured as high current pwm output pin which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. the pin interfaces to the coils of motor 0. it can aslo be configured as timer(tim0) channel 1 1.7.3.45 pu[1] / m0c0p / m0cosp?port u i/o pin [1] pu[1] is a general-purpose input or output pin. it can be configured as high current pwm output pin which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. the pin interfaces to the coils of motor 0. 1.7.3.46 pu[0] / ioc0_0 / m0c0m / m0cosm?port u i/o pin [0] pu[0] is a general-purpose input or output pin. it can be configured as high current pwm output pin which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. the pin interfaces to the coils of motor 0. it can aslo be configured as timer(tim0) channel 0 1.7.3.47 pv[7] / m3c1p / m3sinp?port v i/o pin [7] pv[7] is a general-purpose input or output pin. it can be configured as high current pwm output pin which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. the pin interfaces to the coils of motor 3. 1.7.3.48 pv[6] / ioc1_3 / ioc0_7 / m3c1m / m3sinm ?port v i/o pin [6] pv[6] is a general-purpose input or output pin. it can be configured as high current pwm output pin which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. the pin
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 48 freescale semiconductor interfaces to the coils of motor 3. it can aslo be configured as timer (tim1) channel 3 or timer (tim0) channel 7. 1.7.3.49 pv[5] / m3c0p / m3cosp ?port v i/o pin [5] pv[5] is a general-purpose input or output pin. it can be configured as high current pwm output pin which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. the pin interfaces to the coils of motor 3. 1.7.3.50 pv[4] / ioc1_2 / ioc0_6 / m3c0m / m3cosm ?port v i/o pin [4] pv[4] is a general-purpose input or output pin. it can be configured as high current pwm output pin which can be used for motor drive or to measure the back emf to calibrate the pointer reset position. the pin interfaces to the coils of motor 3. it can aslo be configured as timer (tim1) channel 2 or timer (tim0) channel 6. 1.7.3.51 pv3 / ss / pwm7 / sda / m2c1p / m2sinp ?port v i/o pin 3 pv3 is a general-purpose input or output pin. it can be con?ured as high current pwm output pin which can be used for motor driver or to measure the back emf to calibrate the pointer reset position. it interface to the coil of motor 2. it can be con?ured as the slave selection pin ss for the serial peripheral interface (spi). it can be con?ured as the serial data pin sda as iic module. it can be con?ured as pwm channel 7. 1.7.3.52 pv2 / pwm6 / sck / ioc1_1 / ioc0_5 / m2c1m / m2sinm port v i/o pin 2 pv2 is a general-purpose input or output pin. it can be con?ured as high current pwm output pin which can be used for motor driver or to measure the back emf to calibrate the pointer reset position. it interface to the coil of motor 2. it can be con?ured as timer(tim1) channel 1 or timer (tim0) channel 5. it can be con?ured as the serial clock sck of the serial peripheral interface (spi). it can be con?ured as pwm channel 6. 1.7.3.53 pv1 / pwm5 / mosi / m2c0p / m2cosp ?port v i/o pin 1 pv1 is a general-purpose input or output pin. it can be con?ured as high current pwm output pin which can be used for motor driver or to measure the back emf to calibrate the pointer reset position. it interface to the coil of motor 2. it can be con?ured as the master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface (spi). it can be con?ured as pwm channel 5. 1.7.3.54 pv0 / miso / pwm4 / scl / ioc1_0 / ioc0_4 / m2c0m / m2cosm port v i/o pin 0 pv0 is a general-purpose input or output pin. it can be con?ured as high current pwm output pin which can be used for motor driver or to measure the back emf to calibrate the pointer reset position. it interface to the coil of motor 2. it can be con?ured as timer (tim1) channel 0 or timer (tim0) channel 4. it can be con?ured as the master input (during master mode) or slave output pin (during slave mode) miso for the
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 49 serial peripheral interface (spi). it can be con?ured as the serial clock pin scl of iic module. it can be con?ured as pwm channel 4. 1.7.4 power supply pins mc9s12xhy-family power and ground pins are described below. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. note all v ss pins must be connected together in the application. 1.7.4.1 vddx[2:1] / vssx[2:1] ?power and ground pins for i/o drivers external power and ground for i/o drivers. bypass requirements depend on how heavily the mcu pins are loaded. all v ddx pins are connected together internally. all v ssx pins are connected together internally. 1.7.4.2 vddr ?power pin for internal voltage regulator power supply input to the internal voltage regulator. 1.7.4.3 vdd / vss2 / vss3 ?core power pins the voltage supply of nominally 1.8v is derived from the internal voltage regulator. the return current path is through the vss2 and vss3 pin. no static external loading of these pins is permitted. 1.7.4.4 vddf / vss1 ?nvm power pins the voltage supply of nominally 2.8 v is derived from the internal voltage regulator. the return current path is through the vss1 pin. no static external loading of these pins is permitted. 1.7.4.5 vdda / vssa ?power supply pins for atd and voltage regulator these are the power supply and ground input pins for the analog-to-digital converters and the voltage regulator. 1.7.4.6 vddpll / vsspll ?power supply pins for pll this pin provides operating voltage and ground for the oscillator and the phased-locked loop. the voltage supply of nominally 1.8v is derived from the internal voltage regulator. this allows the supply voltage to the oscillator and pll to be bypassed independently. this voltage is generated by the internal voltage regulator. no static external loading of these pins is permitted
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 50 freescale semiconductor 1.7.4.7 vdda/vrh / vssa/vrl ?power supply pins for atd and voltage regulator and atd reference voltage inputs these are the power supply and ground input pins for port ad io, the analog-to-digital converter and the voltage regulator. and also server as the reference voltage input pins for the analog-to-digital converter. 1.7.4.8 vddm[2:1] / vssm[2:1]?power supply pins for motor 0 to 3 external power supply pins for the port u and port v. vddm2 and vddm1 as well as vssm2 and vssm1 are internal connected together. 1.7.4.9 vlcd?power supply reference pin for lcd driver vlcd is the voltage reference pin for the lcd driver. adjusting the voltage on this pin will change the display contrast. 1.7.4.10 power and ground connection summary table 1-8. power and ground connection summary mnemonic nominal voltage description vddr 5.0 v external power supply to internal voltage regulator vddx[2:1] 5.0 v external power and ground, supply to pin drivers vssx[2:1] 0 v vdda/vrh 5.0 v operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the a/d to be bypassed independently.alsorreference voltages for the analog-to-digital converter. vssa/vrl 0 v vdd 1.8v internal power and ground generated by internal regulator for the internal core. vss1/vss2/ vss3 0v vddf 2.8v internal power and ground generated by internal regulator for the internal nvm. vddpll 1.8v provides operating voltage and ground for the phased-locked loop. this allows the supply voltage to the pll to be bypassed independently. internal power and ground generated by internal regulator. vsspll 0v vddm[2:1] 5.0 v external power and ground, supply to port u/v motor drivers vssm[2:1] 0 v vlcd 5.0 v external voltage reference for the lcd driver
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 51 1.8 system clock description for the lcd clk in table 1-8. lcd clock and frame frequency , it is always connected to the crg lcd clok output, which is from osc clock, see figure 7-16. system clocks generator .the clock and reset generator module (crg) provides the internal clock signals for the core and all peripheral modules. figure 1-5 shows the clock connections from the crg to all modules. consult the s12xecrg section for details on clock generation. note the xhy and xs family uses the xe family clock and reset generator module. therefore all crg references are related to s12xecrg. figure 1-5. clock connections the system clock can be supplied in several ways enabling a range of system operating frequencies to be supported: the on-chip phase locked loop (pll) sci0 . . sci 1 spi0 atd0 can0..can1 crg bus clock extal xtal core clock oscillator clock ram s12x flash mc tim pim lcd iic pwm ssd lcd clock
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 52 freescale semiconductor the pll self clocking the oscillator the clock generated by the pll or oscillator provides the main system clock frequencies core clock and bus clock. as shown in figure 1-5 , these system clocks are used throughout the mcu to drive the core, the memories, and the peripherals. the program flash memory is supplied by the bus clock and the oscillator clock. the oscillator clock is used as a time base to derive the program and erase times for the nvms. the can modules may be con?ured to have their clock sources derived either from the bus clock or directly from the oscillator clock. this allows the user to select its clock based on the required jitter performance. in order to ensure the presence of the clock the mcu includes an on-chip clock monitor connected to the output of the oscillator. the clock monitor can be con?ured to invoke the pll self-clocking mode or to generate a system reset if it is allowed to time out as a result of no oscillator clock being present. in addition to the clock monitor, the mcu also provides a clock quality checker which performs a more accurate check of the clock. the clock quality checker counts a predetermined number of clock edges within a de?ed time window to insure that the clock is running. the checker can be invoked following speci? events such as on wake-up or clock monitor failure. 1.9 modes of operation the mcu can operate in different modes. these are described in 1.9.1 chip con?uration summary . the mcu can operate in different power modes to facilitate power saving when full system performance is not required. these are described in 1.10.2 power modes low power operation . some modules feature a software programmable option to freeze the module status whilst the background debug module is active to facilitate debugging. 1.9.1 chip con?uration summary the different modes and the security state of the mcu affect the debug features (enabled or disabled). the operating mode out of reset is determined by the state of the modc signal during reset (see table 1-9 ). the modc bit in the mode register shows the current operating mode and provides limited mode
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 53 switching during operation. the state of the modc signal is latched into this bit on the rising edge of reset. 1.9.1.1 normal single-chip mode this mode is intended for normal device operation. the opcode from the on-chip memory is being executed after reset (requires the reset vector to be programmed correctly). the processor program is executed from internal memory. 1.9.1.2 special single-chip mode this mode is used for debugging single-chip operation, boot-strapping, or security related operations. the background debug module bdm is active in this mode. the cpu executes a monitor program located in an on-chip rom. bdm ?mware waits for additional serial commands through the bkgd pin. table 1-9. chip modes chip modes modc normal single chip 1 special single chip 0
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 54 freescale semiconductor 1.9.2 power modes the mcu features two main low-power modes. consult the respective section for module speci? behavior in system stop, system pseudo stop, and system wait mode. an important source of information about the clock system is the clock and reset generator section (crg). 1.9.2.1 system stop modes the system stop modes are entered if the cpu executes the stop instruction unless an nvm command is active. depending on the state of the pstp bit in the clksel register the mcu goes into pseudo stop mode or full stop mode. please refer to crg section. asserting reset, xirq, irq or any other interrupt that is not masked exits system stop modes. system stop modes can be exited by cpu activity, depending on the con?uration of the interrupt request. if the cpu executes the stop instruction whilst an nvm command is being processed, then the system clocks continue running until nvm activity is completed. if a non-masked interrupt occurs within this time then the system does not effectively enter stop mode although the stop instruction has been executed. 1.9.2.2 full stop mode the oscillator is stopped in this mode. by default all clocks are switched off and all counters and dividers remain frozen. the autonomous periodic interrupt (api) and atd module may be enabled to self wake the device. a fast wake up mode is available to allow the device to wake from full stop mode immediately on the pll internal clock without starting the oscillator clock. 1.9.2.3 pseudo stop mode in this mode the system clocks are stopped but the oscillator is still running and the real time interrupt (rti) and watchdog (cop), api and atd and lcd modules may be enabled. other peripherals are turned off. this mode consumes more current than system stop mode but, as the oscillator continues to run, the full speed wake up time from this mode is signi?antly shorter. 1.9.2.4 wait mode this mode is entered when the cpu executes the wai instruction. in this mode the cpu will not execute instructions. the internal cpu clock is switched off. all peripherals can be active in system wait mode. for further power consumption the peripherals can individually turn off their local clocks. asserting reset, xirq, irq or any other interrupt that is not masked ends system wait mode. 1.9.2.5 run mode although this is not a low-power mode, unused peripheral modules should not be enabled in order to save power.
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 55 1.9.3 freeze mode the timer module, pulse width modulator, and analog-to-digital converters provide a software programmable option to freeze the module status when the background debug module is active. this is useful when debugging application software. for detailed description of the behavior of the atd, tim, pwm when the background debug module is active consult the corresponding section. 1.10 security the mcu security mechanism prevents unauthorized access to the flash memory. refer to section 5.4.1 security and section 15.5 security 1.11 resets and interrupts consult the s12x cpu manual and the s12xint section for information on exception processing. note when referring to the s12xint section please be aware that the xhy family neither features an xgate nor an mpu module. 1.11.1 resets table 1-10. lists all reset sources and the vector locations. resets are explained in detail in the table 1-10. reset sources and vector locations vector address reset source ccr mask local enable $fffe power-on reset (por) none none $fffe low voltage reset (lvr) none none $fffe external pin reset none none $fffe illegal address reset none none $fffc clock monitor reset none pllctl(cme,scme) $fffa cop watchdog reset none cop rate select
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 56 freescale semiconductor 1.11.2 vectors table 1-11 lists all interrupt sources and vectors in the default order of priority. the interrupt module (see section chapter 4 interrupt (s12xintv2) ) provides an interrupt vector base register (ivbr) to relocate the vectors. table 1-11. interrupt vector locations (sheet 1 of 3) vector address (1) interrupt source ccr mask local enable vector base + $f8 unimplemented instruction trap none none vector base+ $f6 swi none none vector base+ $f4 xirq x bit irqcr (xirqen) vector base+ $f2 irq i bit irqcr (irqen) vector base+ $f0 real time interrupt i bit crgint (rtie) vector base+ $ee tim0 timer channel 0 i bit tim0tie (c0i) vector base + $ec tim0 timer channel 1 i bit tim0tie (c1i) vector base+ $ea tim0 timer channel 2 i bit tim0tie (c2i) vector base+ $e8 tim0 timer channel 3 i bit tim0tie (c3i) vector base+ $e6 tim0 timer channel 4 i bit tim0tie (c4i) vector base + $e4 tim0 timer channel 5 i bit tim0tie (c5i) vector base+ $e2 tim0 timer channel 6 i bit tim0tie (c6i) vector base+ $e0 tim0 timer channel 7 i bit tim0tie (c7i) vector base+ $de tim0 timer over?w i bit tim0tsrc2 (tof) vector base+ $dc tim0 pulse accumulator a over?w i bit tim0pactl (paovi) vector base + $da tim0 pulse accumulator input edge i bit tim0pactl (pai) vector base + $d8 spi i bit spicr1 (spie, sptie) vector base+ $d6 sci0 i bit sci0cr2 (tie, tcie, rie, ilie) vector base + $d4 sci1 i bit sci1cr2 (tie, tcie, rie, ilie) vector base + $d2 atd i bit atdctl2 (ascie) vector base + $d0 reserved vector base + $ce port ad i bit piead (piead7-piead0) vector base + $cc port r i bit pier (pier3-pier0) vector base + $ca port s i bit pies (pies6-pies5) vector base + $c8 reserved i bit vector base + $c6 crg pll lock i bit crgint(lockie) vector base + $c4 crg self-clock mode i bit crgint(scmie) vector base + $c2 reserved
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 57 vector base + $c0 iic bus i bit ibcr(ibie) vector base + $be to vector base + $bc reserved vector base + $ba flash fault detect i bit fcnfg2 (sfdie, dfdie) vector base + $b8 flash i bit fcnfg (ccie) vector base + $b6 can0 wake-up i bit canrier (wupie) vector base + $b4 can0 errors i bit canrier (cscie, ovrie) vector base + $b2 can0 receive i bit canrier (rxfie) vector base + $b0 can0 transmit i bit cantier (txeie[2:0]) vector base+ $ae tim1 timer channel 0 i bit tim1tie (c0i) vector base + $ac tim1 timer channel 1 i bit tim1tie (c1i) vector base+ $aa tim1 timer channel 2 i bit tim1tie (c2i) vector base+ $a8 tim1 timer channel 3 i bit tim1tie (c3i) vector base+ $a6 tim1 timer channel 4 i bit tim1tie (c4i) vector base + $a4 tim1 timer channel 5 i bit tim1tie (c5i) vector base+ $a2 tim1 timer channel 6 i bit tim1tie (c6i) vector base+ $a0 tim1 timer channel 7 i bit tim1tie (c7i) vector base+ $9e tim1 timer over?w i bit tim1tsrc2 (tof) vector base+ $9c tim1 pulse accumulator a over?w i bit tim1pactl (paovi) vector base + $9a tim1 pulse accumulator input edge i bit tim1pactl (pai) vector base+ $98 reserved vector base + $96 motor control timer over?w i-bit mcctl1 (mcocie) vector base + $94 to vector base + $90 reserved vector base + $8e port t i bit piet (piet7-piet0) vector base+ $8c pwm emergency shutdown i bit pwmsdn (pwmie) vector base + $8a ssd0 i bit mdc0ctl(mczie,aovie) vector base + $88 ssd1 i bit mdc1ctl(mczie,aovie) vector base + $86 ssd2 i bit mdc2ctl(mczie,aovie) vector base + $84 ssd3 i bit mdc3ctl(mczie,aovie) vector base + $82 reserved vector base + $80 low-voltage interrupt (lvi) i bit vregctrl (lvie) vector base + $7e autonomous periodical interrupt (api) i bit vregapictrl (apie) table 1-11. interrupt vector locations (sheet 2 of 3) vector address (1) interrupt source ccr mask local enable
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 58 freescale semiconductor 1.11.3 effects of reset when a reset occurs, mcu registers and control bits are initialized. refer to the respective block sections for register reset states. on each reset, the flash module executes a reset sequence to load flash configuration registers. 1.11.3.1 flash con?uration reset sequence phase on each reset, the flash module will hold cpu activity while loading flash module registers from the flash memory. if double faults are detected in the reset phase, flash module protection and security may be active on leaving reset. this is explained in more detail in the flash module section. vector base + $7c high temperature interrupt(hti) i bit vreghtcl (htie) vector base + $7a can1 wake-up i bit canrier (wupie) vector base + $78 can1 errors i bit canrier (cscie, ovrie) vector base + $76 can1 receive i bit canrier (rxfie) vector base + $74 can1 transmit i bit cantier (txeie[2:0]) vector base + $72 to vector base + $40 reserved vector base + $3e atd compare interrupt i bit atdctl2 (acmpie) vector base + $3c to vector base + $14 reserved vector base + $12 system call interrupt (sys) none vector base + $10 spurious interrupt none 1. 16 bits vector address based note 9s12hy64 family lvi/api/hti vector number is $8a-$86, while 9s12xhy256 is $80-$7c;9s12hy64 family atd compare interrupt number is $84, while 9s12hy64 family is $3e;9s12hy64 family has no sys vector; 9s12hy64 family spurious interrupt vector number is $80. table 1-11. interrupt vector locations (sheet 3 of 3) vector address (1) interrupt source ccr mask local enable
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 59 1.11.3.2 reset while flash command active if a reset occurs while any flash command is in progress, that command will be immediately aborted. the state of the word being programmed or the sector/block being erased is not guaranteed. 1.11.3.3 i/o pins refer to the pim section for reset con?urations of all peripheral module ports. 1.11.3.4 memory the ram arrays are not initialized out of reset. 1.12 cop con?uration the cop time-out rate bits cr[2:0] and the wcop bit in the copctl registerare loaded from the flash register fopt. see table 1-12 and table 1-13 for coding. the fopt register is loaded from the flash con?uration ?ld byte at global address 0x7_ff0e during the reset sequence. if the mcu is secured the cop time-out rate is always set to the longest period (cr[2:0] = 111) after any reset into special single chip mode.{mcu_9s12xhy256_cop_resetval.s} 1.13 atd external trigger input connection table 1-12. initial cop rate con?uration nv[2:0] in fopt register cr[2:0] in copctl register 000 111 001 110 010 101 011 100 100 011 101 010 110 001 111 000 table 1-13. initial wcop con?uration nv[3] in fopt register wcop in copctl register 10 01
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 60 freescale semiconductor the atd module includes external trigger inputs etrig[3:0]. the external trigger allows the user to synchronize atd conversion to external trigger events. table 1-14 shows the connection of the external trigger inputs. consult the atd section for information about the analog-to-digital converter module. references to freeze mode are equivalent to active bdm mode. 1.14 atd channel[17] connection further to the 12 externally available channels, atd0 features an extra channel[17] that is connected to the internal temperature sensor at device level. to access this channel atd must use the channel encoding sc:cd:cc:cb:ca = 1:0:0:0:1 in atdctl5. for more temperature sensor information, please refer to 1.15.1 temperature sensor con?uration . 1.15 vreg con?uration the device must be con?ured with the internal voltage regulator enabled. operation in conjunction with an external voltage regulator is not supported. the api trimming register apitr is loaded from the flash ifr option ?ld at global address 0x40_00f0 bits[5:0] during the reset sequence. currently factory programming of this ifr range is not supported. read access to reserved vreg register space returns ?? write accesses have no effect. this device does not support access abort of reserved vreg register space. 1.15.1 temperature sensor con?uration the vreg high temperature trimming register bits vreghttr[3:0] are loaded from the internal flash during the reset sequence. to use the high temperature interrupt within the speci?d limits (t htia and t htid ) these bits must be loaded with 0x8. currently factory programming is not supported. the device temperature can be monitored on atd0 channel[17]. the internal bandgap reference voltage can also be mapped to atd0 analog input channel[17]. the voltage regulator vsel bit when set, maps the bandgap and, when clear, maps the temperature sensor to atd0 channel[17]. table 1-14. atd external trigger sources external trigger input connectivity etrig0 pp1(pwm channel 1) (1) 1. when lcd segment output driver is enabled on pp1/pp3, the atd external trigger function will be unavailable etrig1 pp3(pwm channel 3) 1 etrig2 tim0 channel output 2 (2) 2. independ on the tim0ocpd3/2 bit setting etrig3 tim0 channel output 3 2
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 61 1.16 oscillator con?uration the xclks is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) pierce oscillator is used or whether full swing pierce oscillator/external clock circuitry is used. the xclks signal selects the oscillator con?uration during reset low phase while a clock quality check is ongoing. this is the case for: power on reset or low-voltage reset clock monitor reset any reset while in self-clock mode or full stop mode the selected oscillator con?uration is frozen with the rising edge of the reset pin in any of these above described reset cases. note unlike xs family, xclks signal is applied in mc9s12xhy family instead of xclks in xs family figure 1-6. loop controlled pierce oscillator connections (xclks = 0) mcu extal xtal v sspll crystal or ceramic resonator c 2 c 1
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 62 freescale semiconductor figure 1-7. full swing pierce oscillator connections (xclks = 1) figure 1-8. external clock connections (xclks = 1) 1.17 documentation note the terms s12p, s12x , s12hy,s12xhy and s12s which appear in some of the following chapters refer to the original architecture which those modules were designed to work with. please do not confuse them with the s12xhy product families. s12xhy will support only 10-bit atd resolution, although in atd12b block it still has the 12-bit descriptions. ssd block says one ssd can be con?ed to control two motors, while in chip level, this feature is not supported. mcu extal xtal r s r b v sspll crystal or ceramic resonator c 2 c 1 r b =1m ? ; r s speci?d by crystal vendor mcu extal xtal cmos-compatible external oscillator not connected
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 63 revision history version number revision date author description of changes rev0.07 jul-29-2009 daniel add ssd pin de?es update typo rev0.08 jul-30-2009 daniel update pim rev0.09 oct-30-2009 daniel update table 1-2., ?evice register memory map , 0x0400-0x07ff is reserved update section figure 1-2., ?c9s12xhy-family global memory map update section table 1-5., ?ort availability by package option for sum of power pins rev0.10 nov-11-2009 daniel update section table 1-5., ?ort availability by package option ,vdd/vss2 ? section 1.7.4.4, ?ddf / vss1 ?nvm power pins ? section 1.7.4.5, ?dda / vssa ?power supply pins for atd and voltage regulator update section figure 1-5., ?lock connections , add lcd clock, add ssd iic mc ? section table 1-2., ?evice register memory map , ssd name update table 1-1 ,bus speed is 40mhz update 1.8 system clock description , for lcd clock rev0.11 jun-03-2010 daniel update table 1-7., ?in-out summary , reset state of pin reset ? 1.12, ?op con?uration , fopt address is 0x7_ff0e rev0.12 nov-16-2010 daniel fix typo of table 1-2./1-23 , size of moudle int is 16, 0x130~ is 16 update table 1-1./1-14 ,all parts has 2x mscan and sci
device overview mc9s12xhy-family mc9s12xhy-family reference manual, rev. 1.01 64 freescale semiconductor
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 65 chapter 2 port integration module (s12xhypimv1) revision history version number revision date effective date author description of changes 0.01 18 may 2009 initial version 0.02 8 jun 2009 add pin routing of ioc0[7:4] to pv( table 2-1 ) add port m to pin functions in table 2-1 ? typo 0.03 9 jun 2009 remove womm in register map table 2-2./2-74 update link in register map table 2-2./2-74 perm reserved bit reset value is 0 in 2.3.18/2-96 0.04 10 jun 2009 update by stevens review on v0.01 0.05 23 jun 2009 update by team review based on ver0.04 update pwm re-route ptrrh&ptrrl 0.06 25 jun 2009 change ioc re-route on pm to pu/pv. sci re-route on pm to ph 0.07 29 jul 2009 update by team review add ssd pin functions in pinmap update wire-or options on port m 0.08 30 jul 2009 ?, add ioc1_1 ioc1_0 to table 2-1., ?in functions and priorities ?, add ioc0_7 to 2.3.89, ?ort v data register (ptv) 0.09 27 oct 2009 fix wong ?ure name in section 2.3.54, ?ort h routing register (pthrr) remove reduded drive strength descript in section 2.1.2, ?eatures update ranget for section 2.3.9, ?im reserved register ? table 2-2 , add pttrr{7:4] ? table/?ure name table 2-58 , table 2-59 , figure 2-70 , figure 2-71 ? table/?ure name table 2-62 , figure 2-75 update womm[1:0] at figure 2-34 , figure 2-2 , figure 2-80 update figure 2-80 ,reduced drive,routing,wire-or ? table 2-38 , un-hidepmm5:4] routing ? table 2-95 , port name for glitch
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 66 freescale semiconductor 2.1 introduction 2.1.1 overview the s12xhy family port integration module establishes the interface between the peripheral modules and the i/o pins for all ports. it controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins. this document covers: port a associated with the xlks, irq, xirq interrupt inputs and api_extclk. also associated with the lcd driver output port b used as general purpose i/o and lcd driver output(including bp and fp pins) port r associated with 2 timer module - port 4:0 inputs can be used as an external interrupt source.also associated with the lcd driver output. pr also associated with the iic and can1 port t associated with 2 timer module. also associated with the lcd driver output. it can be used as external interrupt source port s associated with 1 spi module, 1 sci module, 1 iic module and 1 mscan, and pwm. port 6-5and 3-2 can be used as an external interrupt source. port p connected to the pwm, also associated with lcd driver output port h associated with 1 spi, 1 sci. also associated with lcd driver output port m associated with sci1 pwm and tim port ad associated with one 12-channel atd module. it an be used as an external interrupt source port u/v associated with the motor driver output. also pv3-0 associated with 1 spi, 1 iic and 4 pwm channels. pu0/pu2/pu4/pu6 and pv0/pv2/pv4/pv6 associated with tim0 channels 0 -3 and tim1 channels 0 -3 most i/o pins can be con?ured by register bits to select data direction, to enable and select pull-up or pull-down devices. port u/v have register bits to select the slew rate control. note this document assumes the availability of all features (112-pin package option). some functions are not available on lower pin count package options. refer to the pin-out summary section. 0.10 03 jun 2010 ? on page 2-146 , no open drain output when portv route to iic ? table 2-1., ?in functions and priorities , pm[1:0] connect to sci 0.11 15 nov 2010 add nclkx2 bit on eclkctl register 2.3.10/2-91 ? typo,it is ptim and ptm 2.3.16/2-95 remove reduced drive at section 2.4.2.4 and 2.3.2/2-84 ? table table 2-1./2-67 , pm[1:0] is for txd/rxd ? table table 2-16./2-97 , pttrr[4], pt4 instead of pt6 version number revision date effective date author description of changes
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 67 2.1.2 features the port integration module includes these distinctive registers: data registers and data direction registers for ports a, b, h, t, s, p, r, m,u, v and ad when used as general purpose i/o control registers to enable/disable pull devices and select pull-ups/pull-downs on ports h, t, s, p, r,m, u and v on per-pin basis control registers to enable/disable pull-up devices on port ad on per-pin basis single control register to enable/disable pull-down on ports a and b, on per-port basis and single control register to enable/disable pull-up on bkgd pin control registers to enable/disable open-drain (wired-or) mode on ports h, r,m and s.control register to enable/disable slew rate control on port u and port v interrupt ?g register for pin interrupts on ports r, port s, port t and ad control register to con?ure irq/xirq pin operation routing register to support module port relocation free-running clock outputs a standard port pin has the following minimum features: input/output selection 5v output drive 5v digital and analog input input with selectable pull-up or pull-down device optional features supported on dedicated pins: open drain for wired-or connections interrupt inputs with glitch filtering the output slew rate control 2.2 external signal description this section lists and describes the signals that do connect off-chip. table 2-1 shows all the pins and their functions that are controlled by the port integration module. note if there is more than one function associated with a pin, the priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority). table 2-1. pin functions and priorities port pin name pin function & priority 1 i/o description pin function after reset - bkgd modc 2 i modc input during reset bkgd bkgd i/o bdm communication pin
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 68 freescale semiconductor ad pad[11:0] an[11:0] i atd analog gpio kwad[7:0] i key wakeup gpio i/o general purpose a pa[7:4] fp[36:33] o lcd frontplane segment driver output gpio gpio i/o general purpose pa[3] fp[32] o lcd frontplane segment driver output api_extclk o api output gpio i/o general purpose pa[2] fp[31] o lcd frontplane segment driver output gpio i/o general purpose pa[1] fp[30] o lcd frontplane segment driver output xirq i non-maskable level-sensitive interrupt gpio i/o general purpose pa[0] fp[29] o lcd frontplane segment driver output irq i maskable level or falling edge-sensitive interrupt gpio i/o general purpose b pb[7:4] bp[3:0] o lcd backplane segment driver output gpio gpio i/o general purpose pb[3:0] fp[39:37,28] o lcd frontplane segment driver output gpio i/o general purpose port pin name pin function & priority 1 i/o description pin function after reset
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 69 h ph[7:4] fp[26:23] o lcd frontplane segment driver output gpio gpio i/o general purpose ph[3] fp[22] o lcd frontplane segment driver output ss i/o ss of spi, mappable through software gpio i/o general purpose ph[2] fp[21] o lcd frontplane segment driver output sck i/o sck of spi, mappable through software eclk o free-running clock at bus clock rate or programmable down-scaled bus clock gpio i/o general purpose ph[1] fp[20] o lcd frontplane segment driver output txd1 i/o serial communication interface(sci1) transmit pin mosi i/o mosi of spi, mappable through software gpio i/o general purpose ph[0] fp[19] o lcd frontplane segment driver output rxd1 i/o serial communication interface(sci1) receive pin miso i/o miso of spi, mappable through software gpio i/o general purpose m pm[3:2] ioc1[3:2] i/o tim1 channel [3:2], mappable through software gpio pwm[7:6] i/o pulse width modulator channel 7 - 6 gpio i/o general purpose pm[1] txd1 o txd of sci1 ioc0[3] i/o tim0 channel [3], mappable through software pwm[5] i/o pulse width modulator channel 5 gpio i/o general purpose pm[0] rxd1 i rxd of sci1 ioc0[2] i/o tim0 channel [2], mappable through software pwm[4] i/o pulse width modulator channel 4 gpio i/o general purpose p pp[7:0] fp[7:0] o lcd frontplane segment driver output gpio pwm[7:0] i/o pulse width modulator channel 7 - 0 gpio i/o general purpose port pin name pin function & priority 1 i/o description pin function after reset
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 70 freescale semiconductor r pr[7] fp[27] i lcd frontplane segment driver output gpio gpio i/o general purpose pr[6] fp[18] i lcd frontplane segment driver output scl i/o scl of iic, mappable through software gpio i/o general purpose pr[5] fp[17] i lcd frontplane segment driver output sda i/o sda of iic, mappable through software gpio i/o general purpose pr[4] fp[12] i lcd frontplane segment driver output kwr4 i key wakeup gpio i/o general purpose pr[3:2] kwr[3:2] i key wakeup ioc1[7:6] i/o tim1 channel, mappable through software gpio i/o general purpose pr[1] kwr[1] i key wakeup txcan1 o tx of can1 ioc0[7] i/o tim0 channel, mappable through software gpio i/o general purpose pr[0] kwr[0] i key wakeup rxcan1 i rx of can1 ioc0[6] i/o tim0 channel, mappable through software gpio i/o general purpose port pin name pin function & priority 1 i/o description pin function after reset
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 71 s ps7 ss i/o ss of spi gpio sda i/o sda of iic pwm3 o pwm channel 3, mappable through software gpio i/o general purpose ps6 kws[6] i key wakeup sck i/o sck of spi pwm2 o pwm channel 2, mappable through software gpio i/o general purpose ps5 kws[5] i key wakeup mosi i/o mosi of spi pwm1 o pwm channel 1, mappable through software gpio i/o general purpose ps4 miso i/o miso of spi scl i/o scl of iic pwm0 o pwm channel 0, mappable through software gpio i/o general purpose ps3 txcan0 o tx of can0 kws3 i key wakeup pwm5 o pwm channel 5, mappable through software gpio i/o general purpose ps2 rxcan0 i rx of can0 kws2 i key wakeup pwm4 o pwm channel 4, mappable through software gpio i/o general purpose ps1 txd0 i/o serial communication interface(sci0) transmit pin pwm7 i/o pwm channel 7, mappable through software gpio i/o general purpose ps0 rxd0 i/o serial communication interface(sci0) receive pin pwm6 o pwm channel 6, mappable through software gpio i/o general purpose t pt[7:4] fp[16:13] o lcd segment driver output gpio kwt[7:4] i key wakeup ioc0[7:4] i/o timer0 channels 7-4 gpio i/o general purpose pt[3:0] fp[11:8] o lcd segment driver output kwt[3:0] i key wakeup ioc1[7:4] i/o timer1 channels 7-4 gpio i/o general purpose port pin name pin function & priority 1 i/o description pin function after reset
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 72 freescale semiconductor u pu[7] m1sinp i/o ssd1 sine+ node gpio m1c1p o motor control output for motor 1 gpio i/o general purpose pu[6] m1sinm i/o ssd1 sine- node m1c1m o motor control output for motor 1 ioc0_3 i/o tim0 channel 3 gpio i/o general purpose pu[5] m1cosp i/o ssd1 cosine+ node m1c0p o motor control output for motor 1 gpio i/o general purpose pu[4] m1cosm i/o ssd1 cosine- node m1c0m o motor control output for motor 1 ioc0_2 i/o tim0 channel2 gpio i/o general purpose pu[3] m0sinp i/o ssd0 sine+ node m0c1p o motor control output for motor 0 gpio i/o general purpose pu[2] m0sinm i/o ssd0 sine- node m0c1m o motor control output for motor 0 ioc0_1 i/o tim0 channel 1 gpio i/o general purpose pu[1] m0cosp i/o ssd0 cosine+ node m0c0p o motor control output for motor 0 gpio i/o general purpose pu[0] m0cosm i/o ssd0 cosine- node m0c0m o motor control output for motor 0 ioc0_0 i/o tim0 channel 0 gpio i/o general purpose port pin name pin function & priority 1 i/o description pin function after reset
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 73 v pv[7] m3sinp i/o ssd3 sine+ node gpio m3c1p o motor control output for motor 3 gpio i/o general purpose pv[6] m3sinm i/o ssd3 sine- node m3c1m o motor control output for motor 3 ioc0_7 i/o tim0 channel 7 ioc1_3 i/o tim1 channel 3 gpio i/o general purpose pv[5] m3cosp i/o ssd3 cosine+ node m3c0p o motor control output for motor 3 gpio i/o general purpose pv[4] m3cosm i/o ssd3 cosine- node m3c0m o motor control output for motor 3 ioc0_6 i/o tim0 channel 6 ioc1_2 i/o tim1 channel 2 gpio i/o general purpose pv3 m2sinp i/o ssd2 sine+ node m2c1p o motor control output for motor 2 sda i/o sda of iic, mappable through software pwm7 i/o pwm channel 7, mappable through software ss i/o ss of spi, mappable through software gpio i/o general purpose pv2 m2sinm i/o ssd2 sine- node m2c1m o motor control output for motor 2 ioc0_5 i/o tim0 channel 5 ioc1_1 i/o tim1 channel 1 sck i/o sck of spi, mappable through software pwm6 i/o pwm channel 6, mappable through software gpio i/o general purpose pv1 m2cosp i/o ssd2 cosine+ node m2c0p o motor control output for motor 2 mosi i/o mosi of spi, mappable through software pwm5 o pwm channel 5, mappable through software gpio i/o general purpose pv0 m2cosm i/o ssd2 cosine- node m2c0m o motor control output for motor 2 ioc0_4 i/o tim0 channel 4 ioc1_0 i/o tim1 channel 0 scl i/o scl of iic, mappable through software pwm4 o pwm channel 4, mappable through software miso i/o miso of spi, mappable through software port pin name pin function & priority 1 i/o description pin function after reset
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 74 freescale semiconductor 2.3 memory map and register de?ition this section provides a detailed description of all port integration module registers. 2.3.1 memory map table 2-2 shows the register map of the port integration module. 1 signals in brackets denote alternative module routing pins. 2 function active when reset asserted. table 2-2. block memory map port offset or address register access reset value section/page a b 0x0000 porta?ort a data register r/w 0x00 2.3.3/2-86 0x0001 portb?ort b data register r/w 0x00 2.3.4/2-87 0x0002 ddra?ort a data direction register r/w 0x00 2.3.5/2-87 0x0003 ddrb?ort b data direction register r/w 0x00 2.3.6/2-88 0x0004 : : 0x0009 pim reserved r 0x00 2.3.9/2-90 0x000a : 0x000b non-pim address range 1 - - - a b 0x000c pucr?ull-up up control register r/w 2 0x43 2.3.8/2-89 0x000d pim reserved r/w 0x00 2.3.9/2-90 0x000e : 0x001b non-pim address range 1 - - - 0x001c eclkctl?clk control register r/w 0x80 2.3.10/2-91 0x001d pim reserved r 0x00 2.3.11/2-91 0x001e irqcr?rq control register r/w 2 0x00 2.3.12/2-92 0x001f pim reserved r 0x00 2.3.13/2-92 0x0020 : 0x023f non-pim address range 1 - - -
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 75 t 0x0240 ptt?ort t data register r/w 0x00 2.3.14/2-93 0x0241 ptit?ort t input register r 3 2.3.15/2-94 0x0242 ddrt?ort t data direction register r/w 0x00 2.3.16/2-95 0x0243 pim reserved r/w 0x00 2.3.34/2-109 0x0244 pert?ort t pull device enable register r/w 0xff 2.3.18/2-96 0x0245 ppst?ort t polarity select register r/w 0xff 2.3.19/2-96 0x0246 pim reserved r 0x00 2.3.38/2-111 0x0247 pttrr?port t routing register r/w 0x00 2.3.21/2-97 s 0x0248 pts?ort s data register r/w 0x00 2.3.22/2-98 0x0249 ptis?ort s input register r 3 2.3.23/2-100 0x024a ddrs?ort s data direction register r/w 0x00 2.3.24/2-101 0x024b pim reserved r/w 0x00 2.3.25/2-102 0x024c pers?ort s pull device enable register r/w 0xff 2.3.26/2-103 0x024d ppss?ort s polarity select register r/w 0x00 2.3.27/2-103 0x024e woms?ort s wired-or mode register r/w 0x00 2.3.28/2-104 0x024f ptsrr?port s routing register r/w 0x00 2.3.29/2-104 m 0x0250 ptm?ort m data register r/w 0x00 2.3.31/2-106 0x0251 ptim?ort m input register r 3 2.3.32/2-107 0x0252 ddrm?ort m data direction register r/w 0x00 2.3.16/2-95 0x0253 pim reserved r/w 0x00 2.3.42/2-113 0x0254 perm?ort m pull device enable register r/w 0xff 2.3.18/2-96 0x0255 ppsm?ort m polarity select register r/w 0x00 2.3.19/2-96 0x0256 womm?ort mwired-or mode register r/w 0x00 2.3.38/2-111 0x0257 pim reserved r/w 0x00 2.3.21/2-97 p 0x0258 ptp?ort p data register r/w 0x00 2.3.39/2-111 0x0259 ptip?ort p input register r 3 2.3.40/2-112 0x025a ddrp?ort p data direction register r/w 0x00 2.3.41/2-112 0x025b pim reserved r/w 0x00 2.3.42/2-113 0x025c perp?ort p pull device enable register r/w 0xff 2.3.43/2-113 0x025d ppsp?ort p polarity select register r/w 0xff 2.3.44/2-114 0x025e ptprrh?port p routing register high r/w 0x00 2.3.45/2-114 0x025f ptprrl?port p routing register low r/w 0x00 2.3.46/2-115 table 2-2. block memory map (continued) port offset or address register access reset value section/page
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 76 freescale semiconductor h 0x0260 pth?ort h data register r/w 0x00 2.3.47/2-116 0x0261 ptih?ort h input register r 3 2.3.48/2-118 0x0262 ddrh?ort h data direction register r/w 0x00 2.3.49/2-118 0x0263 pim reserved r/w 0x00 2.3.50/2-120 0x0264 perh?ort h pull device enable register r/w 0xff 2.3.51/2-120 0x0265 ppsh?ort h polarity select register r/w 0xff 2.3.52/2-120 0x0266 womh?ort h wired-or mode register r/w 0x00 2.3.53/2-121 0x0267 pthrr?port h routing register r 0x00 2.3.54/2-122 0x0268 : 0x026f pim reserved r 0x00 2.3.55/2-122 ad 0x0270 pt0ad?ort ad data register r 0x00 2.3.56/2-123 0x0271 pt1ad?ort ad data register r/w 0x00 2.3.56/2-123 0x0272 ddr0ad - port ad data direction register r 0x00 2.3.58/2-124 0x0273 ddr1ad - port ad data direction register r/w 0x00 2.3.58/2-124 0x0274 pim reserved r 0x00 2.3.60/2-125 0x0275 pim reserved r/w 0x00 2.3.42/2-113 0x0276 per0ad?ort ad pull up enable register r 0x00 2.3.62/2-126 0x0277 per1ad?ort ad pull up enable register r/w 0x00 2.3.62/2-126 0x0278 : 0x027f pim reserved r 0x00 2.3.64/2-127 r 0x0280 ptr?ort r data register r/w 0x00 2.3.65/2-127 0x0281 ptir?ort r input register r 3 2.3.66/2-129 0x0282 ddrr?ort r data direction register r/w 0x00 2.3.67/2-130 0x0283 pim reserved r/w 0x00 2.3.68/2-131 0x0284 perr?ort r pull device enable register r/w 0xff 2.3.69/2-131 0x0285 ppsr?ort r polarity select register r/w 0xff 2.3.70/2-132 0x0286 womr?ort r wired-or mode register r/w 0x00 2.3.71/2-132 0x0287 pim reserved r 0x00 2.3.72/2-133 table 2-2. block memory map (continued) port offset or address register access reset value section/page
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 77 key wak eup 0x0288 piet?ort t interrupt enable register r/w 0x00 2.3.73/2-133 0x0289 pift?ort t interrupt flag register r/w 0x00 2.3.74/2-134 0x028a pies?ort s interrupt enable register r/w 0x00 2.3.75/2-134 0x028b pifs?ort s interrupt flag register r/w 0x00 2.3.76/2-135 0x028c pie1ad?ort ad interrupt enable register r/w 0x00 2.3.77/2-135 0x028d pif1ad?ort ad interrupt flag register r/w 0x00 2.3.78/2-136 0x028e pier?ort r interrupt enable register r/w 0x00 2.3.79/2-136 0x028f pifr?ort r interrupt flag register r/w 0x00 2.3.80/2-137 u 0x0290 ptu?ort u data register r/w 0x00 2.3.81/2-137 0x0291 ptiu?ort u input register r 3 2.3.82/2-138 0x0292 ddru?ort u data direction register r/w 0x00 2.3.83/2-139 0x0293 pim reserved r 0x00 2.3.84/2-139 0x0294 peru?ort u pull device enable register r/w 0x00 2.3.85/2-140 0x0295 ppsu?ort u polarity select register r/w 0x00 2.3.86/2-140 0x0296 srru?ort u slew rate register r/w 0x00 2.3.87/2-141 0x0297 pturr?port s routing register pim reserved r 0x00 2.3.88/2-141 v 0x0298 ptv?ort v data register r/w 0x00 2.3.89/2-143 0x0299 ptiv?ort v input register r 3 2.3.90/2-145 0x029a ddrv?ort v data direction register r/w 0x00 2.3.91/2-146 0x029b pim reserved r 0x00 2.3.92/2-148 0x029c perv?ort v pull device enable register r/w 0x00 2.3.93/2-148 0x029d ppsv?ort v polarity select register r/w 0x00 2.3.94/2-148 0x029e srrv?ort v slew rate register r/w 0x00 2.3.95/2-149 0x029f ptvrr?port s routing register r 0x00 2.3.96/2-150 1 refer to memory map in soc guide to determine related module 2 write access not applicable for one or more register bits. refer to register description 3 read always returns logic level on pins. register name bit 7 654321 bit 0 0x0000 porta r pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 w = unimplemented or reserved table 2-2. block memory map (continued) port offset or address register access reset value section/page
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 78 freescale semiconductor 0x0001 portb r pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 w 0x0002 ddra r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w 0x0003 ddrb r ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 w 0x0004 -0x0009 reserved r00000000 w 0x000a 0x000b non-pim address range r non-pim address range w 0x000c pucr r0 bkpue 0000 pupbe pupae w 0x000d reserved r00000000 w 0x000e 0x001b non-pim address range r non-pim address range w 0x001c eclkctl r neclk 0 div16 ediv4 ediv3 ediv2 ediv1 ediv0 w 0x001d reserved r00000000 w 0x001e irqcr r irqe irqen xirqen 00000 w 0x001f reserved r00000000 w register name bit 7 654321 bit 0 = unimplemented or reserved
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 79 0x0020 0x023f non-pim address range r non-pim address range w 0x0240 ptt r ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 w 0x0241 ptit r ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 w 0x0242 ddrt r ddrt7 ddrt6 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 w 0x0243 reserved r00000000 w 0x0244 pert r pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 w 0x0245 ppst r ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 w 0x0246 reserved r00000000 w 0x0247 pttrr r pttrr7 pttrr6 pttrr5 pttrr4 pttrr3 pttrr2 pttrr1 pttrr0 w 0x0248 pts r pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 w 0x0249 ptis r ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 w 0x024a ddrs r ddrs7 ddrs6 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 w 0x024b reserved r00000000 w 0x024c pers r pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 w register name bit 7 654321 bit 0 = unimplemented or reserved
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 80 freescale semiconductor 0x024d ppss r ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 w 0x024e woms r woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 w 0x024f ptsrr r0 0 ptsrr5 ptsrr4 00 ptsrr1 ptsrr0 w 0x0250 ptm r0000 ptm3 ptm2 ptm1 ptm0 w 0x0251 ptim r 0 0 0 0 ptim3 ptim2 ptim1 ptim0 w 0x0252 ddrm r0000 ddrm3 ddrm2 ddrm1 ddrm0 w 0x0253 reserved r00000000 w 0x0254 perm r0000 perm3 perm2 perm1 perm0 w 0x0255 ppsm r0000 ppsm3 ppsm2 ppsm1 ppsm0 w 0x0256 womm r000000 womm1 womm0 w 0x0257 reserved r00000000 w 0x0258 ptp r ptp7 ptp6 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 w 0x0259 ptip r ptip7 ptip6 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 w 0x025a ddrp r ddrp7 ddrp6 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 w 0x025b reserved r00000000 w register name bit 7 654321 bit 0 = unimplemented or reserved
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 81 0x025c perp r perp7 perp6 perp5 perp4 perp3 perp2 perp1 perp0 w 0x025d ppsp r ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppsp0 w 0x025e ptprrh r ptprrh7 ptprrh6 ptprrh5 ptprrh4 ptprrh3 ptprrh2 ptprrh1 ptprrh0 w 0x025f ptprrl r0000 ptprrl3 ptprrl2 ptprrl1 ptprrl0 w 0x0260 pth r pth7 pth6 pth5 pth4 pth3 pth2 pth1 pth0 w 0x0261 ptih r ptih7 ptih6 ptih5 ptih4 ptih3 ptih2 ptih1 ptih0 w 0x0262 ddrh r ddrh7 ddrh6 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 w 0x0263 reserved r pim reserved( w 0x0264 perh r perh7 perh6 perh5 perh4 perh3 perh2 perh1 perh0 w 0x0265 ppsh r ppsh7 ppsh6 ppsh5 ppsh4 ppsh3 ppsh2 ppsh1 ppsh0 0x0266 womh r womh7 womh6 womh5 womh4 womh3 womh2 womh1 womh0 w 0x0267 pthrr r0000000 pthrr0 w 0x0268- 0x026f reserved r00000000 w 0x0270 pt0ad r0000 pt0ad3 pt0ad2 pt0ad1 pt0ad8 w 0x0271 pt1ad r pt1ad7 pt1ad6 pt1ad5 pt1ad4 pt1ad3 pt1ad2 pt1ad1 pt1ad0 w register name bit 7 654321 bit 0 = unimplemented or reserved
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 82 freescale semiconductor 0x0272 ddr0ad r0000 ddr0ad3 ddr0ad2 ddr0ad1 ddr0ad0 w 0x0273 ddr1ad r ddr1ad7 ddr1ad6 ddr1ad5 ddr1ad4 ddr1ad3 ddr1ad2 ddr1ad1 ddr1ad0 w 0x0274 reserved r00000000 w 0x0275 reserved r00000000 w 0x0276 per0ad r0000 per0ad3 per0ad2 per0ad1 per0ad0 w 0x0277 per1ad r per1ad7 per1ad6 per1ad5 per1ad4 per1ad3 per1ad2 per1ad1 per1ad0 w 0x0278 -0x027f reserved r00000000 w 0x0280 ptr r ptr7 ptr6 ptr5 ptr4 ptr3 ptr2 ptr1 ptr0 w 0x0281 ptir r ptir7 ptir6 ptir5 ptir4 ptir3 ptir2 ptir1 ptir0 w 0x0282 ddrr r ddrr7 ddrr6 ddrr5 ddrr4 ddrr3 ddrr2 ddrr1 ddrr0 w 0x0283 reserved r00000000 w 0x0284 perr r perr7 perr6 perr5 perr4 perr3 perr2 perr1 perr0 w 0x0285 ppsr r ppsr7 ppsr6 ppsr5 ppsr4 ppsr3 ppsr2 ppsr1 ppsr0 w 0x0286 womr r womr7 womr6 womr5 womr4 womr3 womr2 womr1 womr0 w 0x0287 reserved r00000000 w register name bit 7 654321 bit 0 = unimplemented or reserved
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 83 0x0288 piet r piet7 piet6 piet5 piet4 piet3 piet2 piet1 piet0 w 0x0289 pift r pift7 pift6 pift5 pift4 pift3 pift2 pift1 pift0 w 0x028a pies r0 pies6 pies5 00000 w 0x028b pifs r0 pifs6 pifs5 00000 w 0x028c pie1ad r pie1ad7 pie1ad6 pie1ad5 pie1ad4 pie1ad3 pie1ad2 pie1ad1 pie1ad0 w 0x028d pif1ad r pif1ad7 pif1ad6 pif1ad5 pif1ad4 pif1ad3 pif1ad2 pif1ad1 pif1ad0 w 0x028e pier r0000 pier3 pier2 pier1 pier0 w 0x028f pifr r0000 pifr3 pifr2 pifr1 pifr0 w 0x0290 ptu r ptu7 ptu6 ptu5 ptu4 ptu3 ptu2 ptu1 ptu0 w 0x0291 ptiu r ptiu7 ptiu6 ptiu5 ptiu4 ptiu3 ptiu2 ptiu1 ptiu0 w 0x0292 ddru r ddru7 ddru6 ddru5 ddru4 ddru3 ddru2 ddru1 ddru0 w 0x0293 reserved r00000000 w 0x0294 peru r peru7 peru6 peru5 peru4 peru3 peru2 peru1 peru0 w 0x0295 ppsu r ppsu7 ppsu6 ppsu5 ppsu4 ppsu3 ppsu2 ppsu1 ppsu0 0x0296 srru r srru7 srru6 srru5 srru4 srru3 srru2 srru1 srru0 w register name bit 7 654321 bit 0 = unimplemented or reserved
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 84 freescale semiconductor 2.3.2 register descriptions the following table summarizes the effect of the various con?uration bits, i.e. data direction (ddr), output level (io), pull enable (pe), pull select (ps) on the pin function and pull device activity. the con?uration bit ps is used for two purposes: 1. con?ure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. select either a pull-up or pull-down device if pe is active. 0x0297 pturr r0000 pturr3 pturr2 00 w 0x0298 ptv r ptv7 ptv6 ptv5 ptv4 ptv3 ptv2 ptv1 ptv0 w 0x0299 ptiv r ptiv7 ptiv6 ptiv5 ptiv4 ptiv3 ptiv2 ptiv1 ptiv0 w 0x029a ddrv r ddrv7 ddrv6 ddrv5 ddrv4 ddrv3 ddrv2 ddrv1 ddrv0 w 0x029b reserved r00000000 w 0x029c perv r perv7 perv6 perv5 perv4 perv3 perv2 perv1 perv0 w 0x0294d ppsv r ppsv7 ppsv6 ppsv5 ppsv4 ppsv3 ppsv2 ppsv1 ppsv0 0x029e srrv r srrv7 srrv6 srrv5 srrv4 srrv3 srrv2 srrv1 srrv0 w 0x029f ptvrr r0000 ptvrr3 ptvrr2 00 w register name bit 7 654321 bit 0 = unimplemented or reserved
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 85 table 2-3. pin con?uration summary note all register bits in this module are completely synchronous to internal clocks during a register read. note figure of port data registers also display the alternative functions if applicable on the related pin as de?ed in table 2-1 . names in brackets denote the availability of the function when using a speci? routing option. note figures of module routing registers also display the module instance or module channel associated with the related routing bit. ddr io rdr 1 1 not applicable only on mc9s12xhy pe ps 2 2 always ??on port a, b, and always ??on ad. ie 3 3 applicable only on port t, s, r,m and ad. function pull device interrupt 0 x x 0 x 0 input disabled disabled 0 x x 1 0 0 input pull up disabled 0 x x 1 1 0 input pull down disabled 0 x x 0 0 1 input disabled falling edge 0 x x 0 1 1 input disabled rising edge 0 x x 1 0 1 input pull up falling edge 0 x x 1 1 1 input pull down rising edge 1 0 0 x x 0 output, full drive to 0 disabled disabled 1 1 0 x x 0 output, full drive to 1 disabled disabled 1 0 1 x x 0 output, reduced drive to 0 disabled disabled 1 1 1 x x 0 output, reduced drive to 1 disabled disabled 1 0 0 x 0 1 output, full drive to 0 disabled falling edge 1 1 0 x 1 1 output, full drive to 1 disabled rising edge 1 0 1 x 0 1 output, reduced drive to 0 disabled falling edge 1 1 1 x 1 1 output, reduced drive to 1 disabled rising edge
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 86 freescale semiconductor 2.3.3 port a data register (porta) address 0x0000 (prr) access: user read/write 1 1 read: anytime. the data source is depending on the data direction value. write: anytime 76543210 r pa 7 pa 6 pa 5 pa4 pa3 pa2 pa1 pa 0 w api_extclk xirq irq altern. function fp36 fp35 fp34 fp33 fp32 fp31 fp30 fp29 reset 00000000 figure 2-1. port a data register (porta) table 2-4. porta register field descriptions field description 7-4,2 pa port a general purpose input/output data ?ata register, lcd segment driver output the associated pin can be used as general purpose i/o when not used as alternative function is not enabled. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the general purpose i/o function if the related lcd segment is enabled. 3 pa port a general purpose input/output data ?ata register, lcd segment driver output, api_extclk the associated pin can be used as general purpose i/o when not used as alternative function. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the api_extclk and general purpose i/o function if the related lcd segment is enabled. the api_extclk takes precedence over the general purpose i/o function if the api_extclk function is enabled 1 pa port a general purpose input/output data ?ata register, lcd segment driver output, xirq the associated pin can be used as general purpose i/o when not used as alternative function. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the xirq and general purpose i/o function if the related lcd segment is enabled. the xirq takes precedence over the general purpose i/o function if the xirq function is enabled 0 pa port a general purpose input/output data ?ata register, lcd segment driver output, irq the associated pin can be used as general purpose i/o when not used as alternative function. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the irq and general purpose i/o function if the related lcd segment is enabled. the irq takes precedence over the general purpose i/o function if the irq function is enabled
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 87 2.3.4 port b data register (portb) 2.3.5 port a data direction register (ddra) address 0x0001 (prr) access: user read/write 1 1 read: anytime. the data source is depending on the data direction value. write: anytime 76543210 r pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb7 w altern. function bp3 bp2 bp1 bp0 fp39 fp38 fp37 fp28 reset 00000000 figure 2-2. port b data register (portb) table 2-5. portb register field descriptions field description 7-0 pb port b general purpose input/output data ?ata register, lcd segment driver output the associated pin can be used as general purpose i/o when not used as alternative function. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the general purpose i/o function if the related lcd segment is enabled. address 0x0002 (prr) access: user read/write 1 1 read: anytime write: anytime 76543210 r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w reset 00000000 figure 2-3. port a data direction register (ddra)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 88 freescale semiconductor 2.3.6 port b data direction register (ddrb) table 2-6. ddra register field descriptions field description 7-4,2 ddra port a data direction this bit determines whether the associated pin is an input or output. if corresponding lcd segment is enabled, it will be forced as input/output disable 1 associated pin is con?ured as output 0 associated pin is con?ured as input 3 ddra port a data direction this bit determines whether the associated pin is an input or output. if corresponding lcd segment is enabled, it will be forced as input/output disabled else if api_extclk is enabled, it will be forced as output 1 associated pin is con?ured as output 0 associated pin is con?ured as input 1 ddra port a data direction this bit determines whether the associated pin is an input or output. if corresponding lcd segment is enabled, it will be forced as input/output disabled else if xirq is enabled, it will be forced as input 1 associated pin is con?ured as output 0 associated pin is con?ured as input 0 ddra port a data direction this bit determines whether the associated pin is an input or output. if corresponding lcd segment is enabled, it will be forced as input/output disabled else if / irq is enabled, it will be forced as input 1 associated pin is con?ured as output 0 associated pin is con?ured as input address 0x0003 (prr) access: user read/write 1 1 read: anytime write: anytime 76543210 r ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 w reset 00000000 figure 2-4. port b data direction register (ddrb)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 89 note due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on pta, ptb registers, when changing the ddra,ddrb register. 2.3.7 pim reserved register 2.3.8 ports a, b, bkgd pin pull control register (pucr) table 2-7. ddrb register field descriptions field description 7-0 ddrb port b data direction this bit determines whether the associated pin is an input or output. if corresponding lcd segment is enabled, it will be forced as input/output disabled 1 associated pin is con?ured as output 0 associated pin is con?ured as input address 0x0004 (prr) to 0x0009 (prr) access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 2-5. pim reserved register address 0x000c (prr) access: user read/write 1 1 read:anytime in single-chip modes. write:anytime, except bkpue which is writable in special single-chip mode only. 76543210 r0 bkpue 0000 pupbe pupae w reset 01000011 = unimplemented or reserved figure 2-6. ports ab, bkgd pin pull control register (pucr)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 90 freescale semiconductor 2.3.9 pim reserved register table 2-8. pucr register field descriptions field description 6 bkpue bkgd pin pull-up enable ?nable pull-up device on pin this bit con?ures whether a pull-up device is activated, if the pin is used as input. if a pin is used as output this bit has no effect. 1 pull-up device enabled 0 pull-up device disabled 1 pupbe port b pull-down enable ?nable pull-down devices on all port input pins this bit con?ures whether a pull-down device is activated on all associated port input pins. if a pin is used as output this bit has no effect. 1 pull-down device enabled 0 pull-down device disabled 0 pupae port a pull-down enable ?nable pull-down devices on all port input pins this bit con?ures whether a pull-down device is activated on all associated port input pins. if a pin is used as output this bit has no effect. 1 pull-down device enabled 0 pull-down device disabled address 0x000d (prr) access: user read/write 1 1 read: anytime write: anytime 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 2-7. pim reserved register
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 91 2.3.10 eclk control register (eclkctl) 2.3.11 pim reserved register address 0x001c (prr) access: user read/write 1 1 read: anytime write: anytime 76543210 r neclk 0 div16 ediv4 ediv3 ediv2 ediv1 ediv0 w reset: 10000000 = unimplemented or reserved figure 2-8. eclk control register (eclkctl) table 2-9. eclkctl register field descriptions field description 7 neclk no eclk ?isable eclk output this bit controls the availability of a free-running clock on the eclk pin. this clock has a xed rate of equivalent to the internal bus clock. 1 eclk disabled 0 eclk enabled 5 div16 free-running eclk predivider ?ivide by 16 this bit enables a divide-by-16 stage on the selected ediv rate. 1 divider enabled: eclk rate = ediv rate divided by 16 0 divider disabled: eclk rate = ediv rate 4-0 ediv free-running eclk divider ?on?ure eclk rate these bits determine the rate of the free-running clock on the eclk pin. 00000 eclk rate = bus clock rate 1 00001 eclk rate = bus clock rate divided by 2 00010 eclk rate = bus clock rate divided by 3,... 11111 eclk rate = bus clock rate divided by 32 1 when ediv=00000 div16-0,and bus clock>=32mhz, eclk output maybe cannot work address 0x001d (prr) access: user read 1 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 2-9. pim reserved register
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 92 freescale semiconductor 2.3.12 irq control register (irqcr) 2.3.13 pim reserved register this register is reserved for factory testing of the pim module and is not available in normal operation. 1 read: always reads 0x00 write: unimplemented address 0x001e access: user read/write 1 1 read: see individual bit descriptions below. write: see individual bit descriptions below. 76543210 r irqe irqen xirqen 00000 w reset 00000000 = unimplemented or reserved figure 2-10. irq control register (irqcr) table 2-10. irqcr register field descriptions field description 7 irqe irq select edge sensitive only special mode: read or write anytime. normal mode: read anytime, write once. 1 irq pin con?ured to respond only to falling edges. falling edges on the irq pin will be detected anytime irqe=1 and will be cleared only upon a reset or the servicing of the irq interrupt. 0 irq pin con?ured for low level recognition 6 irqen irq enable read or write anytime. 1 irq pin is connected to interrupt logic 0 irq pin is disconnected from interrupt logic 5 xirqen xirq enable special mode: read or write anytime. normal mode: read anytime, write once. 1 xirq pin is connected to interrupt logic 0 xirq pin is disconnected from interrupt logic
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 93 2.3.14 port t data register (ptt) address 0x001f access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 2-11. pim reserved register address 0x0240 access: user read/write 1 1 read: anytime. the data source is depending on the data direction value. write: anytime 76543210 r ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 w ioc0_7 ioc0_6 ioc0_5 ioc0_4 ioc1_7 ioc1_6 ioc1_5 ioc1_4 altern. function fp16 fp15 fp14 fp13 fp11 fp10 fp9 fp8 reset 00000000 figure 2-12. port t data register (ptt)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 94 freescale semiconductor 2.3.15 port t input register (ptit) table 2-11. ptt register field descriptions field description 7-4 ptt port t general purpose input/output data ?ata register, lcd segment driver output, tim0 output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the tim0 and general purpose i/o function if related lcd segment is enabled the tim0 output function takes precedence over the general purpose i/o function if the related channel is enabled. 1 1 in order tim input capture to be function correctly, the corresponding ddrt bit should be set to 0 3-0 ptt port t general purpose input/output data ?ata register, lcd segment driver output, tim1 output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the tim1 and general purpose i/o function if related lcd segment is enabled the tim1 output function takes precedence over the general purpose i/o function if the related channel is enabled. 1 address 0x0241 access: user read 1 1 read: anytime write:never, writes to this register have no effect. 76543210 r ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-13. port t input register (ptit) table 2-12. ptit register field descriptions field description 7-0 ptit port t input data a read always returns the buffered input state of the associated pin. it can be used to detect overload or short circuit conditions on output pins.
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 95 2.3.16 port t data direction register (ddrt) note due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on ptt or ptit registers, when changing the ddrt register. 2.3.17 pim reserved register address 0x0242 access: user read/write 1 1 read: anytime write: anytime 76543210 r ddrt7 ddrt6 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 w reset 00000000 figure 2-14. port t data direction register (ddrt) table 2-13. ddrt register field descriptions field description 7-4 ddrt port t data direction this bit determines whether the pin is an input or output. if corresponding lcd segment is enabled, it will be forced as input/output disabled else if corresponding tim0 output compare channel is enabled, it will be forced as output. 1 associated pin is con?ured as output 0 associated pin is con?ured as input 3-0 ddrt port t data direction this bit determines whether the pin is an input or output. if corresponding lcd segment is enabled, it will be forced as input/output disabled else if corresponding tim1 output compare channel is enabled, it will be forced as output. 1 associated pin is con?ured as output 0 associated pin is con?ured as input address 0x0243 access: user read/write 1 76543210 r00000000 w w reset 00000000 figure 2-15. pim reserved register
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 96 freescale semiconductor 2.3.18 port t pull device enable register (pert) 2.3.19 port t polarity select register (ppst) 1 read: anytime write: anytime address 0x0244 access: user read/write 1 1 read: anytime write: anytime 76543210 r pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 w reset 11111111 figure 2-16. port t pull device enable register (pert) table 2-14. pert register field descriptions field description 7-0 pert port t pull device enable ?nable pull device on input pin this bit controls whether a pull device on the associated port input pin is active. if a pin is used as output this bit has no effect. the polarity is selected by the related polarity select register bit. 1 pull device enabled 0 pull device disabled address 0x0245 access: user read/write 1 1 read: anytime write: anytime 76543210 r ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 w reset 11111111 figure 2-17. port t polarity select register (ppst) table 2-15. ppst register field descriptions field description 7-0 ppst port t pull device select ?on?ure pull device polarity on input pin this bit selects a pull-up or a pull-down device if enabled on the associated port input pin. 1 a pull-down device is selected 0 a pull-up device is selected
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 97 2.3.20 pim reserved register 2.3.21 port t routing register (pttrr) this register configures the re-routing of tim0/1 channels on alternative pins on port r/t. address 0x0246 access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 2-18. pim reserved register address 0x0247 access: user read 1 1 read: anytime write: anytime 76543210 r pttrr7 pttrr6 pttrr5 pttrr4 pttrr3 pttrr2 pttrr1 pttrr0 w routing option ioc0_7 ioc0_5 ioc0_4 ioc0_6 ioc1_7 ioc1_6 reset 00000000 = unimplemented or reserved figure 2-19. port t routing register (pttrr) table 2-16. port t routing register field descriptions field description [7:6] pttrr port t data direction this register controls the routing of ioc0_7. 00 ioc0_7 routed to pt7 01 ioc0_7 routed to pr1 10 ioc0_7 routed to pv6 11 ioc0_7 routed to pt7(reserved) 5 pttrr port t data direction this register controls the routing of ioc0_5. 0 ioc0_5 routed to pt5 1 ioc0_5 routed to pv2
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 98 freescale semiconductor 2.3.22 port s data register (pts) 4 pttrr port t data direction this register controls the routing of ioc0_4. 0 ioc0_4 routed to pt4 1 ioc0_4 routed to pv0 [3:2] pttrr port t data direction this register controls the routing of ioc0_6. 00 ioc0_6 routed to pt6 01 ioc0_6 routed to pr0 10 ioc0_6 routed to pv4 11 ioc0_6 routed to pt6(reserved) 1 pttrr port t data direction this register controls the routing of ioc1_7. 0 ioc1_7routed to pt3 1 ioc1_7 routed to pr3 0 pttrr port t data direction this register controls the routing of ioc1_6. 0 ioc1_6 routed to pt2 1 ioc1_6 routed to pr2 address 0x0248 access: user read/write 1 1 read: anytime the data source is depending on the data direction value. write: anytime 76543210 r pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 w pwm3 pwm2 pwm1 pwm0 pwm7 pwm6 sdascl altern. function ss sck mosi miso txcan rxcan txd rxd reset 00000000 figure 2-20. port s data register (pts) table 2-16. port t routing register field descriptions (continued) field description
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 99 table 2-17. pts register field descriptions field description 7 pts port s general purpose input/output data ?ata register, spi ss inout, iic sda inout, pwm channel3 when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the spi takes precedence over the iic, pwm3 and the general purpose i/o function if enabled the iic takes precedence over the pwm3 and the general purpose i/o function if enabled the pwm3 takes precedence over the general purpose i/o function if enabled 6 pts port s general purpose input/output data ?ata register, spi sck inout, pwm channel2 when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the spi takes precedence over the pwm2 and the general purpose i/o function if enabled the pwm2 takes precedence over the general purpose i/o function if enabled 5 pts port s general purpose input/output data ?ata register, spi mosi inout, pwm channel1 when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the spi takes precedence over the pwm1 and the general purpose i/o function if enabled the pwm1 takes precedence over the general purpose i/o function if enabled 4 pts port s general purpose input/output data ?ata register, spi miso inout, iic scl inout, pwm channel0 when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the spi takes precedence over the iic, pwm0 and the general purpose i/o function if enabled the iic takes precedence over the pwm0 and the general purpose i/o function if enabled the pwm0 takes precedence over the general purpose i/o function if enabled 3 pts port s general purpose input/output data ?ata register, can tx when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the can takes precedence over the general purpose i/o function if enabled 2 pts port s general purpose input/output data ?ata register, can rx when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the can takes precedence over the general purpose i/o function if enabled
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 100 freescale semiconductor 2.3.23 port s input register (ptis) 1 pts port s general purpose input/output data ?ata register, sci txd, pwm channel7 when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the sci takes precedence over the pwm7 and general purpose i/o function if enabled the pwm7 takes precedence over the general purpose i/o function if enabled 0 pts port s general purpose input/output data ?ata register, sci rxd, pwm channel6 when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the sci takes precedence over the pwm6 and general purpose i/o function if enabled the pwm6 takes precedence over the general purpose i/o function if enabled address 0x0249 access: user read 1 1 read: anytime. write:never, writes to this register have no effect. 76543210 r ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-21. port s input register (ptis) table 2-18. ptis register field descriptions field description 7-0 ptis port s input data this register always reads back the buffered state of the associated pins. this can also be used to detect overload or short circuit conditions on output pins. table 2-17. pts register field descriptions (continued) field description
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 101 2.3.24 port s data direction register (ddrs) address 0x024a access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddrs7 ddrs6 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 w reset 00000000 figure 2-22. port s data direction register (ddrs) table 2-19. ddrs register field descriptions field description 7 ddrs port s data direction this register controls the data direction of pin 7.this register con?ures pin as either input or output. if spi is routing to ps and spi is enabled, the spi determines the pin direction else if iic is routing to ps and iic is enabled, the iic determines the pin direction, it will force as open-drain output else if pwm3 is routing to ps and pwm3 is enabled it will force as output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 6 ddrs port s data direction this register controls the data direction of pin 6.this register con?ures pin as either input or output. if spi is routing to ps and spi is enabled, the spi determines the pin direction else if pwm2 is routing to ps and pwm2 is enabled it will force as output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 5 ddrs port s data direction this register controls the data direction of pin 5.this register con?ures pin as either input or output. if spi is routing to ps and spi is enabled, the spi determines the pin direction else if pwm1 is routing to ps and pwm1 is enabled it will force as output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 4 ddrs port s data direction this register controls the data direction of pin 4.this register con?ures pin as either input or output. if spi is routing to ps and spi is enabled, the spi determines the pin direction else if iic is routing to ps and iic is enabled, it will force as open-drain output else if pwm0 is routing to ps and pwm0 is enabled it will force as output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input.
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 102 freescale semiconductor note due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on pts or ptis registers, when changing the ddrs register. 2.3.25 pim reserved registers 3 ddrs port s data direction this register controls the data direction of pin 3.this register con?ures pin as either input or output. if can is enabled, it will force the pin as output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 2 ddrs port s data direction this register controls the data direction of pin 2.this register con?ures pin as either input or output. if can is enabled, it will force the pin as input. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 1 ddrs port s data direction this register controls the data direction of pin 1.this register con?ures pin as either input or output. if sci is enabled, it will force the pin as output else if pwm7 is routing to ps1 and use as pwm channel output, it will force pin as output. if use as pwm emergency shut down, it will force pin as input. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 0 ddrs port s data direction this register controls the data direction of pin 0.this register con?ures pin as either input or output. if sci is enabled, it will force the pin as input else if pwm6 is routing to ps0 and pwm6 is enabled, it will force pin as output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. address 0x024b access: user read/write 1 1 read: anytime. write: anytime. 76543210 r00000000 w reset 00000000 figure 2-23. pim reserved register) table 2-19. ddrs register field descriptions (continued) field description
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 103 2.3.26 port s pull device enable register (pers) 2.3.27 port s polarity select register (ppss) address 0x024c access: user read/write 1 1 read: anytime. write: anytime. 76543210 r pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 w reset 11111111 figure 2-24. port s pull device enable register (pers) table 2-20. pers register field descriptions field description 7-0 pers port s pull device enable ?nable pull devices on input pins these bits con?ure whether a pull device is activated, if the associated pin is used as an input. this bit has no effect if the pin is used as an output. out of reset all pull devices are enabled. 1 pull device enabled. 0 pull device disabled. address 0x024d access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 w reset 00000000 figure 2-25. port s polarity select register (ppss) table 2-21. ppss register field descriptions field description 7-0 ppss port s pull device select ?etermine pull device polarity on input pins this register selects whether a pull-down or a pull-up device is connected to the pin. 1 a rising edge on the associated port s pin sets the associated ?g bit in the pifs register. a pull-down device is connected to the associated pin, if enabled and if the pin is used as input. 0 a falling edge on the associated port s pin sets the associated ?g bit in the pifs register. a pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 104 freescale semiconductor 2.3.28 port s wired-or mode register (woms) 2.3.29 port s routing register (ptsrr) this register configures the re-routing of iic and spi on alternative ports. address 0x024e access: user read/write 1 1 read: anytime. write: anytime. 76543210 r woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 w reset 00000000 figure 2-26. port s wired-or mode register (woms) table 2-22. woms register field descriptions field description 7-0 woms port s wired-or mode ?nable wired-or functionality this register con?ures the output pins as wired-or. if enabled the output is driven active low only (open-drain). a logic level of ??is not driven.this allows a multipoint connection of several serial modules. these bits have no in?ence on pins used as inputs. 1 output buffers operate as open-drain outputs. 0 output buffers operate as push-pull outputs. address 0x024f access: user read/write 1 1 read: anytime. write: anytime. 76543210 r0 0 ptsrr5 ptsrr4 00 ptsrr1 ptsrr0 w reset 00000000 figure 2-27. port s routing register (ptsrr) table 2-23. module routing summary module ptsrr related pins 54 10 scl sda
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 105 2.3.30 pim reserved register iic x x 0 0 ps4 ps7 x x 0 1 ps4 ps7 x x 1 0 pr6 pr5 x x 1 1 pv0 pv3 miso mosi sck ss spi 0 0 x x ps4 ps5 ps6 ps7 0 1 x x ph0 ph1 ph2 ph3 1 0 x x pv0 pv1 pv2 pv3 1 1 x x reserved table 2-23. module routing summary module ptsrr related pins
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 106 freescale semiconductor 2.3.31 port m data register (ptm) address 0x0250 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r0000 ptm3 ptm2 ptm1 ptm0 w -- -- -- -- pwm7 pwm6 pwm5 pwm4 -- -- -- -- ioc1_3 ioc1_2 ioc0_3 ioc0_2 altern. function -- -- -- -- -- -- txd1 rxd1 reset uuuu0000 = unimplemented or reserved u = unaffected by reset table 2-24. port m data register (ptm) table 2-25. ptm register field descriptions field description 3 ptm port m general purpose input/output data ?ata register, pwm channel7,tim1 output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the tim1 output function takes precedence over the pwm7 and general purpose i/o function if the related channel is enabled. 1 the pwm7 takes precedence over the general purpose i/o function if enabled 2 ptm port m general purpose input/output data ?ata register,pwm channel6,tim1 output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the tim1 output function takes precedence over the pwm6 and general purpose i/o function if the related channel is enabled. 2 the pwm6 takes precedence over the general purpose i/o function if enabled
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 107 2.3.32 port m input register (ptim) 1 ptm port m general purpose input/output data ?ata register, sci1 txd, pwm channel5,tim0 output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the sci1 takes precedence over the tim0 output,pwm5 and general purpose i/o function if enabled the tim0 output function takes precedence over the pwm5 and general purpose i/o function if the related channel is enabled. 3 the pwm5 takes precedence over the general purpose i/o function if enabled 0 ptm port m general purpose input/output data ?ata register, sci1 rxd, pwm channel4,tim0 output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the sci1 takes precedence over the tim0 output,pwm4 and general purpose i/o function if enabled the tim0 output function takes precedence over the pwm4 and general purpose i/o function if the related channel is enabled. 4 the pwm4 takes precedence over the general purpose i/o function if enabled 1 in order tim input capture to be function correctly, the corresponding ddrt bit should be set to 0 2 in order tim input capture to be function correctly, the corresponding ddrt bit should be set to 0 3 in order tim input capture to be function correctly, the corresponding ddrt bit should be set to 0 4 in order tim input capture to be function correctly, the corresponding ddrt bit should be set to 0 address 0x0251 access: user read 1 1 read: anytime write:never, writes to this register have no effect. 76543210 r0000 ptim3 ptim2 ptim1 ptim0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-29. port m input register (ptim) table 2-24. port m data register (ptm) table 2-25. ptm register field descriptions (continued) field description
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 108 freescale semiconductor 2.3.33 port m data direction register (ddrm) note due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on ptm or ptim registers, when changing the ddrt register. table 2-26. ptim register field descriptions field description 3-0 ptim port m input data a read always returns the buffered input state of the associated pin. it can be used to detect overload or short circuit conditions on output pins. address 0x0252 access: user read/write 1 1 read: anytime write: anytime 76543210 r0000 ddrm3 ddrm2 ddrm1 ddrm0 w reset 00000000 = unimplemented or reserved figure 2-30. port m data direction register (ddrm) table 2-27. ddrm register field descriptions field description 3-2 ddrm port m data direction this bit determines whether the pin is an input or output. if corresponding lcd segment is enabled, it will be forced as input/output disabled else if corresponding output compare channel is enabled, it will be forced as output. else if the corresponding pwm7-6 are enabled, the corresponding i/o state will be forced to output. in this case the data direction bit will not change. 1 associated pin is con?ured as output 0 associated pin is con?ured as input 1-0 ddrm port t data direction this bit determines whether the pin is an input or output. if corresponding lcd segment is enabled, it will be forced as input/output disabled else if corresponding output compare channel is enabled, it will be forced as output. else if the corresponding pwm5-4 are enabled, the corresponding i/o state will be forced to output. in this case the data direction bit will not change. 1 associated pin is con?ured as output 0 associated pin is con?ured as input
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 109 2.3.34 pim reserved registers 2.3.35 port m pull device enable register (perm) address 0x0253 access: user read/write 1 1 read: anytime write: anytime 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 2-31. pim reserved register address 0x0254 access: user read/write 1 1 read: anytime write: anytime 76543210 r0000 perm3 perm2 perm1 perm0 w reset 00001111 = unimplemented or reserved figure 2-32. port m pull device enable register (perm) table 2-28. pert register field descriptions field description 3-0 perm port m pull device enable ?nable pull device on input pin this bit controls whether a pull device on the associated port input pin is active. if a pin is used as output this bit has no effect. the polarity is selected by the related polarity select register bit. 1 pull device enabled 0 pull device disabled
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 110 freescale semiconductor 2.3.36 port m polarity select register (ppsm) 2.3.37 port mwired-or mode register (womm) table 2-30. womm register field descriptions address 0x0255 access: user read/write 1 1 read: anytime write: anytime 76543210 r0000 ppsm3 ppsm2 ppsm1 ppsm0 w reset 00000000 = unimplemented or reserved figure 2-33. port m polarity select register (ppsm) table 2-29. ppst register field descriptions field description 3-0 ppsm port m pull device select ?on?ure pull device polarity on input pin this bit selects a pull-up or a pull-down device if enabled on the associated port input pin. 1 a pull-down device is selected 0 a pull-up device is selected address 0x0256 access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r000000 womm1 womm0 w reset 00000011 = unimplemented or reserved figure 2-34. port mwired-or mode register field description 1-0 womm port m wired-or mode ?nable wired-or functionality this register con?ures the output pins as wired-or. if enabled the output is driven active low only (open-drain). a logic level of ??is not driven.this allows a multipoint connection of several serial modules. these bits have no in?ence on pins used as inputs. 1 output buffers operate as open-drain outputs. 0 output buffers operate as push-pull outputs.
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 111 2.3.38 pim reserved register 2.3.39 port p data register (ptp) address 0x0257 access: user read 1 1 read: anytime write: anytime 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 2-35. pim reserved register address 0x0258 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ptp7 ptp6 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 w pwm7 pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 altern. function fp7 fp6 fp5 fp4 fp3 fp2 fp1 fp0 reset 00000000 figure 2-36. port p data register (ptp) table 2-31. ptp register field descriptions field description 7-0 ptp port p general purpose input/output data ?ata register, lcd segment driver output, pwm channel output port p pins are associated with the pwm channel output and lcd segment driver output . when not used with the alternative functions, these pins can be used as general purpose i/o. if the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the lcd segment takes precedence over the pwm function and the general purpose i/o function is lcd segment output is enabled the pwm function takes precedence over the general purpose i/o function if the pwm channel is enabled.
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 112 freescale semiconductor 2.3.40 port p input register (ptip) 2.3.41 port p data direction register (ddrp) address 0x0259 access: user read 1 1 read: anytime. write:never, writes to this register have no effect. 76543210 r ptip7 ptip6 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-37. port p input register (ptip) table 2-32. ptip register field descriptions field description 7-0 ptip port p input data this register always reads back the buffered state of the associated pins. this can also be used to detect overload or short circuit conditions on output pins. address 0x025a access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddrp7 ddrp6 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 w reset 00000000 figure 2-38. port p data direction register (ddrp)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 113 note due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on ptp or ptip registers, when changing the ddrp register. 2.3.42 pim reserved registers 2.3.43 port p pull device enable register (perp) table 2-33. ddrp register field descriptions field description 7 ddrp port p data direction this register controls the data direction of pin 7. if enabled the lcd segment output it will force the i/o state to be a input/output disabled else if the enabled pwm channel 7 forces the i/o state to be an output. if the pwm shutdown feature is enabled this pin is forced to be an input. in these cases the data direction bit will not change. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 6-0 ddrp port p data direction if enabled the lcd segment output it will force the i/o state to be a input/output disabled else if the pwm forces the i/o state to be an output for each port line associated with an enabled pwm6-0 channel. in this case the data direction bit will not change. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. address 0x025b access: user read/write 1 1 read: anytime. write: anytime. 76543210 r00000000 w reset 00000000 figure 2-39. pim reserved register address 0x025c access: user read/write 1 76543210 r perp7 perp6 perp5 perp4 perp3 perp2 perp1 perp0 w reset 11111111 figure 2-40. port p pull device enable register (perp)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 114 freescale semiconductor 2.3.44 port p polarity select register (ppsp) 2.3.45 port p routing register high (ptprrh) read: anytime. 1 read: anytime. write: anytime. table 2-34. perp register field descriptions field description 7-0 perp port p pull device enable ?nable pull devices on input pins these bits con?ure whether a pull device is activated, if the associated pin is used as an input. this bit has no effect if the pin is used as an output. out of reset all pull device is enabled. 1 pull device enabled. 0 pull device disabled. address 0x025d access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppsp0 w reset 11111111 figure 2-41. port p polarity select register (ppsp) table 2-35. ppsp register field descriptions field description 7-0 ppsp port p pull device select ?etermine pull device polarity on input pins this register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 1 a pull-down device is connected to the associated port p pin, if enabled by the associated bit in register perp and if the port is used as input. 0 a pull-up device is connected to the associated port p pin, if enabled by the associated bit in register perp and if the port is used as input. address 0x025e access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ptprrh7 ptprrh6 ptprrh5 ptprrh4 ptprrh3 ptprrh2 ptprrh1 ptprrh0 w reset 00000000 figure 2-42. port p routing register high (ptprrh)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 115 2.3.46 port p routing register low(ptprrl) the ptprrh/ptprrl register configures the re-routing of pwm on alternative ports. table 2-36. port routing register high field descriptions field description 7-0 ptprrh port p routing register high the registers enable the pwm[7:4] routing the port s/v/p address 0x025f access: user read/write 1 1 read: anytime. write: anytime. 76543210 r0000 ptprrl3 ptprrl2 ptprrl1 ptprrl0 w reset 00000000 figure 2-43. port p routing register low(ptprrl) table 2-37. ptprrl register field descriptions field description 3-0 ptprrl port p routing register low the register decide the pwm[3:0] channel routing on the port s/p/v table 2-38. module routing summary module ptprrh ptprrl related pins 7 6 5 4 3 2103210 pwm 7 pwm 6 pwm 5 pwm 4 pwm 3 pwm 2 pwm 1 pwm 0 pwm7 00 xx xx xx xx xx pp7 01 xx xx xx xx xx ps1 10 xx xx xx xx xx pv3 11 xx xx xx xx xxpm3 pwm6 xx 00 xx xx xx xx pp6 xx 01 xx xx xx xx ps0 xx 10 xx xx xx xx pv2 xx 11 xx xx xx xx pm2
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 116 freescale semiconductor 2.3.47 port h data register (pth) pwm5 x x x x x 0 0 x x x x x x x pp5 x x x x x 0 1 x x x x x x x ps3 x x x x x 1 0 x x x x x x x pv1 x x x x x 1 1 x x x x x x x pm1 pwm4 xx xx xx 00 xx xx pp4 xx xx xx 01 xx xx ps2 xx xx xx 10 xx xx pv0 xx xx xx 11 xx xx pm0 pwm3 x x x x x x x x 0 x x x pp3 xx xx xx xx 1x xx ps7 pwm2 x x x x x x x x x 0 x x pp2 xx xx xx xx x1 xx ps6 pwm1 x x x x x x x x x x 0 x pp1 xx xx xx xx xx 1x ps5 pwm0 x x x x x x x x x x x 0 pp0 xx xx xx xx xx x1 ps4 address 0x0260 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r pth7 pth6 pth5 pth4 pth3 pth2 pth1 pth0 w ss eclk mosi miso 2 2 special priority for spi & iic sck txd1 rxd1 altern. function fp26 fp25 fp24 fp23 fp22 fp21 fp20 fp19 reset 00000000 figure 2-44. port h data register (pth) table 2-38. module routing summary module ptprrh ptprrl related pins 7 6 5 4 3 2103210 pwm 7 pwm 6 pwm 5 pwm 4 pwm 3 pwm 2 pwm 1 pwm 0
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 117 table 2-39. pth register field descriptions field description 7-4 pth port h general purpose input/output data ?ata register, lcd segment driver output when not used with the alternative function, this pin can be used as general purpose i/o. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the lcd segment driver output function takes precedence over the general purpose i/o function if enabled 3 pth port h general purpose input/output data ?ata register, lcd segment driver output, ss of spi when not used with the alternative function, this pin can be used as general purpose i/o. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the spi, iic and the general purpose i/o function the ss of spi takes precedence over the general purpose i/o function 2 pth port h general purpose input/output data ?ata register, lcd segment driver output, sck of spi, eclk when not used with the alternative function, this pin can be used as general purpose i/o. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the spi, eclk and the general purpose i/o function the sck of spi takes precedence over the eclk and the general purpose i/o function the eclk takes precedence over the general purpose i/o function 1 pth port h general purpose input/output data ?ata register, lcd segment driver output, mosi of spi,txd of sci1 when not used with the alternative function, this pin can be used as general purpose i/o. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the sci,spi and the general purpose i/o function the txd of sci1 takes precedence over the spi and the general purpose i/o function the mosi of spi takes precedence over the general purpose i/o function 0 pth port h general purpose input/output data ?ata register, lcd segment driver output, miso of spi, scl of iic when not used with the alternative function, this pin can be used as general purpose i/o. if the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the spi, sci and the general purpose i/o function the rxd of sci1 takes precedence over the spi and the general purpose i/o function the miso of spi takes precedence over the general purpose i/o function
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 118 freescale semiconductor 2.3.48 port h input register (ptih) 2.3.49 port h data direction register (ddrh) address 0x0261 access: user read 1 1 read: anytime. write:never, writes to this register have no effect. 76543210 r ptih7 ptih6 ptih5 ptih4 ptih3 ptih2 ptih1 ptih0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-45. port h input register (ptih) table 2-40. ptih register field descriptions field description 7-0 ptih port h input data this register always reads back the buffered state of the associated pins. this can also be used to detect overload or short circuit conditions on output pins. address 0x0262 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddrh7 ddrh6 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 w reset 00000000 figure 2-46. port h data direction register (ddrh)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 119 note due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on pth or ptih registers, when changing the ddrh register. table 2-41. ddrh register field descriptions field description 7-4 ddrh port h data direction this register controls the data direction of pin 7-4. if enabled the lcd segment output it will force the i/o state to be a input/output diabled. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 3 ddrh port h data direction this register controls the data direction of pin 3. if enabled the lcd segment output it will force the i/o state to be a input/output disabled else if the spi is routing to ph and spi is enabled, the spi will determine the pin direction 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 2 ddrh port h data direction this register controls the data direction of pin 2. if enabled the lcd segment output it will force the i/o state to be a input/output disabled else if the spi is routing to ph and spi is enabled, the spi will determine the pin direction else if eclk is enabled, it will force the pin to output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 1 ddrh port h data direction this register controls the data direction of pin 1. if enabled the lcd segment output it will force the i/o state to be a input/output disabled else if the sci1 is routing to ph and sci1 is enabled, the sci1 will determined the pin direction else if the spi is routing to ph and spi is enabled, the spi will determine the pin direction. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 0 ddrh port h data direction this register controls the data direction of pin 0. if enabled the lcd segment output it will force the i/o state to be a input/output disabled else if the sci1 is routing to ph and sci1 is enabled, the sci1 will determined the pin direction else if the spi is routing to ph and spi is enabled, the spi will determine the pin direction t. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input.
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 120 freescale semiconductor 2.3.50 pim reserved registers 2.3.51 port h pull device enable register (perh) 2.3.52 port h polarity select register (ppsh) address 0x0263 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r00000000 w reset 00000000 figure 2-47. pim reserved register) address 0x0264 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r perh7 perh6 perh5 perh4 perh3 perh2 perh1 perh0 w reset 11111111 figure 2-48. port h pull device enable register (perh) table 2-42. perh register field descriptions field description 7-0 perh port h pull device enable ?nable pull devices on input pins these bits con?ure whether a pull device is activated, if the associated pin is used as an input. this bit has no effect if the pin is used as an output. out of reset all pull device is enabled. 1 pull device enabled. 0 pull device disabled. address 0x0265 access: user read/write 1 76543210 r ppsh7 ppsh6 ppsh5 ppsh4 ppsh3 ppsh2 ppsh1 ppsh0 w reset 11111111 figure 2-49. port h polarity select register (ppsh)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 121 2.3.53 port h wired-or mode register (womh) 1 read: anytime. write: anytime. table 2-43. ppsh register field descriptions field description 7-0 ppsh port h pull device select ?etermine pull device polarity on input pins this register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 1 a rising edge on the associated port h pin sets the associated ?g bit in the pifh register. a pull-down device is connected to the associated port h pin, if enabled by the associated bit in register perh and if the port is used as input. 0 a falling edge on the associated port h pin sets the associated ?g bit in the pifh register.a pull-up device is connected to the associated port h pin, if enabled by the associated bit in register perh and if the port is used as input. address 0x0266 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r womh7 womh6 womh5 womh4 womh3 womh2 womh1 womh0 w reset 00000000 figure 2-50. port h wired-or mode register (womh) table 2-44. woms register field descriptions field description 7-0 womh port h wired-or mode ?nable wired-or functionality this register con?ures the output pins as wired-or. if enabled the output is driven active low only (open-drain). a logic level of ??is not driven.this allows a multipoint connection of several serial modules. these bits have no in?ence on pins used as inputs. 1 output buffers operate as open-drain outputs. 0 output buffers operate as push-pull outputs.
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 122 freescale semiconductor 2.3.54 port h routing register (pthrr) this register configures the re-routing of sci1 on alternative pins on port m/h. 2.3.55 pim reserved register address 0x0267 access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r0000000 pthrr0 w reset 00000000 = unimplemented or reserved figure 2-51. port hrouting register (pthrr) table 2-45. port h routing register field descriptions field description 0 pthrr port h routing register this register controls the routing of sci1. 0 sci1 routed to ph[1:0] 1 sci1 routed to pm[1:0] address 0x0268-0x26f access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 2-52. pim reserved register
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 123 2.3.56 port ad data register (pt0ad) 2.3.57 port ad data register (pt1ad) address 0x0270 access: user read/write 1 1 read: anytime. the data source is depending on the data direction value. write: anytime 76543210 r0000 pt0ad3 pt0ad2 pt0ad1 pt0ad0 w altern. function -- -- -- -- an11 an10 an9 an8 reset 00000000 figure 2-53. port ad data register (pt0ad) table 2-46. pt0ad register field descriptions field description 3-0 pt0ad port ad general purpose input/output data ?ata register, atd an analog input when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. address 0x0271 access: user read/write 1 1 read: anytime. the data source is depending on the data direction value. write: anytime 76543210 r pt1ad7 pt1ad6 pt1ad5 pt1ad4 pt1ad3 pt1ad2 pt1ad1 pt1ad0 w kwad7 kwad6 kwad5 kwad4 kwad3 kwad2 kwad1 kwad0 altern. function an7 an6 an5 an4 an3 an2 an1 an0 reset 00000000 figure 2-54. port ad data register (pt1ad)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 124 freescale semiconductor 2.3.58 port ad data direction register (ddr0ad) note due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on pt1ad registers, when changing the ddr1ad register. table 2-47. pt1ad register field descriptions field description 7-0 pt1ad port ad general purpose input/output data ?ata register, atd an analog input when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. address 0x0272 access: user read/write 1 1 read: anytime write: anytime 76543210 r0000 ddr0ad3 ddr0ad2 ddr0ad1 ddr0ad0 w reset 00000000 figure 2-55. port ad data direction register (ddr1ad) table 2-48. ddr0ad register field descriptions field description 3-0 ddr0ad port ad data direction this bit determines whether the associated pin is an input or output. to use the digital input function the atd digital input enable register (atddien) has to be set to logic level ?? 1 associated pin is con?ured as output 0 associated pin is con?ured as input
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 125 2.3.59 port ad data direction register (ddr1ad) note due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on pt1ad registers, when changing the ddr1ad register. 2.3.60 pim reserved register address 0x0273 access: user read/write 1 1 read: anytime write: anytime 76543210 r ddr1ad7 ddr1ad6 ddr1ad5 ddr1ad4 ddr1ad3 ddr1ad2 ddr1ad1 ddr1ad0 w reset 00000000 figure 2-56. port ad data direction register (ddr1ad) table 2-49. ddr1ad register field descriptions field description 7-0 ddr1ad port ad data direction this bit determines whether the associated pin is an input or output. to use the digital input function the atd digital input enable register (atddien) has to be set to logic level ?? 1 associated pin is con?ured as output 0 associated pin is con?ured as input address 0x0274 access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 2-57. pim reserved register
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 126 freescale semiconductor 2.3.61 pim reserved registers 2.3.62 port ad pull up enable register (per0ad) 2.3.63 port ad pull up enable register (per1ad) address 0x0275 access: user read/write 1 1 read: anytime write: anytime 76543210 r00000000 w reset 00000000 figure 2-58. pim reserved register address 0x0276 access: user read/write 1 1 read: anytime write: anytime 76543210 r0000 per0ad3 per0ad2 per0ad1 per0ad0 w reset 00000000 figure 2-59. port ad pull up enable register (per0ad) table 2-50. per0ad register field descriptions field description 3-0 per0ad port ad pull-up enable ?nable pull-up device on input pin this bit controls whether a pull device on the associated port input pin is active. if a pin is used as output this bit has no effect. the polarity is selected by the related polarity select register bit. 1 pull device enabled 0 pull device disabled address 0x0277 access: user read/write 1 76543210 r per1ad7 per1ad6 per1ad5 per1ad4 per1ad3 per1ad2 per1ad1 per1ad0 w reset 00000000 figure 2-60. port ad pull up enable register (per1ad)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 127 2.3.64 pim reserved registers 2.3.65 port r data register (ptr) 1 read: anytime write: anytime table 2-51. per1ad register field descriptions field description 7-0 per1ad port ad pull-up enable ?nable pull-up device on input pin this bit controls whether a pull device on the associated port input pin is active. if a pin is used as output this bit has no effect. the polarity is selected by the related polarity select register bit. 1 pull device enabled 0 pull device disabled address 0x0278-0x27f access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved u = unaffected by reset figure 2-61. pim reserved registers address 0x0280 access: user read/write 1 1 read: anytime the data source is depending on the data direction value. write: anytime 76543210 r ptr7 ptr6 ptr5 ptr4 ptr3 ptr2 ptr1 ptr0 w scl sda txcan1 rxcan1 altern. function fp27 fp18 fp17 fp112 ioc1_7 ioc1_6 ioc0_7 ioc0_6 reset 00000000 figure 2-62. port r data register (ptr)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 128 freescale semiconductor table 2-52. ptr register field descriptions field description 7 ptr port r general purpose input/output data ?ata register, lcd segment driver output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the general purpose i/o function 6 ptr port r general purpose input/output data ?ata register, lcd segment driver output, scl of iic when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the iic and general purpose i/o function the iic function takes over the general purpose i/o function 5 ptr port r general purpose input/output data ?ata register, lcd segment driver output, sda of iic when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the iic and general purpose i/o function the iic function takes over the general purpose i/o function 4 ptr port r general purpose input/output data ?ata register, lcd segment driver output when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the lcd segment driver output takes precedence over the general purpose i/o function 3-2 ptr port r general purpose input/output data ?ata register, tim1channels when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the tim1 output compare function takes precedence over the general purpose i/o function 1
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 129 2.3.66 port r input register (ptir) 1 ptr port r general purpose input/output data ?ata register, tim0 channels,tx of can1 when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the tx of can1 function takes precedence over the tim0 and general purpose i/o function the tim0 output compare function takes precedence over the general purpose i/o function 2 0 ptr port r general purpose input/output data ?ata register, tim0 channels,rx of can1 when not used with the alternative function, the associated pin can be used as general purpose i/o. in general purpose output mode the register bit value is driven to the pin. if the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered pin input state is read. the rx of can1 function takes precedence over the tim0 and general purpose i/o function the tim0 output compare function takes precedence over the general purpose i/o function 3 1 in order tim input capture to be function correctly, the corresponding ddrr bit should be set as input state 2 in order tim input capture to be function correctly, the corresponding ddrr bit should be set as input state 3 in order tim input capture to be function correctly, the corresponding ddrr bit should be set as input state address 0x0281 access: user read 1 1 read: anytime. write:never, writes to this register have no effect. 76543210 r ptir7 ptir6 ptir5 ptir4 ptir3 ptir2 ptir1 ptir0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-63. port r input register (ptir) table 2-53. ptir register field descriptions field description 7-0 ptir port r input data this register always reads back the buffered state of the associated pins. this can also be used to detect overload or short circuit conditions on output pins. table 2-52. ptr register field descriptions (continued) field description
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 130 freescale semiconductor 2.3.67 port r data direction register (ddrr) address 0x0282 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddrr7 ddrr6 ddrr5 ddrr4 ddrr3 ddrr2 ddrr1 ddrr0 w reset 00000000 figure 2-64. port r data direction register (ddrr) table 2-54. ddrr register field descriptions field description 7 ddrr port r data direction this register controls the data direction of pin 7.this register con?ures pin as either input or output. if lcd segment driver output is enabled, it will force as input/output disabled. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 6 ddrr port r data direction this register controls the data direction of pin 6.this register con?ures pin as either input or output. if lcd segment driver output is enabled, it will force as input/output disabled else if iic is routing to pr and iic is enabled, it will force as open-drain output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 5 ddrr port r data direction this register controls the data direction of pin 5.this register con?ures pin as either input or output. if lcd segment driver output is enabled, it will force as input/output disabled else if iic is routing to pr and iic is enabled, it will force as open-drain output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 4 ddrr port r data direction this register controls the data direction of pin 4.this register con?ures pin as either input or output. if lcd segment driver output is enabled, it will force as input/output disabled. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 3-2 ddrr port r data direction this register controls the data direction of pin 3-2.this register con?ures pin as either input or output. if tim1/ are routing to the pr and tim1 output compare functions are enabled, it will force as output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input.
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 131 note due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on ptr or ptir registers, when changing the ddrr register. 2.3.68 pim reserved registers 2.3.69 port r pull device enable register (perr) 1 ddrr port r data direction this register controls the data direction of pin 1.this register con?ures pin as either input or output. if tim0 are routing to the pr and tim0 output compare functions are enabled, it will force as output. else if tx of can1 is routing to pr and ca1 is enabled, it will force as output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 0 ddrr port r data direction this register controls the data direction of pin 3-0.this register con?ures pin as either input or output. if tim1/tim0 are routing to the pr and tim1/tim0 output compare functions are enabled, it will force as output. else if rx of can1 is routing to pr and ca1 is enabled, it will force as input. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. address 0x0283 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r00000000 w reset 00000000 figure 2-65. pim reserved register address 0x0284 access: user read/write 1 76543210 r perr7 perr6 perr5 perr4 perr3 perr2 perr1 perr0 w reset 11111111 figure 2-66. port r pull device enable register (perr) table 2-54. ddrr register field descriptions (continued) field description
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 132 freescale semiconductor 2.3.70 port r polarity select register (ppsr) 2.3.71 port r wired-or mode register (womr) 1 read: anytime. write: anytime. table 2-55. perr register field descriptions field description 7-0 perr port r pull device enable ?nable pull devices on input pins these bits con?ure whether a pull device is activated, if the associated pin is used as an input. this bit has no effect if the pin is used as an output. out of reset all pull devices are enabled. 1 pull device enabled. 0 pull device disabled. address 0x0285 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ppsr7 ppsr6 ppsr5 ppsr4 ppsr3 ppsr2 ppsr1 ppsr0 w reset 11111111 figure 2-67. port r polarity select register (ppsr) table 2-56. ppsr register field descriptions field description 7-0 ppsr port r pull device select ?etermine pull device polarity on input pins this register selects whether a pull-down or a pull-up device is connected to the pin. 1 a rising edge on the associated port r pin sets the associated ?g bit in the pifs register. a pull-down device is connected to the associated pin, if enabled and if the pin is used as input. 0 a falling edge on the associated port r pin sets the associated ?g bit in the pifs register. a pull-up device is connected to the associated pin, if enabled and if the pin is used as input. address 0x0286 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r womr7 womr6 womr5 womr4 womr3 womr2 womr1 womr0 w reset 00000000 figure 2-68. port r wired-or mode register (womr)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 133 2.3.72 pim reserved registers 2.3.73 port t interrupt enable register (piet) read: anytime. table 2-57. womr register field descriptions field description 7-0 womr port r wired-or mode ?nable wired-or functionality this register con?ures the output pins as wired-or. if enabled the output is driven active low only (open-drain). a logic level of ??is not driven.this allows a multipoint connection of several serial modules. these bits have no in?ence on pins used as inputs. 1 output buffers operate as open-drain outputs. 0 output buffers operate as push-pull outputs. address 0x0287 access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved u = unaffected by reset figure 2-69. pim reserved registers address 0x0288 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r piet7 piet6 piet5 piet4 piet3 piet2 piet1 piet0 w reset 00000000 figure 2-70. port tinterrupt enable register (piet) table 2-58. piet register field descriptions field description 7-0 piet port t interrupt enable this register disables or enables on a per-pin basis the edge sensitive external interrupt associated with port t. 1 interrupt is enabled. 0 interrupt is disabled (interrupt ?g masked).
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 134 freescale semiconductor 2.3.74 port t interrupt flag register (pift) 2.3.75 port s interrupt enable register (pies) read: anytime. address 0x0289 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r pift7 pift6 pift5 pift4 pift3 pift2 pift1 pift0 w reset 00000000 figure 2-71. port tinterrupt flag register (pift) table 2-59. pift register field descriptions field description 6-5 pift port t interrupt ?g each ?g is set by an active edge on the associated input pin. this could be a rising or a falling edge based on the state of the ppst register. to clear this ?g, write logic level 1 to the corresponding bit in the pifs register. writing a 0 has no effect. 1 1 active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). 0 no active edge pending. 1 in order to enable the key wakup function, need to disable the lcd fp function ?st address 0x028a access: user read/write 1 1 read: anytime. write: anytime. 76543210 r0 pies6 pies5 0 pies3 pies2 00 w reset 00000000 figure 2-72. port s interrupt enable register (pies) table 2-60. pies register field descriptions field description 6-5 3-2 pies port s interrupt enable this register disables or enables on a per-pin basis the edge sensitive external interrupt associated with port s. 1 interrupt is enabled. 0 interrupt is disabled (interrupt ?g masked).
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 135 2.3.76 port s interrupt flag register (pifs) 2.3.77 port ad interrupt enable register (pie1ad) read: anytime. address 0x028b access: user read/write 1 1 read: anytime. write: anytime. 76543210 r0 pifs6 pifs5 0 pifs3 pifs2 00 w reset 00000000 figure 2-73. port s interrupt flag register (pifs) table 2-61. pifs register field descriptions field description 6-5 3-2 pifs port s interrupt ?g each ?g is set by an active edge on the associated input pin. this could be a rising or a falling edge based on the state of the ppss register. to clear this ?g, write logic level 1 to the corresponding bit in the pifs register. writing a 0 has no effect. 1 active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). 0 no active edge pending. address 0x028c access: user read/write 1 1 read: anytime. write: anytime. 76543210 r pie1ad7 pie1ad6 pie1ad5 pie1ad4 pie1ad3 pie1ad2 pie1ad1 pie1ad0 w reset 00000000 figure 2-74. port ad interrupt enable register (pie1ad) table 2-62. pie1ad register field descriptions field description 7-0 pie1ad port ad interrupt enable this register disables or enables on a per-pin basis the edge sensitive external interrupt associated with port ad. 1 interrupt is enabled. 0 interrupt is disabled (interrupt ?g masked).
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 136 freescale semiconductor 2.3.78 port ad interrupt flag register (pif1ad) 2.3.79 port r interrupt enable register (pier) read: anytime. address 0x028d access: user read/write 1 1 read: anytime. write: anytime. 76543210 r pif1ad7 pif1ad6 pif1ad5 pif1ad4 pif1ad3 pif1ad2 pif1ad1 pif1ad0 w reset 00000000 figure 2-75. port f interrupt flag register (pif1ad) table 2-63. pif1ad register field descriptions field description 7-0 pif1ad port ad interrupt ?g each ?g is set by an active edge on the associated input pin. to clear this ?g, write logic level 1 to the corresponding bit in the pif1ad register. writing a 0 has no effect. 1 1 active falling edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). 0 no active edge pending. 1 in order to enable the key wakeup function, need to set the atdienl ?st. address 0x028e access: user read/write 1 1 read: anytime. write: anytime. 76543210 r000 pier4 pier3 pier2 pier1 pier0 w reset 00000000 figure 2-76. port r interrupt enable register (pier) table 2-64. pier register field descriptions field description 4-0 pier port r interrupt enable this register disables or enables on a per-pin basis the edge sensitive external interrupt associated with port r. 1 interrupt is enabled. 0 interrupt is disabled (interrupt ?g masked).
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 137 2.3.80 port r interrupt flag register (pifr) 2.3.81 port u data register (ptu) address 0x028f access: user read/write 1 1 read: anytime. write: anytime. 76543210 r000 pifr4 pifr3 pifr2 pifr1 pifr0 w reset 00000000 figure 2-77. port r interrupt flag register (pifr) table 2-65. pifr register field descriptions field description 4-0 pifr port r interrupt ?g each ?g is set by an active edge on the associated input pin. this could be a rising or a falling edge based on the state of the ppsr register. to clear this ?g, write logic level 1 to the corresponding bit in the pifr register. writing a 0 has no effect. 1 active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). 0 no active edge pending. address 0x0290 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ptu7 ptu6 ptu5 ptu4 ptu3 ptu2 ptu1 ptu0 w ioc0_3 ioc0_2 ioc0_1 ioc0_0 altern. function m1c1p m1c1m m1c0p m1c0m m0c1p m0c1m m0c0p m0c0m m1sinp m1sinm m1cosp m1cosm m0sinp m0sinm m0cosp m0cosm reset 00000000 figure 2-78. port u data register (ptu)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 138 freescale semiconductor 2.3.82 port u input register (ptiu) table 2-66. ptu register field descriptions field description 7,5,3,1 ptu port u general purpose input/output data ?ata register, motor driver pwm output port u 7,5,3,1 pins are associated with the motor pwm output . when not used with the alternative functions, these pins can be used as general purpose i/o. if the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the ssd takes precedence over the motor driver and general purpose i/o function the motor driver pwm takes precedence over the general purpose i/o function. 6,4,2,0 ptu port u general purpose input/output data ?ata register, motor driver pwm output, tim0 channels 3-0 port u 6,4,2,0 pins are associated with the motor pwm output and tim0 channels 3-0 when not used with the alternative functions, these pins can be used as general purpose i/o. if the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the ssd takes precedence over the motor driver and and tim0 and general purpose i/o function the motor driver pwm takes precedence over the tim0 and the general purpose i/o function. the tim0 output function takes precedence over the general purpose i/o function if related channel is enabled 1 1 in order tim input capture to be function correctly, the corresponding ddru bit shoud be set to 0. also the corresponding srru bit should be set to 0. address 0x0291 access: user read 1 1 read: anytime. write:never, writes to this register have no effect. 76543210 r ptiu7 ptiu6 ptiu5 ptiu4 ptiu3 ptiu2 ptiu1 ptiu0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-79. port u input register (ptiu) table 2-67. ptiu register field descriptions field description 7-0 ptiu port u input data this register always reads back the buffered state of the associated pins. this can also be used to detect overload or short circuit conditions on output pins.
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 139 2.3.83 port u data direction register (ddru) note due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on ptu or ptiu registers, when changing the ddru register. 2.3.84 pim reserved registers address 0x0292 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddru7 ddru6 ddru5 ddru4 ddru3 ddru2 ddru1 ddru0 w reset 00000000 figure 2-80. port u data direction register (ddru) table 2-68. ddru register field descriptions field description 7,5,3,1 ddru port u data direction if enabled the motor driver pwm output it will force the i/o state to be output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 6,4,2,0 ddru port u data direction if enabled the motor driver pwm output it will force the i/o state to be output. else if corresponding tim0 output compare channel is enabled, it will be force as output 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. address 0x0293 access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved u = unaffected by reset figure 2-81. pim reserved registers
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 140 freescale semiconductor 2.3.85 port u pull device enable register (peru) 2.3.86 port u polarity select register (ppsu) address 0x0294 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r peru7 peru6 peru5 peru4 peru3 peru2 peru1 peru0 w reset 00000000 figure 2-82. port u pull device enable register (peru) table 2-69. peru register field descriptions field description 7-0 peru port u pull device enable ?nable pull devices on input pins these bits con?ure whether a pull device is activated, if the associated pin is used as an input. this bit has no effect if the pin is used as an output. out of reset no pull device is enabled. 1 pull device enabled. 0 pull device disabled. address 0x0295 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ppsu7 ppsu6 ppsu5 ppsu4 ppsu3 ppsu2 ppsu1 ppsu0 w reset 00000000 figure 2-83. port u polarity select register (ppsu) table 2-70. ppsu register field descriptions field description 7-0 ppsu port u pull device select ?etermine pull device polarity on input pins this register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 1 a pull-down device is connected to the associated port u pin, if enabled by the associated bit in register peru and if the port is used as input. 0 a pull-up device is connected to the associated port u pin, if enabled by the associated bit in register peru and if the port is used as input.
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 141 2.3.87 port u slew rate register(srru) 2.3.88 port u routing register (pturr) address 0x0296 access: user read/write 1 1 read: anytime. write: anytime. 76543210 r srru7 srru6 srru5 srru4 srru3 srru2 srru1 srru0 w reset 00000000 figure 2-84. port u polarity select register (srru) table 2-71. srru register field descriptions field description 7-0 srru port u slew rate register ?etermine the slew rate on the pins 1 1 enable the slew rate control and disables the digital input buffer 0 disable the slew rate control and enable the digital input buffer 1 when change srru from non-zero value to zero value or vice versa, it will need to wait about 300 nanoseconds delay before the slew rate control to be real function as setting. when enter stop, to save the power, the slew rate control will be force to off state. after wakeup from stop, it will also need to wait about 300 nanoseconds before slew rate control to be function as setting. address 0x0297 access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r0000 pturr0 pturr0 00 w reset 00000000 = unimplemented or reserved u = unaffected by reset figure 2-85. port u routing register (pturr)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 142 freescale semiconductor this register configures the re-routing of tim0 channels on alternative pins on port m/u. table 2-72. port u routing register field descriptions field description 2 pturr port u routing register this register controls the routing of ioc0_2 0 ioc0_2 routed to pu4 1 ioc0_2 routed to pm0 3 pturr port u routing register this register controls the routing of ioc0_3 0 ioc0_3 routed to pu6 1 ioc0_3 routed to pm1
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 143 2.3.89 port v data register (ptv) address 0x0298 access: user read/write 1 1 read: anytime. write: anytime 76543210 r ptv7 ptv6 ptv5 ptv4 ptv3 ptv2 ptv1 ptv0 w ss miso 2 2 special spi/pwm&iic priority pwm7 pwm6 pwm5 pwm4 sdasck mosi scl ioc1_3 ioc1_2 ioc1_1 ioc1_0 ioc0_7 ioc0_6 ioc0_5 ioc0_4 altern. function m3c1p m3c1m m3c0p m3c0m m2c1p m2c1m m2c0p m2c0m m3sinp m3sinm m3cosp m3cosm m2sinp m2sinm m2cosp m2cosm reset 00000000 figure 2-86. port v data register (ptv) table 2-73. ptv register field descriptions field description 7,5 ptv port v general purpose input/output data ?ata register, motor driver pwm output port v pins are associated with the motor pwm output . when not used with the alternative functions, these pins can be used as general purpose i/o. if the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the ssd takes precedence over the motor driver and general purpose i/o function the motor driver pwm takes precedence over the general purpose i/o function. 6, 4 ptv port v general purpose input/output data ?ata register, motor driver pwm output, tim1 channel 3,2 port v pins are associated with the motor pwm output and tim1 channels 3-2 when not used with the alternative functions, these pins can be used as general purpose i/o. if the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the ssd takes precedence over the motor driver and tim0,tim1 and general purpose i/o function the motor driver pwm takes precedence over the tim0, tim1 and the general purpose i/o function. the tim0 output compare function takes precedence over the tim1 and the general purpose i/o function. the tim1 output compare function takes precedence over the general purpose i/o function if the related channels is enabled 1
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 144 freescale semiconductor 3 ptv port v general purpose input/output data ?ata register, motor driver pwm output, ss of spi, pwm channel 7, sda of iic port v pin 3 is associated with the motor pwm output, spi and pwm channel 4 and iic . when not used with the alternative functions, this pin can be used as general purpose i/o. if the associated data direction bit of this pins is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the ssd takes precedence over the motor driver, spi, pwm channel 7, iic and general purpose i/o function the motor driver pwm takes precedence over the spi, pwm channel 7, iic and general purpose i/o function. the sda of iic takes precedence over the pwm channel 7, spi and general purpose i/o function the pwm channel 7 takes precedence over the spi and general purpose i/o function the ss of spi takes precedence over the general purpose i/o function 2 ptv port v general purpose input/output data ?ata register, motor driver pwm output, tim1 channel 1, sck of spi, pwm channel 6 port v pin 2 is associated with the motor pwm output, spi and pwm channel 7 . when not used with the alternative functions, this pin can be used as general purpose i/o. if the associated data direction bit of this pins is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the ssd takes precedence over the motor driver, tim0, tim1, spi, pwm channel 6, iic and general purpose i/o function the motor driver pwm takes precedence over the tim0,tim1, spi, pwm channel 6 and general purpose i/o function. the tim0 channel 5 output function takes precedence over the tim1, spi, pwm channel 6 and general purpose i/o function. the tim1 channel 1 output function takes precedence over the spi, pwm channels 6 and the general purpose i/o function if related channel is enabled 1 the sck of spi takes precedence over the pwm channel 6 and the general purpose i/o function the pwm channel 6 takes precedence over the general purpose i/o function table 2-73. ptv register field descriptions field description
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 145 2.3.90 port v input register (ptiv) 1 ptv port v general purpose input/output data ?ata register, motor driver pwm output, mosi of spi, pwm channel 5 port v pin 1 is associated with the motor pwm output, spi and pwm channel 6 . when not used with the alternative functions, this pin can be used as general purpose i/o. if the associated data direction bit of this pins is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the ssd takes precedence over the motor driver, spi, pwm channel 5, iic and general purpose i/o function the motor driver pwm takes precedence over the spi, pwm channel 5 and general purpose i/o function. the mosi of spi takes precedence over the pwm channel 5 and the general purpose i/o function the pwm channel 5 takes precedence over the general purpose i/o function 0 ptv port v general purpose input/output data ?ata register, motor driver pwm output, tim1 channel 0, miso of spi, pwm channel 4, scl of iic port v pin 0 is associated with the motor pwm output, tim1 channel 0, spi and pwm channel 5 and iic . when not used with the alternative functions, this pin can be used as general purpose i/o. if the associated data direction bit of this pins is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. the ssd takes precedence over the motor driver, tim0, tim1, spi, pwm channel 4, iic and general purpose i/o function the motor driver pwm takes precedence over the tim0, tim1, spi, pwm channel 4, iic and general purpose i/o function. the tim0 output compare function take precedence over the tim1, spi, pwm channel 4, iic and general purpose i/o function. the tim1 output compare function take precedence over the spi, pwm channel4, iic and general purpose i/o 1 the scl of iic takes presentees over the pwm channel 4, spi and general purpose i/o function the pwm channel 4 takes precedence over the spi and the general purpose i/o function the miso of spi takes precedence over the general purpose i/o function 1 in order tim1 input capture to be function correctly, need to disable all the output functions on the corresponding channel. also the corresponding srrv bit should be set to 0. address 0x0299 access: user read 1 1 read: anytime. write:never, writes to this register have no effect. 76543210 r ptiv7 ptiv6 ptiv5 ptiv4 ptiv3 ptiv2 ptiv1 ptiv0 w reset uuuuuuuu = unimplemented or reserved u = unaffected by reset figure 2-87. port v input register (ptiv) table 2-73. ptv register field descriptions field description
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 146 freescale semiconductor 2.3.91 port v data direction register (ddrv) table 2-74. ptiv register field descriptions field description 7-0 ptiv port v input data this register always reads back the buffered state of the associated pins. this can also be used to detect overload or short circuit conditions on output pins. address 0x029a access: user read/write 1 1 read: anytime. write: anytime. 76543210 r ddrv7 ddrv6 ddrv5 ddrv4 ddrv3 ddrv2 ddrv1 ddrv0 w reset 00000000 figure 2-88. port v data direction register (ddrv) table 2-75. ddrv register field descriptions field description 7 ddrv port v data direction if enabled the motor driver pwm output it will force the i/o state to be output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 6 ddrv port v data direction if enabled the motor driver pwm output or enable the tim1 channel 3 output compare function, it will force the i/o state to be output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 5 ddrv port v data direction if enabled the motor driver pwm output it will force the i/o state to be output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 4 ddrv port v data direction if enabled the motor driver pwm output or enable the tim1 channel 2 output compare function, it will force the i/o state to be output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input.
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 147 note due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on ptv or ptiv registers, when changing the ddrv register. 3 ddrv port v data direction if enabled the motor driver pwm output it will force the i/o state to be output else if iic is routing to pv and iic is enabled, it will force the i/o state to be output, also the input buffer is enabled else if pwm7 is routing to pv and pwm 7 is con?ured as pwm channel output, it will force the i/o state to be output else if pwm7 is routing to pv and pwm7 is con?ured as pwm emergency shutdown, it will force the i/o state to be input else if spi is routing to pv and spi is enabled, spi will determine the i/o state. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 2 ddrv port v data direction if enabled the motor driver pwm output it will force the i/o state to be output else if corresponding tim1 output compare channle is enabled, it will be force as output else if spi is routing to pv and spi is enabled, spi will determined the i/o state else if pwm6 is routing to pv, it will force the i/o state to be output. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 1 ddrv port v data direction if enabled the motor driver pwm output it will force the i/o state to be output else if spi is routing to pv and spi is enabled, spi will determined the i/o state else if pwm5 is routing to pv, it will force i/o state to be output else if spi is routing to pv and spi is enabled, spi will determined the i/o state. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. 0 ddrv port v data direction if enabled the motor driver pwm output it will force the i/o state to be output else if corresponding tim1 output compare channel is enabled, it will be forced as output else if iic is routing to pv and iic is enabled, it will force the i/o state to be output, also the input buffer is enabled else if pwm4 is routing to pv, it will force i/o state to be output else if spi is routing to pv and spi is enabled, spi will determine the i/o state. 1 associated pin is con?ured as output. 0 associated pin is con?ured as input. table 2-75. ddrv register field descriptions (continued) field description
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 148 freescale semiconductor 2.3.92 pim reserved registers 2.3.93 port v pull device enable register (perv) 2.3.94 port v polarity select register (ppsv) address 0x029b access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r00000000 w reset 00000000 = unimplemented or reserved u = unaffected by reset figure 2-89. pim reserved registers address 0x029c access: user read/write 1 1 read: anytime. write: anytime. 76543210 r perv7 perv6 perv5 perv4 perv3 perv2 perv1 perv0 w reset 00000000 figure 2-90. port v pull device enable register (perv) table 2-76. perv register field descriptions field description 7-0 perv port v pull device enable ?nable pull devices on input pins these bits con?ure whether a pull device is activated, if the associated pin is used as an input. this bit has no effect if the pin is used as an output. out of reset no pull device is enabled. 1 pull device enabled. 0 pull device disabled. address 0x029d access: user read/write 1 76543210 r ppsv7 ppsv6 ppsv5 ppsv4 ppsv3 ppsv2 ppsv1 ppsv0 w reset 00000000 figure 2-91. port v polarity select register (ppsv)
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 149 2.3.95 port v slew rate register(srrv) 1 read: anytime. write: anytime. table 2-77. ppsv register field descriptions field description 7-0 ppsv port v pull device select ?etermine pull device polarity on input pins this register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 1 a pull-down device is connected to the associated port v pin, if enabled by the associated bit in register perv and if the port is used as input. 0 a pull-up device is connected to the associated port v pin, if enabled by the associated bit in register perv and if the port is used as input. address 0x029e access: user read/write 1 1 read: anytime. write: anytime. 76543210 r srrv7 srrv6 srrv5 srrv4 srrv3 srrv2 srrv1 srrv0 w reset 00000000 figure 2-92. port v polarity select register (srrv) table 2-78. srrv register field descriptions field description 7-0 srrv port v slew rate register ?etermine the slew rate on the pins 1 1 enable the slew rate control and disables the digital input buffer 2 0 disable the slew rate control and enable the digital input buffer 1 when change srrv from non-zero value to zero value or vice versa, it will need to wait about 300 nanoseconds delay before the slew rate control to be real function as setting. when enter stop, to save the power, the slew rate control will be force to off state. after wakeup from stop, it will also need to wait about 300 nanoseconds before slew rate control to be function as setting. 2 when mc function is disabled and iic/spi/pwm async shutdown are routing to pv and enabled, the corresponding digital input buffer will be always enabled
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 150 freescale semiconductor 2.3.96 port v routing register (ptvrr) this register configures the re-routing of tim1 channels on alternative pins on port m/v. 2.4 functional description 2.4.1 general each pin except bkgd can act as general purpose i/o. in addition each pin can act as an output or input of a peripheral module. 2.4.2 registers a set of con?uration registers is common to all ports with exception of the atd port ( table 2-80 ). all registers can be written at any time, however a speci? con?uration might not become active. for example selecting a pull-up device: this device does not become active while the port is used as a push-pull output. address 0x029f access: user read 1 1 read: always reads 0x00 write: unimplemented 76543210 r0000 ptvrr3 ptvrr2 00 w reset 00000000 = unimplemented or reserved u = unaffected by reset figure 2-93. port v routing register (ptvrr) table 2-79. port v routing register field descriptions field description 2 ptvrr port v routing register this register controls the routing of ioc1_2 0 ioc1_2 routed to pv4 1 ioc1_2 routed to pm2 3 ptvrr port v routing register this register controls the routing of ioc1_3. 0 ioc1_3 routed to pv6 1 ioc1_3 routed to pm3
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 151 2.4.2.1 data register (portx, ptx) this register holds the value driven out to the pin if the pin is used as a general purpose i/o. writing to this register has only an effect on the pin if the pin is used as general purpose output. when reading this address, the buffered state of the pin is returned if the associated data direction register bit is set to ?? if the data direction register bits are set to logic level ?? the contents of the data register is returned. this is independent of any other con?uration ( figure 2-94 ). 2.4.2.2 input register (ptix) this register is read-only and always returns the buffered state of the pin ( figure 2-94 ). 2.4.2.3 data direction register (ddrx) this register de?es whether the pin is used as an general purpose input or an output. if a peripheral module controls the pin the contents of the data direction register is ignored ( figure 2-94 ). independent of the pin usage with a peripheral module this register determines the source of data when reading the associated data register address ( 2.4.2.1/2-151 ). note due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on port data or port input registers, when changing the data direction register. table 2-80. register availability per port 1 1 each cell represents one register with individual con?uration bits port data input data direction reduced drive pull enable polarity select wired- or mode slew rate interrupt enable interrupt flag routing ayes-yesnoyes------ byes-yes ------ t yes yes yes no yes yes - - yes yes yes s yes yes yes no yes yes yes - yes yes yes m yes yes yes no yes yes yes - no no no r yes yes yes no yes yes yes - yes yes no pyesyesyesnoyesyes----yes h yes yes yes no yes yes yes - - - yes ad yes - yes no yes - - - yes yes - u yes yes yes no yes yes - yes - - yes v yes yes yes no yes yes - yes - - yes
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 152 freescale semiconductor figure 2-94. illustration of i/o pin functionality 2.4.2.4 pull device enable register (perx) this register turns on a pull-up or pull-down device on the related pins determined by the associated polarity select register ( 2.4.2.5/2-152 ). the pull device becomes active only if the pin is used as an input or as a wired-or output. some peripheral module only allow certain con?urations of pull devices to become active. refer to the respective bit descriptions. 2.4.2.5 polarity select register (ppsx) this register selects either a pull-up or pull-down device if enabled. it becomes only active if the pin is used as an input. a pull-up device can be activated if the pin is used as a wired-or output. 2.4.2.6 wired-or mode register (womx) if the pin is used as an output this register turns off the active high drive. this allows wired-or type connections of outputs. 2.4.2.7 interrupt enable register (piex) if the pin is used as an interrupt input this register serves as a mask to the interrupt ?g to enable/disable the interrupt. 2.4.2.8 interrupt ?g register (pifx) if the pin is used as an interrupt input this register holds the interrupt ?g after a valid pin event. pt ddr output enable module enable 1 0 1 1 0 0 pin pti data out module
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 153 2.4.2.9 slew rate register(srrx) 2.4.2.10 this register select the either slew rate enable or slew rate disable on the motor dirverpad. .module routing register (ptxrrx) this register allows software re-con?uration of the pinouts of the different package options for speci? peripherals: ptxrrx supports the re-routing of the pwm channels to alternative ports 2.4.3 pins and ports note please refer to the device pinout section to determine the pin availability in the different package options. 2.4.3.1 bkgd pin the bkgd pin is associated with the bdm module. during reset, the bkgd pin is used as modc input. 2.4.3.2 port ad this port is associated with the atd. 2.4.3.3 port a, b these ports are associated with lcd, irq, xirq and api_extclk 2.4.3.4 port h this port is associated with lcd/spi/iic. 2.4.3.5 port m this port is associated with the pwm/sci1/pwm. 2.4.3.6 port p this port is associated with the pwm. 2.4.3.7 port r this port is associated with lcd/iic. 2.4.3.8 port s this port is associated with spi/sci/iic/pwm/can.
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 154 freescale semiconductor 2.4.3.9 port t this port is associated with lcd and tim. 2.4.3.10 port u this port is associated with the motor driver/tim0. 2.4.3.11 port v this port is associated with the motor driver/tim1/spi/iic/pwm. 2.4.4 pin interrupts ports t, s, r, ad offer pin interrupt capability. the interrupt enable as well as the sensitivity to rising or falling edges can be individually con?ured on per-pin basis. all bits/pins in a port share the same interrupt vector. interrupts can be used with the pins con?ured as inputs or outputs. an interrupt is generated when a bit in the port interrupt ?g register and its corresponding port interrupt enable bit are both set. the pin interrupt feature is also capable to wake up the cpu when it is in stop or wait mode. a digital ?ter on each pin prevents pulses ( figure 2-96 ) shorter than a speci?d time from generating an interrupt. the minimum time varies over process conditions, temperature and voltage ( figure 2-95 and table 2-81 ). figure 2-95. interrupt glitch filter on port t,s,r, and ad(pps=0) glitch, ?tered out, no interrupt ?g set valid pulse, interrupt ?g set t pign t pval uncertain
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 155 table 2-81. pulse detection criteria figure 2-96. pulse illustration a valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly. the ?ters are continuously clocked by the bus clock in run and wait mode. in stop mode the clock is generated by an rc-oscillator in the port integration module. to maximize current saving the rc oscillator runs only if the following condition is true on any pin individually: sample count <= 4 and interrupt enabled (pie=1) and interrupt ?g not set (pif=0). 2.5 initialization information 2.5.1 port data and data direction register writes it is not recommended to write portx/ptx and ddrx in a word access. when changing the register pins from inputs to outputs, the data may have extra transitions during the write access. initialize the port data register before enabling the outputs. pulse mode stop stop 1 1 these values include the spread of the oscillator frequency over tempera- ture, voltage and process. unit ignored t pulse 3 bus clocks t pulse t pign uncertain 3 < t pulse < 4 bus clocks t pign < t pulse < t pval valid t pulse 4 bus clocks t pulse t pval t pulse
port integration module (s12xhypimv1) mc9s12xhy-family reference manual, rev. 1.01 156 freescale semiconductor
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 157 chapter 3 memory mapping control (s12xmmcv4) revision history 3.1 introduction this section describes the functionality of the module mapping control (mmc) sub-block of the s12x platform. the block diagram of the mmc is shown in figure 3-1 . the mmc module controls the multi-master priority accesses, the selection of internal resources . internal buses, including internal memories and peripherals, are controlled in this module. the local address space for each master is translated to a global memory space. rev. no. (item no.) date (submitted by) sections affected substantial change(s) v04.09 01-feb-08 - minor changes v04.10 17-feb-09 - minor changes v04.11 30-jun-10 3.3.2.7/3-169 - removed confusing statements in epage description
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 158 freescale semiconductor 3.1.1 terminology 3.1.2 features the main features of this block are: paging capability to support a global 8mb memory address space bus arbitration between the masters cpu, bdm simultaneous accesses to different resources 1 (internal, and peripherals) (see figure 3-1 ) resolution of target bus access collision mcu operation mode control mcu security control separate memory map schemes for each master cpu, bdm rom control bits to enable the on-chip flash or rom selection generation of system reset when cpu accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes table 3-1. acronyms and abbreviations logic level ? voltage that corresponds to boolean true state logic level ? voltage that corresponds to boolean false state 0x represents hexadecimal number x represents logic level don? care byte 8-bit data word 16-bit data local address based on the 64kb memory space (16-bit address) global address based on the 8mb memory space (23-bit address) aligned address address on even boundary mis-aligned address address on odd boundary bus clock system clock. refer to crg block guide. single-chip modes normal single-chip mode special single-chip mode normal modes normal single-chip mode special modes special single-chip mode ns normal single-chip mode ss special single-chip mode unimplemented areas areas which are accessible by the pages (rpage,ppage,epage) and not implemented prr port replacement registers pru port replacement unit located on the emulator side mcu microcontroller unit nvm non-volatile memory; flash, data flash or rom ifr information row sector located on the top of nvm. for test purposes. 1. resources are also called targets.
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 159 3.1.3 s12x memory mapping the s12x architecture implements a number of memory mapping schemes including a cpu 8mb global map, de?ed using a global page (gpage) register and dedicated 23-bit address load/store instructions. a bdm 8mb global map, de?ed using a global page (bdmgpr) register and dedicated 23-bit address load/store instructions. a (cpu or bdm) 64kb local map, de?ed using speci? resource page (rpage, epage and ppage) registers and the default instruction set. the 64kb visible at any instant can be considered as the local map accessed by the 16-bit (cpu or bdm) address. the mmc module performs translation of the different memory mapping schemes to the speci? global (physical) memory implementation. 3.1.4 modes of operation this subsection lists and brie? describes all operating modes supported by the mmc. 3.1.4.1 power saving modes run mode mmc is functional during normal run mode. wait mode mmc is functional during wait mode. stop mode mmc is inactive during stop mode. 3.1.4.2 functional modes single chip modes in normal and special single chip mode the internal memory is used. 3.1.5 block diagram figure 3-1 shows a block diagram of the mmc.
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 160 freescale semiconductor figure 3-1. mmc block diagram 3.2 external signal description the user is advised to refer to the soc guide for port con?uration and location of external bus signals. some pins may not be bonded out in all implementations. table 3-2 outlines the pin names and functions. it also provides a brief description of their operation. table 3-2. external input signals associated with the mmc signal i/o description availability modc i mode input latched after reset (active low) cpu bdm target bus controller dbg mmc address decoder & priority peripherals pgmflash data flash ram
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 161 3.3 memory map and registers 3.3.1 module memory map a summary of the registers associated with the mmc block is shown in figure 3-2 . detailed descriptions of the registers and bits are given in the subsections that follow. 3.3.2 register descriptions address register name bit 7 6 5 4 3 2 1 bit 0 0x000a reserved r 0 0 0 0 0 0 0 0 w 0x000b mode r modc 0000000 w 0x0010 gpage r 0 gp6 gp5 gp4 gp3 gp2 gp1 gp0 w 0x0011 direct r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w 0x0012 reserved r 0 0 0 0 0 0 0 0 w 0x0013 mmcctl1 r mgramon 0 dfifron pgmifron 0000 w 0x0014 reserved r 0 0 0 0 0 0 0 0 w 0x0015 ppage r pix7 pix6 pix5 pix4 pix3 pix2 pix1 pix0 w 0x0016 rpage r rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 w 0x0017 epage r ep7 ep6 ep5 ep4 ep3 ep2 ep1 ep0 w = unimplemented or reserved figure 3-2. mmc register summary
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 162 freescale semiconductor 3.3.2.1 mode register (mode) read: anytime. write: only if a transition is allowed (see figure 3-5 ). the mode bits of the mode register are used to establish the mcu operating mode. figure 3-4. figure 3-5. mode transition diagram when mcu is unsecured address: 0x000b prr 76543210 r modc 0000000 w reset modc 1 0000000 1. external signal (see table 3-2 ). = unimplemented or reserved figure 3-3. mode register (mode) table 3-3. mode field descriptions field description 7 modc mode select bit ?this bit controls the current operating mode during reset high (inactive). the external mode pin modc determines the operating mode during reset low (active). the state of the pin is latched into the respective register bit after the reset signal goes inactive (see figure 3-3 ). write restrictions exist to disallow transitions between certain modes. figure 3-5 illustrates all allowed mode changes. attempting non authorized transitions will not change the mode bits, but it will block further writes to these register bits except in special modes. write accesses to the mode register are blocked when the device is secured. normal single-chip 1 special single-chip 0 reset (ss) 0 reset 1 (ns) reset transition done by external pins (modc) transition done by write access to the mode register 1 state state state
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 163 3.3.2.2 global page index register (gpage) read: anytime write: anytime the global page index register is used to construct a 23 bit address in the global map format. it is only used when the cpu is executing a global instruction (gldaa, gldab, gldd, glds, gldx, gldy,gstaa, gstab, gstd, gsts, gstx, gsty) (see cpu block guide). the generated global address is the result of concatenation of the cpu local address [15:0] with the gpage register [22:16] (see figure 3-7 ). figure 3-7. gpage address mapping example 3-1. this example demonstrates usage of the gpage register ldx #0x5000 ;set gpage offset to the value of 0x5000 movb #0x14, gpage ;initialize gpage register with the value of 0x14 gldaa x ;load accu a from the global address 0x14_5000 address: 0x0010 76543210 r0 gp6 gp5 gp4 gp3 gp2 gp1 gp0 w reset 00000000 = unimplemented or reserved figure 3-6. global page index register (gpage) table 3-4. gpage field descriptions field description 6? gp[6:0] global page index bits 6? these page index bits are used to select which of the 128 64kb pages is to be accessed. bit16 bit 0 bit15 bit22 cpu address [15:0] gpage register [6:0] global address [22:0]
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 164 freescale semiconductor 3.3.2.3 direct page register (direct) read: anytime write: anytime in special modes, one time only in other modes. this register determines the position of the 256b direct page within the memory map.it is valid for both global and local mapping scheme. figure 3-9. direct address mapping bits [22:16] of the global address will be formed by the gpage[6:0] bits in case the cpu executes a global instruction in direct addressing mode or by the appropriate local address to the global address expansion (refer to section 3.4.2.1.1, ?xpansion of the local address map ). example 3-2. this example demonstrates usage of the direct addressing mode movb #0x80,direct ;set direct register to 0x80. write once only. ;global data accesses to the range 0xxx_80xx can be direct. ;logical data accesses to the range 0x80xx are direct. ldy <00 ;load the y index register from 0x8000 (direct access). ;< operator forces direct access on some assemblers but in ;many cases assemblers are ?irect page aware?and can ;automatically select direct mode. address: 0x0011 76543210 r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w reset 00000000 figure 3-8. direct register (direct) table 3-5. direct field descriptions field description 7? dp[15:8] direct page index bits 15? ?these bits are used by the cpu when performing accesses using the direct addressing mode. the bits from this register form bits [15:8] of the address (see figure 3-9 ). bit15 bit0 bit7 bit22 cpu address [15:0] global address [22:0] bit8 bit16 dp [15:8]
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 165 3.3.2.4 mmc control register (mmcctl1) read: anytime. . write: refer to each bit description. 3.3.2.5 program page index register (ppage) read: anytime address: 0x0013 prr 76543210 r mgramon 0 dfifron pgmifron 0000 w reset 00000000 = unimplemented or reserved figure 3-10. mmc control register (mmcctl1) table 3-6. mmcctl1 field descriptions field description 7 mgramon flash memory controller scratch ram visible in the global memory map write: anytime this bit is used to made the flash memory controller scratch ram visible in the global memory map. 0 not visible in the global memory map. 1 visible in the global memory map. 5 dfifron data flash information row (ifr) visible in the global memory map write: anytime this bit is used to made the ifr sector of the data flash visible in the global memory map. 0 not visible in the global memory map. 1 visible in the global memory map. 4 pgmifron program flash information row (ifr) visible in the global memory map write: anytime this bit is used to map the ifr sector of the program flash to address range 0x40_000-0x40_3fff of the global memory map. 0 not visible in the global memory map. 1 visible in the global memory map. address: 0x0015 76543210 r pix7 pix6 pix5 pix4 pix3 pix2 pix1 pix0 w reset 11111110 figure 3-11. program page index register (ppage)
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 166 freescale semiconductor write: anytime these eight index bits are used to page 16kb blocks into the flash page window located in the local (cpu or bdm) memory map from address 0x8000 to address 0xbfff (see figure 3-12 ). this supports accessing up to 4mb of flash (in the global map) within the 64kb local map. the ppage register is effectively used to construct paged flash addresses in the local map format. the cpu has special access to read and write this register directly during execution of call and rtc instructions.. figure 3-12. ppage address mapping note writes to this register using the special access of the call and rtc instructions will be complete before the end of the instruction execution. the reset value of 0xfe ensures that there is linear flash space available between addresses 0x4000 and 0xffff out of reset. the ?ed 16k page from 0xc000-0xffff is the page number 0xff. 3.3.2.6 ram page index register (rpage) table 3-7. ppage field descriptions field description 7? pix[7:0] program page index bits 7? ?these page index bits are used to select which of the 256 flash or rom array pages is to be accessed in the program page window. address: 0x0016 76543210 r rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 w reset 11111101 figure 3-13. ram page index register (rpage) bit14 bit0 1 address [13:0] ppage register [7:0] global address [22:0] bit13 bit21 address: cpu local address or bdm local address
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 167 read: anytime write: anytime these eight index bits are used to page 4kb blocks into the ram page window located in the local (cpu or bdm) memory map from address 0x1000 to address 0x1fff (see figure 3-14 ) . this supports accessing up to 1022kb of ram (in the global map) within the 64kb local map. the ram page index register is effectively used to construct paged ram addresses in the local map format . figure 3-14. rpage address mapping note because ram page 0 has the same global address as the register space, it is possible to write to registers through the ram space when rpage = 0x00. the reset value of 0xfd ensures that there is a linear ram space available between addresses 0x1000 and 0x3fff out of reset. the ?ed 4k page from 0x2000?x2fff of ram is equivalent to page 254 (page number 0xfe). the ?ed 4k page from 0x3000?x3fff of ram is equivalent to page 255 (page number 0xff). note the page 0xfd (reset value) contains unimplemented area in the range not occupied by ram if ramsize is less than 12kb (refer to section 3.4.2.3, ?mplemented memory map ). table 3-8. rpage field descriptions field description 7? rp[7:0] ram page index bits 7? these page index bits are used to select which of the 256 ram array pages is to be accessed in the ram page window. bit18 bit0 bit11 0 address [11:0] rpage register [7:0] global address [22:0] bit12 bit19 0 address: cpu local address or bdm local address 0
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 168 freescale semiconductor the two xed 4kb pages (0xfe, 0xff) contain unimplemented area in the range not occupied by ram if ramsize is less than 8kb (refer to section 3.4.2.3, ?mplemented memory map ).
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 169 3.3.2.7 data flash page index register (epage) read: anytime write: anytime these eight index bits are used to page 1kb blocks into the data flash page window located in the local (cpu or bdm) memory map from address 0x0800 to address 0x0bff (see figure 3-16 ). this supports accessing up to 256kb of data flash (in the global map) within the 64kb local map. the data flash page index register is effectively used to construct paged data flash addresses in the local map format. figure 3-16. epage address mapping address: 0x0017 76543210 r ep7 ep6 ep5 ep4 ep3 ep2 ep1 ep0 w reset 11111110 figure 3-15. data flash page index register (epage) table 3-9. epage field descriptions field description 7? ep[7:0] data flash page index bits 7? ?these page index bits are used to select which of the 256 data flash array pages is to be accessed in the data flash page window. bit16 bit0 bit9 address [9:0] epage register [7:0] global address [22:0] bit10 bit17 0 0 1 00 address: cpu local address or bdm local address
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 170 freescale semiconductor 3.4 functional description the mmc block performs several basic functions of the s12x sub-system operation: mcu operation modes, priority control, address mapping, select signal generation and access limitations for the system. each aspect is described in the following subsections. 3.4.1 mcu operating mode normal single-chip mode there is no external bus in this mode. the mcu program is executed from the internal memory and no external accesses are allowed. special single-chip mode this mode is generally used for debugging single-chip operation, boot-strapping or security related operations. the active background debug mode is in control of the cpu code execution and the bdm ?mware is waiting for serial commands sent through the bkgd pin. there is no external bus in this mode. 3.4.2 memory map scheme 3.4.2.1 cpu and bdm memory map scheme the bdm ?mware lookup tables and bdm register memory locations share addresses with other modules; however they are not visible in the global memory map during users code execution. the bdm memory resources are enabled only during the read_bd and write_bd access cycles to distinguish between accesses to the bdm memory area and accesses to the other modules. (refer to bdm block guide for further details). when the mcu enters active bdm mode, the bdm ?mware lookup tables and the bdm registers become visible in the local memory map in the range 0xff00-0xffff (global address 0x7f_ff00 - 0x7f_ffff) and the cpu begins execution of ?mware commands or the bdm begins execution of hardware commands. the resources which share memory space with the bdm module will not be visible in the global memory map during active bdm mode. please note that after the mcu enters active bdm mode the bdm ?mware lookup tables and the bdm registers will also be visible between addresses 0xbf00 and 0xbfff if the ppage register contains value of 0xff. .
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 171 figure 3-17. expansion of the local address map 0x7f_ffff 0x00_0000 0x14_0000 0x10_0000 0x00_0800 epage rpage ppage cpu and bdm local memory map global memory map 0xffff reset vectors 0xc000 0x8000 unpaged 0x4000 0x1000 0x0000 16kb flash window 0x0c00 0x2000 0x0800 8kb ram 4kb ram window reserved 2kb registers 1kb data flash window 16kb flash unpaged 16kb flash 2kb registers 2kb ram 253*4kb paged ram 256*1kb paged data flash 253 *16kb paged flash 16kb flash (ppage 0xfd) 8kb ram 16kb flash (ppage 0xfe) 16kb flash (ppage 0xff) 0x00_1000 0x0f_e000 0x13_fc00 0x40_0000 0x7f_4000 0x7f_8000 0x7f_c000 1m minus 2kb 256kb 4mb 2.75mb unimplemented space
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 172 freescale semiconductor 3.4.2.1.1 expansion of the local address map expansion of the cpu local address map the program page index register in mmc allows accessing up to 4mb of flash or rom in the global memory map by using the eight page index bits to page 256 16kb blocks into the program page window located from address 0x8000 to address 0xbfff in the local cpu memory map. the page value for the program page window is stored in the ppage register. the value of the ppage register can be read or written by normal memory accesses as well as by the call and rtc instructions (see section 3.5.1, ?all and rtc instructions ). control registers, vector space and parts of the on-chip memories are located in unpaged portions of the 64kb local cpu address space. the starting address of an interrupt service routine must be located in unpaged memory unless the user is certain that the ppage register will be set to the appropriate value when the service routine is called. however an interrupt service routine can call other routines that are in paged memory. the upper 16kb block of the local cpu memory space (0xc000?xffff) is unpaged. it is recommended that all reset and interrupt vectors point to locations in this area or to the other unpaged sections of the local cpu memory map. the ram page index register allows accessing up to 1mb minus 2kb of ram in the global memory map by using the eight rpage index bits to page 4kb blocks into the ram page window located in the local cpu memory space from address 0x1000 to address 0x1fff. the data flash page index register epage allows accessing up to 256kb of data flash in the system by using the eight epage index bits to page 1kb blocks into the data flash page window located in the local cpu memory space from address 0x0800 to address 0x0bff.
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 173 expansion of the bdm local address map ppage, rpage, and epage registers are also used for the expansion of the bdm local address to the global address. these registers can be read and written by the bdm. the bdm expansion scheme is the same as the cpu expansion scheme. 3.4.2.2 global addresses based on the global page cpu global addresses based on the global page the seven global page index bits allow access to the full 8mb address map that can be accessed with 23 address bits. this provides an alternative way to access all of the various pages of flash, ram and data flash. the gpage register is used only when the cpu is executing a global instruction (see section 3.3.2.2, ?lobal page index register (gpage) ). the generated global address is the result of concatenation of the cpu local address [15:0] with the gpage register [22:16] (see figure 3-7 ). bdm global addresses based on the global page the seven bdmgpr global page index bits allow access to the full 8mb address map that can be accessed with 23 address bits. this provides an alternative way to access all of the various pages of flash, ram and data flash. the bdm global page index register (bdmgpr) is used only in the case the cpu is executing a ?mware command which uses a global instruction (like gldd, gstd) or by a bdm hardware command (like write_w, write_byte, read_w, read_byte). see the bdm block guide for further details. the generated global address is a result of concatenation of the bdm local address with the bdmgpr register [22:16] in the case of a hardware command or concatenation of the cpu local address and the bdmgpr register [22:16] in the case of a ?mware command (see figure 3-18 ).
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 174 freescale semiconductor figure 3-18. bdmgpr address mapping 3.4.2.3 implemented memory map the global memory spaces reserved for the internal resources (ram, data flash, and flash) are not determined by the mmc module. size of the individual internal resources are however xed in the design of the device cannot be changed by the user. please refer to the soc guide for further details. figure 3-19 and table 3-10 show the memory spaces occupied by the on-chip resources. please note that the memory spaces have ?ed top addresses. table 3-10. global implemented memory space internal resource $address ram ram_low = 0x10_0000 minus ramsize 1 1 ramsize is the hexadecimal value of ram size in bytes data flash df_high = 0x10_0000 plus dflashsize 2 2 dflashsize is the hexadecimal value of dflash size in bytes flash flash_low = 0x80_0000 minus flashsize 3 3 flashsize is the hexadecimal value of flash size in bytes bit16 bit0 bit15 bit22 bdm local address bdmgpr register [6:0] global address [22:0] bit16 bit0 bit15 bit22 cpu local address bdmgpr register [6:0] global address [22:0] bdm hardware command bdm firmware command
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 175 in single-chip modes accesses by the cpu (except for ?mware commands) to any of the unimplemented areas (see figure 3-19 ) will result in an illegal access reset (system reset) in case of no mpu error. bdm accesses to the unimplemented areas are allowed but the data will be unde?ed.no misaligned word access from the bdm module will occur; these accesses are blocked in the bdm module (refer to bdm block guide). misaligned word access to the last location of ram is performed but the data will be unde?ed. misaligned word access to the last location of any global page (64kb) by any global instruction, is performed by accessing the last byte of the page and the ?st byte of the same page, considering the above mentioned misaligned access cases.
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 176 freescale semiconductor figure 3-19. s12x cpu & bdm global address mapping 0x7f_ffff 0x00_0000 0x13_ffff 0x0f_ffff data flash ram 0x00_07ff epage rpage ppage 0x3f_ffff cpu and bdm local memory map global memory map flashsize ramsize 0xffff reset vectors 0xc000 0x8000 unpaged 0x4000 0x1000 0x0000 16k flash window 0x0c00 0x2000 0x0800 8k ram 4k ram window reserved 2k registers 1k data flash window 16k flash unpaged 16k flash 2k registers unimplemented ram ram_low flash flash_low unimplemented flash unimplemented space df_high data flash resources dflashsize
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 177 3.4.3 chip bus control the mmc controls the address buses and the data buses that interface the s12x masters (cpu, bdm ) with the rest of the system (master buses). in addition the mmc handles all cpu read data bus swapping operations. all internal resources are connected to speci? target buses (see figure 3-20 ). figure 3-20. mmc block diagram cpu bdm target bus controller dbg mmc address decoder & priority peripherals pgmflash data flash ram s12x1 s12x0 xbus0
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 178 freescale semiconductor 3.4.3.1 master bus prioritization regarding access con?cts on target buses the arbitration scheme allows only one master to be connected to a target at any given time. the following rules apply when prioritizing accesses from different masters to the same target bus: cpu always has priority over bdm . bdm has priority over cpu when its access is stalled for more than 128 cycles. in the later case the suspect master will be stalled after ?ishing the current operation and the bdm will gain access to the bus. 3.5 initialization/application information 3.5.1 call and rtc instructions call and rtc instructions are uninterruptible cpu instructions that automate page switching in the program page window. the call instruction is similar to the jsr instruction, but the subroutine that is called can be located anywhere in the local address space or in any flash or rom page visible through the program page window. the call instruction calculates and stacks a return address, stacks the current ppage value and writes a new instruction-supplied value to the ppage register. the ppage value controls which of the 256 possible pages is visible through the 16kb program page window in the 64kb local cpu memory map. execution then begins at the address of the called subroutine. during the execution of the call instruction, the cpu performs the following steps: 1. writes the current ppage value into an internal temporary register and writes the new instruction- supplied ppage value into the ppage register 2. calculates the address of the next instruction after the call instruction (the return address) and pushes this 16-bit value onto the stack 3. pushes the temporarily stored ppage value onto the stack 4. calculates the effective address of the subroutine, re?ls the queue and begins execution at the new address this sequence is uninterruptible. there is no need to inhibit interrupts during the call instruction execution. a call instruction can be performed from any address to any other address in the local cpu memory space. the ppage value supplied by the instruction is part of the effective address of the cpu. for all addressing mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand in the instruction. in indexed-indirect variations of the call instruction a pointer speci?s memory locations where the new page value and the address of the called subroutine are stored. using indirect addressing for both the new page value and the address within the page allows usage of values calculated at run time rather than immediate values that must be known at the time of assembly. the rtc instruction terminates subroutines invoked by a call instruction. the rtc instruction unstacks the ppage value and the return address and re?ls the queue. execution resumes with the next instruction after the call instruction.
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 179 during the execution of an rtc instruction the cpu performs the following steps: 1. pulls the previously stored ppage value from the stack 2. pulls the 16-bit return address from the stack and loads it into the pc 3. writes the ppage value into the ppage register 4. re?ls the queue and resumes execution at the return address this sequence is uninterruptible. the rtc can be executed from anywhere in the local cpu memory space. the call and rtc instructions behave like jsr and rts instruction, they however require more execution cycles. usage of jsr/rts instructions is therefore recommended when possible and call/rtc instructions should only be used when needed. the jsr and rts instructions can be used to access subroutines that are already present in the local cpu memory map (i.e. in the same page in the program memory page window for example). however calling a function located in a different page requires usage of the call instruction. the function must be terminated by the rtc instruction. because the rtc instruction restores contents of the ppage register from the stack, functions terminated with the rtc instruction must be called using the call instruction even when the correct page is already present in the memory map. this is to make sure that the correct ppage value will be present on stack at the time of the rtc instruction execution.
memory mapping control (s12xmmcv4) mc9s12xhy-family reference manual, rev. 1.01 180 freescale semiconductor
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 181 chapter 4 interrupt (s12xintv2) 4.1 introduction the xint module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to either the cpu or the xgate module. the xint module supports: i bit and x bit maskable interrupt requests one non-maskable unimplemented op-code trap one non-maskable software interrupt (swi) or background debug mode request one non-maskable system call interrupt (sys) three non-maskable access violation interrupt one spurious interrupt vector request three system reset vector requests each of the i bit maskable interrupt requests can be assigned to one of seven priority levels supporting a ?xible priority scheme. for interrupt requests that are con?ured to be handled by the cpu, the priority scheme can be used to implement nested interrupt capability where interrupts from a lower level are automatically blocked if a higher level interrupt is being processed. interrupt requests con?ured to be handled by the xgate module can be nested one level deep. note the hprio register and functionality of the original s12 interrupt module is no longer supported, since it is superseded by the 7-level interrupt request priority scheme. table 4-1. revision history revision number revision date sections affected description of changes v02.00 01 jul 2005 4.1.2/4-182 initial v2 release, added new features: - xgate threads can be interrupted. - sys instruction vector. - access violation interrupt vectors. v02.04 11 jan 2007 4.3.2.2/4-187 4.3.2.4/4-188 - added notes for devices without xgate module. v02.05 20 mar 2007 4.4.6/4-194 - fixed priority de?ition for software exceptions. v02.06 07 jan 2008 4.5.3.1/4-196 - added clari?ation of ?ake-up from stop or wait by xirq with x bit set feature.
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 182 freescale semiconductor 4.1.1 glossary the following terms and abbreviations are used in the document. 4.1.2 features interrupt vector base register (ivbr) one spurious interrupt vector (at address vector base 1 + 0x0010). one non-maskable system call interrupt vector request (at address vector base + 0x0012). three non-maskable access violation interrupt vector requests (at address vector base + 0x0014 ? 0x0018). 2?09 i bit maskable interrupt vector requests (at addresses vector base + 0x001a?x00f2). each i bit maskable interrupt request has a con?urable priority level and can be con?ured to be handled by either the cpu or the xgate module 2 . i bit maskable interrupts can be nested, depending on their priority levels. one x bit maskable interrupt vector request (at address vector base + 0x00f4). one non-maskable software interrupt request (swi) or background debug mode vector request (at address vector base + 0x00f6). one non-maskable unimplemented op-code trap (trap) vector (at address vector base + 0x00f8). three system reset vectors (at addresses 0xfffa?xfffe). determines the highest priority xgate and interrupt vector requests, drives the vector to the xgate module or to the bus on cpu request, respectively. wakes up the system from stop or wait mode when an appropriate interrupt request occurs or whenever xirq is asserted, even if x interrupt is masked. xgate can wake up and execute code, even with the cpu remaining in stop or wait mode. table 4-2. terminology term meaning ccr condition code register (in the s12x cpu) dma direct memory access int interrupt ipl interrupt processing level isr interrupt service routine mcu micro-controller unit xgate refers to the xgate co-processor; xgate is an optional feature irq refers to the interrupt request associated with the irq pin xirq refers to the interrupt request associated with the xirq pin 1. the vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (ivbr, used as upper byte) and 0x00 (used as lower byte). 2. the irq interrupt can only be handled by the cpu
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 183 4.1.3 modes of operation run mode this is the basic mode of operation. wait mode in wait mode, the xint module is frozen. it is however capable of either waking up the cpu if an interrupt occurs or waking up the xgate if an xgate request occurs. please refer to section 4.5.3, ?ake up from stop or wait mode for details. stop mode in stop mode, the xint module is frozen. it is however capable of either waking up the cpu if an interrupt occurs or waking up the xgate if an xgate request occurs. please refer to section 4.5.3, ?ake up from stop or wait mode for details. freeze mode (bdm active) in freeze mode (bdm active), the interrupt vector base register is overridden internally. please refer to section 4.3.2.1, ?nterrupt vector base register (ivbr) for details.
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 184 freescale semiconductor 4.1.4 block diagram figure 4-1 shows a block diagram of the xint module. figure 4-1. xint block diagram 4.2 external signal description the xint module has no external signals. wake up current rqst ivbr one set per channel xgate interrupts xgate requests interrupt requests interrupt requests cpu vector address new ipl ipl (up to 108 channels) rqst xgate request route, priolvln priority level = bits from the channel con?uration in the associated con?uration register int_xgprio = xgate interrupt priority ivbr = interrupt vector base ipl = interrupt processing level priolvl0 priolvl1 priolvl2 int_xgprio peripheral vector id to xgate module priority decoder to cpu priority decoder non i bit maskable channels wake up xgate irq channel
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 185 4.3 memory map and register de?ition this section provides a detailed description of all registers accessible in the xint module. 4.3.1 module memory map table 4-3 gives an overview over all xint module registers. table 4-3. xint memory map address use access 0x0120 reserved 0x0121 interrupt vector base register (ivbr) r/w 0x0122?x0125 reserved 0x0126 xgate interrupt priority con?uration register (int_xgprio) r/w 0x0127 interrupt request con?uration address register (int_cfaddr) r/w 0x0128 interrupt request con?uration data register 0 (int_cfdata0) r/w 0x0129 interrupt request con?uration data register 1 (int_cfdata1) r/w 0x012a interrupt request con?uration data register 2 (int_cfdata2 r/w 0x012b interrupt request con?uration data register 3 (int_cfdata3) r/w 0x012c interrupt request con?uration data register 4 (int_cfdata4) r/w 0x012d interrupt request con?uration data register 5 (int_cfdata5) r/w 0x012e interrupt request con?uration data register 6 (int_cfdata6) r/w 0x012f interrupt request con?uration data register 7 (int_cfdata7) r/w
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 186 freescale semiconductor 4.3.2 register descriptions this section describes in address order all the xint module registers and their individual bits. address register name bit 7 654321 bit 0 0x0121 ivbr r ivb_addr[7:0]7 w 0x0126 int_xgprio r 00000 xilvl[2:0] w 0x0127 int_cfaddr r int_cfaddr[7:4] 0000 w 0x0128 int_cfdata0 r rqst 0000 priolvl[2:0] w 0x0129 int_cfdata1 r rqst 0000 priolvl[2:0] w 0x012a int_cfdata2 r rqst 0000 priolvl[2:0] w 0x012b int_cfdata3 r rqst 0000 priolvl[2:0] w 0x012c int_cfdata4 r rqst 0000 priolvl[2:0] w 0x012d int_cfdata5 r rqst 0000 priolvl[2:0] w 0x012e int_cfdata6 r rqst 0000 priolvl[2:0] w 0x012f int_cfdata7 r rqst 0000 priolvl[2:0] w = unimplemented or reserved figure 4-2. xint register summary
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 187 4.3.2.1 interrupt vector base register (ivbr) read: anytime write: anytime 4.3.2.2 xgate interrupt priority con?uration register (int_xgprio) read: anytime write: anytime address: 0x0121 76543210 r ivb_addr[7:0] w reset 1 1 1 11111 figure 4-3. interrupt vector base register (ivbr) table 4-4. ivbr field descriptions field description 7? ivb_addr[7:0] interrupt vector base address bits these bits represent the upper byte of all vector addresses. out of reset these bits are set to 0xff (i.e., vectors are located at 0xff10?xfffe) to ensure compatibility to previous s12 microcontrollers. note: a system reset will initialize the interrupt vector base register with ?xff before it is used to determine the reset vector address. therefore, changing the ivbr has no effect on the location of the three reset vectors (0xfffa?xfffe). note: if the bdm is active (i.e., the cpu is in the process of executing bdm ?mware code), the contents of ivbr are ignored and the upper byte of the vector address is ?ed as ?xff? address: 0x0126 76543210 r00000 xilvl[2:0] w reset 0 0 0 00001 = unimplemented or reserved figure 4-4. xgate interrupt priority con?uration register (int_xgprio) table 4-5. int_xgprio field descriptions field description 2? xilvl[2:0] xgate interrupt priority level ?the xilvl[2:0] bits configure the shared interrupt level of the xgate interrupts coming from the xgate module. out of reset the priority is set to the lowest active level (??. note: if the xgate module is not available on the device, write accesses to this register are ignored and read accesses to this register will return all 0.
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 188 freescale semiconductor 4.3.2.3 interrupt request con?uration address register (int_cfaddr) read: anytime write: anytime 4.3.2.4 interrupt request con?uration data registers (int_cfdata0?) the eight register window visible at addresses int_cfdata0? contains the con?uration data for the block of eight interrupt requests (out of 128) selected by the interrupt con?uration address register (int_cfaddr) in ascending order. int_cfdata0 represents the interrupt con?uration data register of the vector with the lowest address in this block, while int_cfdata7 represents the interrupt con?uration data register of the vector with the highest address, respectively. table 4-6. xgate interrupt priority levels priority xilvl2 xilvl1 xilvl0 meaning 0 0 0 interrupt request is disabled low 0 0 1 priority level 1 0 1 0 priority level 2 0 1 1 priority level 3 1 0 0 priority level 4 1 0 1 priority level 5 1 1 0 priority level 6 high 1 1 1 priority level 7 address: 0x0127 76543210 r int_cfaddr[7:4] 0000 w reset 0 0 0 10000 = unimplemented or reserved figure 4-5. interrupt con?uration address register (int_cfaddr) table 4-7. int_cfaddr field descriptions field description 7? int_cfaddr[7:4] interrupt request con?uration data register select bits ?these bits determine which of the 128 con?uration data registers are accessible in the 8 register window at int_cfdata0?. the hexadecimal value written to this register corresponds to the upper nibble of the lower byte of the address of the interrupt vector, i.e., writing 0xe0 to this register selects the con?uration data register block for the 8 interrupt vector requests starting with vector at address (vector base + 0x00e0) to be accessible as int_cfdata0?. note: writing all 0s selects non-existing con?uration registers. in this case write accesses to int_cfdata0? will be ignored and read accesses will return all 0.
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 189 address: 0x0128 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 (1) 1. please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-6. interrupt request con?uration data register 0 (int_cfdata0) address: 0x0129 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 (1) 1. please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-7. interrupt request con?uration data register 1 (int_cfdata1) address: 0x012a 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 (1) 1. please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-8. interrupt request con?uration data register 2 (int_cfdata2) address: 0x012b 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 (1) 1. please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-9. interrupt request con?uration data register 3 (int_cfdata3)
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 190 freescale semiconductor read: anytime write: anytime address: 0x012c 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 (1) 1. please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-10. interrupt request con?uration data register 4 (int_cfdata4) address: 0x012d 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 (1) 1. please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-11. interrupt request con?uration data register 5 (int_cfdata5) address: 0x012e 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 (1) 1. please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-12. interrupt request con?uration data register 6 (int_cfdata6) address: 0x012f 76543210 r rqst 0000 priolvl[2:0] w reset 0 0 0 00001 (1) 1. please refer to the notes following the priolvl[2:0] description below. = unimplemented or reserved figure 4-13. interrupt request con?uration data register 7 (int_cfdata7)
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 191 4.4 functional description the xint module processes all exception requests to be serviced by the cpu module. these exceptions include interrupt vector requests and reset vector requests. each of these exception types and their overall priority level is discussed in the subsections below. table 4-8. int_cfdata0? field descriptions field description 7 rqst xgate request enable this bit determines if the associated interrupt request is handled by the cpu or by the xgate module. 0 interrupt request is handled by the cpu 1 interrupt request is handled by the xgate module note: the irq interrupt cannot be handled by the xgate module. for this reason, the con?uration register for vector (vector base + 0x00f2) = irq vector address) does not contain a rqst bit. writing a 1 to the location of the rqst bit in this register will be ignored and a read access will return 0. note: if the xgate module is not available on the device, writing a 1 to the location of the rqst bit in this register will be ignored and a read access will return 0. 2? priolvl[2:0] interrupt request priority level bits the priolvl[2:0] bits con?ure the interrupt request priority level of the associated interrupt request. out of reset all interrupt requests are enabled at the lowest active level (?? to provide backwards compatibility with previous s12 interrupt controllers. please also refer to table 4-9 for available interrupt request priority levels. note: write accesses to con?uration data registers of unused interrupt channels will be ignored and read accesses will return all 0. for information about what interrupt channels are used in a speci? mcu, please refer to the device reference manual of that mcu. note: when vectors (vector base + 0x00f0?x00fe) are selected by writing 0xf0 to int_cfaddr, writes to int_cfdata2? (0x00f4?x00fe) will be ignored and read accesses will return all 0s. the corresponding vectors do not have con?uration data registers associated with them. note: when vectors (vector base + 0x0010?x001e) are selected by writing 0x10 to int_cfaddr, writes to int_cfdata1?nt_cfdata4 (0x0012?x0018) will be ignored and read accesses will return all 0s. the corresponding vectors do not have con?uration data registers associated with them. note: write accesses to the con?uration register for the spurious interrupt vector request (vector base + 0x0010) will be ignored and read accesses will return 0x07 (request is handled by the cpu, priolvl = 7). table 4-9. interrupt priority levels priority priolvl2 priolvl1 priolvl0 meaning 0 0 0 interrupt request is disabled low 0 0 1 priority level 1 0 1 0 priority level 2 0 1 1 priority level 3 1 0 0 priority level 4 1 0 1 priority level 5 1 1 0 priority level 6 high 1 1 1 priority level 7
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 192 freescale semiconductor 4.4.1 s12x exception requests the cpu handles both reset requests and interrupt requests. the xint module contains registers to con?ure the priority level of each i bit maskable interrupt request which can be used to implement an interrupt priority scheme. this also includes the possibility to nest interrupt requests. a priority decoder is used to evaluate the priority of a pending interrupt request. 4.4.2 interrupt prioritization after system reset all interrupt requests with a vector address lower than or equal to (vector base + 0x00f2) are enabled, are set up to be handled by the cpu and have a pre-con?ured priority level of 1. exceptions to this rule are the non-maskable interrupt requests and the spurious interrupt vector request at (vector base + 0x0010) which cannot be disabled, are always handled by the cpu and have a ?ed priority levels. a priority level of 0 effectively disables the associated i bit maskable interrupt request. if more than one interrupt request is con?ured to the same interrupt priority level the interrupt request with the higher vector address wins the prioritization. the following conditions must be met for an i bit maskable interrupt request to be processed. 1. the local interrupt enabled bit in the peripheral module must be set. 2. the setup in the con?uration register associated with the interrupt request channel must meet the following conditions: a) the xgate request enable bit must be 0 to have the cpu handle the interrupt request. b) the priority level must be set to non zero. c) the priority level must be greater than the current interrupt processing level in the condition code register (ccr) of the cpu (priolvl[2:0] > ipl[2:0]). 3. the i bit in the condition code register (ccr) of the cpu must be cleared. 4. there is no access violation interrupt request pending. 5. there is no sys, swi, bdm, trap, or xirq request pending. note all non i bit maskable interrupt requests always have higher priority than i bit maskable interrupt requests. if an i bit maskable interrupt request is interrupted by a non i bit maskable interrupt request, the currently active interrupt processing level (ipl) remains unaffected. it is possible to nest non i bit maskable interrupt requests, e.g., by nesting swi or trap calls. 4.4.2.1 interrupt priority stack the current interrupt processing level (ipl) is stored in the condition code register (ccr) of the cpu. this way the current ipl is automatically pushed to the stack by the standard interrupt stacking procedure. the new ipl is copied to the ccr from the priority level of the highest priority active interrupt request channel which is con?ured to be handled by the cpu. the copying takes place when the interrupt vector is fetched. the previous ipl is automatically restored by executing the rti instruction.
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 193 4.4.3 xgate requests if the xgate module is implemented on the device, the xint module is also used to process all exception requests to be serviced by the xgate module. the overall priority level of those exceptions is discussed in the subsections below. 4.4.3.1 xgate request prioritization an interrupt request channel is con?ured to be handled by the xgate module, if the rqst bit of the associated con?uration register is set to 1 (please refer to section 4.3.2.4, ?nterrupt request con?uration data registers (int_cfdata0?) ). the priority level con?uration (priolvl) for this channel becomes the xgate priority which will be used to determine the highest priority xgate request to be serviced next by the xgate module. additionally, xgate interrupts may be raised by the xgate module by setting one or more of the xgate channel interrupt ?gs (by using the sif instruction). this will result in an cpu interrupt with vector address vector base + (2 * channel id number), where the channel id number corresponds to the highest set channel interrupt ?g, if the xgie and channel rqst bits are set. the shared interrupt priority for the xgate interrupt requests is taken from the xgate interrupt priority con?uration register (please refer to section 4.3.2.2, ?gate interrupt priority con?uration register (int_xgprio) ). if more than one xgate interrupt request channel becomes active at the same time, the channel with the highest vector address wins the prioritization. 4.4.4 priority decoders the xint module contains priority decoders to determine the priority for all interrupt requests pending for the respective target. there are two priority decoders, one for each interrupt request target, cpu or xgate. the function of both priority decoders is basically the same with one exception: the priority decoder for the xgate module does not take the current xgate thread processing level into account. instead, xgate requests are handed to the xgate module including a 1-bit priority identi?r. the xgate module uses this additional information to decide if the new request can interrupt a currently running thread. the 1-bit priority identi?r corresponds to the most signi?ant bit of the priority level con?uration of the requesting channel. this means that xgate requests with priority levels 4, 5, 6 or 7 can interrupt running xgate threads with priority levels 1, 2 and 3. a cpu interrupt vector is not supplied until the cpu requests it. therefore, it is possible that a higher priority interrupt request could override the original exception which caused the cpu to request the vector. in this case, the cpu will receive the highest priority vector and the system will process this exception instead of the original request. if the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the cpu will default to that of the spurious interrupt vector.
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 194 freescale semiconductor note care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0010)). 4.4.5 reset exception requests the xint module supports three system reset exception request types (for details please refer to the clock and reset generator module (crg)): 1. pin reset, power-on reset, low-voltage reset, or illegal address reset 2. clock monitor reset request 3. cop watchdog reset request 4.4.6 exception priority the priority (from highest to lowest) and address of all exception vectors issued by the xint module upon request by the cpu is shown in table 4-10 . generally, all non-maskable interrupts have higher priorities than maskable interrupts. please note that between the three software interrupts (unimplemented op-code trap request, swi/bgnd request, sys request) there is no real priority de?ed because they cannot occur simultaneously (the s12xcpu executes one instruction at a time). table 4-10. exception vector map and priority vector address (1) 1. 16 bits vector address based source 0xfffe pin reset, power-on reset, low-voltage reset, illegal address reset 0xfffc clock monitor reset 0xfffa cop watchdog reset (vector base + 0x00f8) unimplemented op-code trap (vector base + 0x00f6) software interrupt instruction (swi) or bdm vector request (vector base + 0x0012) system call interrupt instruction (sys) (vector base + 0x0018) (reserved for future use) (vector base + 0x0016) xgate access violation interrupt request (2) 2. only implemented if device features both a memory protection unit (mpu) and an xgate co-processor (vector base + 0x0014) cpu access violation interrupt request (3) 3. only implemented if device features a memory protection unit (mpu) (vector base + 0x00f4) xirq interrupt request (vector base + 0x00f2) irq interrupt request (vector base + 0x00f0?x001a) device speci? i bit maskable interrupt sources (priority determined by the associated con?uration registers, in descending order) (vector base + 0x0010) spurious interrupt
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 195 4.5 initialization/application information 4.5.1 initialization after system reset, software should: initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xff10?xfff9). initialize the interrupt processing level con?uration data registers (int_cfaddr, int_cfdata0?) for all interrupt vector requests with the desired priority levels and the request target (cpu or xgate module). it might be a good idea to disable unused interrupt requests. if the xgate module is used, setup the xgate interrupt priority register (int_xgprio) and con?ure the xgate module (please refer the xgate block guide for details). enable i maskable interrupts by clearing the i bit in the ccr. enable the x maskable interrupt by clearing the x bit in the ccr (if required). 4.5.2 interrupt nesting the interrupt request priority level scheme makes it possible to implement priority based interrupt request nesting for the i bit maskable interrupt requests handled by the cpu. i bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority, so that there can be up to seven nested i bit maskable interrupt requests at a time (refer to figure 4- 14 for an example using up to three nested interrupt requests). i bit maskable interrupt requests cannot be interrupted by other i bit maskable interrupt requests per default. in order to make an interrupt service routine (isr) interruptible, the isr must explicitly clear the i bit in the ccr (cli). after clearing the i bit, i bit maskable interrupt requests with higher priority can interrupt the current isr. an isr of an interruptible i bit maskable interrupt request could basically look like this: service interrupt, e.g., clear interrupt ?gs, copy data, etc. clear i bit in the ccr by executing the instruction cli (thus allowing interrupt requests with higher priority) process data return from interrupt by executing the instruction rti
interrupt (s12xintv2) mc9s12xhy-family reference manual, rev. 1.01 196 freescale semiconductor figure 4-14. interrupt processing example 4.5.3 wake up from stop or wait mode 4.5.3.1 cpu wake up from stop or wait mode every i bit maskable interrupt request which is con?ured to be handled by the cpu is capable of waking the mcu from stop or wait mode. to determine whether an i bit maskable interrupts is quali?d to wake up the cpu or not, the same settings as in normal run mode are applied during stop or wait mode: if the i bit in the ccr is set, all i bit maskable interrupts are masked from waking up the mcu. an i bit maskable interrupt is ignored if it is con?ured to a priority level below or equal to the current ipl in ccr. i bit maskable interrupt requests which are con?ured to be handled by the xgate module are not capable of waking up the cpu. the x bit maskable interrupt request can wake up the mcu from stop or wait mode at anytime, even if the x bit in ccr is set. if the x bit maskable interrupt request is used to wake-up the mcu with the x bit in the ccr set, the associated isr is not called. the cpu then resumes program execution with the instruction following the wai or stop instruction. this features works following the same rules like any interrupt request, i.e. care must be taken that the x interrupt request used for wake-up remains active at least until the system begins execution of the instruction following the wai or stop instruction; otherwise, wake-up may not occur. 4.5.3.2 xgate wake up from stop or wait mode interrupt request channels which are con?ured to be handled by the xgate module are capable of waking up the xgate module. interrupt request channels handled by the xgate module do not affect the state of the cpu. 0 reset 4 0 7 6 5 4 3 2 1 0 l4 7 0 4 l1 (pending) l7 l3 (pending) rti 4 0 3 0 rti rti 1 0 0 rti stacked ipl processing levels ipl in ccr
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 197 chapter 5 background debug module (s12xbdmv2) 5.1 introduction this section describes the functionality of the background debug module (bdm) sub-block of the hcs12x core platform. the background debug module (bdm) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal cpu intervention. all interfacing with the bdm is done via the bkgd pin. the bdm has enhanced capability for maintaining synchronization between the target and host while allowing more ?xibility in clock rates. this includes a sync signal to determine the communication rate and a handshake signal to indicate when an operation is complete. the system is backwards compatible to the bdm of the s12 family with the following exceptions: taggo command no longer supported by bdm external instruction tagging feature now part of dbg module bdm register map and register content extended/modi?d global page access functionality enabled but not active out of reset in emulation modes (if modes available) clksw bit set out of reset in emulation modes (if modes available). family id readable from ?mware rom at global address 0x7fff0f (value for hcs12x devices is 0xc1) 5.1.1 features the bdm includes these distinctive features: single-wire communication with host development system enhanced capability for allowing more ?xibility in clock rates sync command to determine communication rate go_until command hardware handshake protocol to increase the performance of the serial communication table 5-1. revision history revision number revision date sections affected description of changes v02.00 07 mar 2006 - first version of s12xbdmv2 v02.01 14 may 2008 - introduced standardized revision history table
background debug module (s12xbdmv2) mc9s12xhy-family reference manual, rev. 1.01 198 freescale semiconductor active out of reset in special single chip mode nine hardware commands using free cycles, if available, for minimal cpu intervention hardware commands not requiring active bdm 14 ?mware commands execute from the standard bdm ?mware lookup table software control of bdm operation during wait mode software selectable clocks global page access functionality enabled but not active out of reset in emulation modes (if modes available) clksw bit set out of reset in emulation modes (if modes available). when secured, hardware commands are allowed to access the register space in special single chip mode, if the non-volatile memory erase test fail. family id readable from ?mware rom at global address 0x7fff0f (value for hcs12x devices is 0xc1) bdm hardware commands are operational until system stop mode is entered (all bus masters are in stop mode) 5.1.2 modes of operation bdm is available in all operating modes but must be enabled before ?mware commands are executed. some systems may have a control bit that allows suspending thefunction during background debug mode. 5.1.2.1 regular run modes all of these operations refer to the part in run mode and not being secured. the bdm does not provide controls to conserve power during run mode. normal modes general operation of the bdm is available and operates the same in all normal modes. special single chip mode in special single chip mode, background operation is enabled and active out of reset. this allows programming a system with blank memory. emulation modes (if modes available) in emulation mode, background operation is enabled but not active out of reset. this allows debugging and programming a system in this mode more easily. 5.1.2.2 secure mode operation if the device is in secure mode, the operation of the bdm is reduced to a small subset of its regular run mode operation. secure operation prevents bdm and cpu accesses to non-volatile memory (flash and/or eeprom) other than allowing erasure. for more information please see section 5.4.1, ?ecurity .
background debug module (s12xbdmv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 199 5.1.2.3 low-power modes the bdm can be used until all bus masters (e.g., cpu or xgate or others depending on which masters are available on the soc) are in stop mode. when cpu is in a low power mode (wait or stop mode) all bdm ?mware commands as well as the hardware background command can not be used respectively are ignored. in this case the cpu can not enter bdm active mode, and only hardware read and write commands are available. also the cpu can not enter a low power mode during bdm active mode. if all bus masters are in stop mode, the bdm clocks are stopped as well. when bdm clocks are disabled and one of the bus masters exits from stop mode the bdm clocks will restart and bdm will have a soft reset (clearing the instruction register, any command in progress and disable the ack function). the bdm is now ready to receive a new command. 5.1.3 block diagram a block diagram of the bdm is shown in figure 5-1 . figure 5-1. bdm block diagram 5.2 external signal description a single-wire interface pin called the background debug interface (bkgd) pin is used to communicate with the bdm system. during reset, this pin is a mode select input which selects between normal and special modes of operation. after reset, this pin becomes the dedicated serial interface pin for the background debug mode. enbdm clksw bdmact trace sdv 16-bit shift register bkgd host system serial interface data control unsec register block register bdmsts instruction code and execution standard bdm firmware lookup table secured bdm firmware lookup table bus interface and control logic address data control clocks
background debug module (s12xbdmv2) mc9s12xhy-family reference manual, rev. 1.01 200 freescale semiconductor 5.3 memory map and register de?ition 5.3.1 module memory map table 5-2 shows the bdm memory map when bdm is active. 5.3.2 register descriptions a summary of the registers associated with the bdm is shown in figure 5-2 . registers are accessed by host-driven communications to the bdm hardware using read_bd and write_bd commands. table 5-2. bdm memory map global address module size (bytes) 0x7fff00?x7fff0b bdm registers 12 0x7fff0c?x7fff0e bdm ?mware rom 3 0x7fff0f family id (part of bdm ?mware rom) 1 0x7fff10?x7fffff bdm ?mware rom 240 global address register name bit 7 6 5 4 3 2 1 bit 0 0x7fff00 reserved r x x x x x x 0 0 w 0x7fff01 bdmsts r enbdm bdmact 0 sdv trace clksw unsec 0 w 0x7fff02 reserved r x x x x x x x x w 0x7fff03 reserved r x x x x x x x x w 0x7fff04 reserved r x x x x x x x x w 0x7fff05 reserved r x x x x x x x x w 0x7fff06 bdmccrl r ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 w = unimplemented, reserved = implemented (do not alter) x = indeterminate 0 = always read zero figure 5-2. bdm register summary
background debug module (s12xbdmv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 201 5.3.2.1 bdm status register (bdmsts) figure 5-3. bdm status register ( bdmsts) 0x7fff07 bdmccrh r 0 0 0 0 0 ccr10 ccr9 ccr8 w 0x7fff08 bdmgpr r bgae bgp6 bgp5 bgp4 bgp3 bgp2 bgp1 bgp0 w 0x7fff09 reserved r 0 0 0 0 0 0 0 0 w 0x7fff0a reserved r 0 0 0 0 0 0 0 0 w 0x7fff0b reserved r 0 0 0 0 0 0 0 0 w register global address 0x7fff01 7 6 54 3 2 1 0 r enbdm bdmact 0sdv trace clksw unsec 0 w reset special single-chip mode 0 1 1 enbdm is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but fully erased (non-volatile memory). this is because the enbdm bit is set by the standard ?mware before a bdm command can be fully transmitted and executed. 1 00 0 0 0 3 3 unsec is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased, else it is 0 and can only be read if not secure (see also bit description). 0 emulation modes (if modes available) 1 0 00 0 1 2 2 clksw is read as 1 by a debugging environment in emulation modes when the device is not secured and read as 0 when secured if emulation modes available. 0 0 all other modes 0 0 00 0 0 0 0 = unimplemented, reserved = implemented (do not alter) 0 = always read zero global address register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented, reserved = implemented (do not alter) x = indeterminate 0 = always read zero figure 5-2. bdm register summary (continued)
background debug module (s12xbdmv2) mc9s12xhy-family reference manual, rev. 1.01 202 freescale semiconductor read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured, but subject to the following: enbdm should only be set via a bdm hardware command if the bdm ?mware commands are needed. (this does not apply in special single chip and emulation modes). bdmact can only be set by bdm hardware upon entry into bdm. it can only be cleared by the standard bdm ?mware lookup table upon exit from bdm active mode. clksw can only be written via bdm hardware write_bd commands. all other bits, while writable via bdm hardware or standard bdm ?mware write commands, should only be altered by the bdm hardware or standard ?mware lookup table as part of bdm command execution. table 5-3. bdmsts field descriptions field description 7 enbdm enable bdm ?this bit controls whether the bdm is enabled or disabled. when enabled, bdm can be made active to allow ?mware commands to be executed. when disabled, bdm cannot be made active but bdm hardware commands are still allowed. 0 bdm disabled 1 bdm enabled note: enbdm is set by the ?mware out of reset in special single chip mode. in emulation modes (if modes available) the enbdm bit is set by bdm hardware out of reset. in special single chip mode with the device secured, this bit will not be set by the ?mware until after the non-volatile memory erase verify tests are complete. in emulation modes (if modes available) with the device secured, the bdm operations are blocked. 6 bdmact bdm active status ?this bit becomes set upon entering bdm. the standard bdm ?mware lookup table is then enabled and put into the memory map. bdmact is cleared by a carefully timed store instruction in the standard bdm ?mware as part of the exit sequence to return to user code and remove the bdm memory from the map. 0 bdm not active 1 bdm active 4 sdv shift data valid this bit is set and cleared by the bdm hardware. it is set after data has been transmitted as part of a ?mware or hardware read command or after data has been received as part of a ?mware or hardware write command. it is cleared when the next bdm command has been received or bdm is exited. sdv is used by the standard bdm ?mware to control program ?w execution. 0 data phase of command not complete 1 data phase of command is complete 3 trace trace1 bdm firmware command is being executed ?this bit gets set when a bdm trace1 ?mware command is ?st recognized. it will stay set until bdm ?mware is exited by one of the following bdm commands: go or go_until. 0 trace1 command is not being executed 1 trace1 command is being executed
background debug module (s12xbdmv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 203 2 clksw clock switch the clksw bit controls which clock the bdm operates with. it is only writable from a hardware bdm command. a minimum delay of 150 cycles at the clock speed that is active during the data portion of the command send to change the clock source should occur before the next command can be send. the delay should be obtained no matter which bit is modi?d to effectively change the clock source (either pllsel bit or clksw bit). this guarantees that the start of the next bdm command uses the new clock for timing subsequent bdm communications. table 5-4 shows the resulting bdm clock source based on the clksw and the pllsel (pll select in the crg module, the bit is part of the clksel register) bits. note: the bdm alternate clock source can only be selected when clksw = 0 and pllsel = 1. the bdm serial interface is now fully synchronized to the alternate clock source, when enabled. this eliminates frequency restriction on the alternate clock which was required on previous versions. refer to the device speci?ation to determine which clock connects to the alternate clock source input. note: if the acknowledge function is turned on, changing the clksw bit will cause the ack to be at the new rate for the write command which changes it. note: in emulation modes (if modes available), the clksw bit will be set out of reset. 1 unsec unsecure ?if the device is secured this bit is only writable in special single chip mode from the bdm secure ?mware. it is in a zero state as secure mode is entered so that the secure bdm ?mware lookup table is enabled and put into the memory map overlapping the standard bdm ?mware lookup table. the secure bdm ?mware lookup table veri?s that the non-volatile memories (e.g. on-chip eeprom and/or flash eeprom) are erased. this being the case, the unsec bit is set and the bdm program jumps to the start of the standard bdm ?mware lookup table and the secure bdm ?mware lookup table is turned off. if the erase test fails, the unsec bit will not be asserted. 0 system is in a secured mode. 1 system is in a unsecured mode. note: when unsec is set, security is off and the user can change the state of the secure bits in the on-chip flash eeprom. note that if the user does not change the state of the bits to ?nsecured?mode, the system will be secured again when it is next taken out of reset.after reset this bit has no meaning or effect when the security byte in the flash eeprom is con?ured for unsecure mode. table 5-4. bdm clock sources pllsel clksw bdmclk 0 0 bus clock dependent on oscillator 0 1 bus clock dependent on oscillator 1 0 alternate clock (refer to the device speci?ation to determine the alternate clock source) 1 1 bus clock dependent on the pll table 5-3. bdmsts field descriptions (continued) field description
background debug module (s12xbdmv2) mc9s12xhy-family reference manual, rev. 1.01 204 freescale semiconductor 5.3.2.2 bdm ccr low holding register (bdmccrl) figure 5-4. bdm ccr low holding register (bdmccrl) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured note when bdm is made active, the cpu stores the content of its ccr l register in the bdmccrl register. however, out of special single-chip reset, the bdmccrl is set to 0xd8 and not 0xd0 which is the reset value of the ccr l register in this cpu mode. out of reset in all other modes the bdmccrl register is read zero. when entering background debug mode, the bdm ccr low holding register is used to save the low byte of the condition code register of the users program. it is also used for temporary storage in the standard bdm ?mware mode. the bdm ccr low holding register can be written to modify the ccr value. 5.3.2.3 bdm ccr high holding register (bdmccrh) figure 5-5. bdm ccr high holding register (bdmccrh) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured when entering background debug mode, the bdm ccr high holding register is used to save the high byte of the condition code register of the users program. the bdm ccr high holding register can be written to modify the ccr value. register global address 0x7fff06 7 6 5 4 3 2 1 0 r ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 w reset special single-chip mode 1 1 0 0 1 0 0 0 all other modes 0 0 0 0 0 0 0 0 register global address 0x7fff07 7 6 5 4 3 2 1 0 r 0 0 0 0 0 ccr10 ccr9 ccr8 w reset 0 0 0 0 0 0 0 0 = unimplemented or reserved
background debug module (s12xbdmv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 205 5.3.2.4 bdm global page index register (bdmgpr) figure 5-6. bdm global page register (bdmgpr) read: all modes through bdm operation when not secured write: all modes through bdm operation when not secured 5.3.3 family id assignment the family id is a 8-bit value located in the ?mware rom (at global address: 0x7fff0f). the read-only value is a unique family id which is 0xc1 for s12x devices. 5.4 functional description the bdm receives and executes commands from a host via a single wire serial interface. there are two types of bdm commands: hardware and ?mware commands. hardware commands are used to read and write target system memory locations and to enter active background debug mode, see section 5.4.3, ?dm hardware commands . target system memory includes all memory that is accessible by the cpu. firmware commands are used to read and write cpu resources and to exit from active background debug mode, see section 5.4.4, ?tandard bdm firmware commands . the cpu resources referred to are the accumulator (d), x index register (x), y index register (y), stack pointer (sp), and program counter (pc). hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted (see section 5.4.3, ?dm hardware commands ) and in secure mode (see section 5.4.1, ?ecurity ). firmware commands can only be executed when the system is not secure and is in active background debug mode (bdm). register global address 0x7fff08 7 6 5 4 3 2 1 0 r bgae bgp6 bgp5 bgp4 bgp3 bgp2 bgp1 bgp0 w reset 0 0 0 0 0 0 0 0 table 5-5. bdmgpr field descriptions field description 7 bgae bdm global page access enable bit bgae enables global page access for bdm hardware and ?mware read/write instructions the bdm hardware commands used to access the bdm registers (read_bd_ and write_bd_) can not be used for global accesses even if the bgae bit is set. 0 bdm global access disabled 1 bdm global access enabled 6? bgp[6:0] bdm global page index bits 6? ?these bits de?e the extended address bits from 22 to 16. for more detailed information regarding the global page window scheme, please refer to the s12x_mmc block guide.
background debug module (s12xbdmv2) mc9s12xhy-family reference manual, rev. 1.01 206 freescale semiconductor 5.4.1 security if the user resets into special single chip mode with the system secured, a secured mode bdm ?mware lookup table is brought into the map overlapping a portion of the standard bdm ?mware lookup table. the secure bdm ?mware veri?s that the on-chip non-volatile memory (e.g. eeprom and flash eeprom) is erased. this being the case, the unsec and enbdm bit will get set. the bdm program jumps to the start of the standard bdm ?mware and the secured mode bdm ?mware is turned off and all bdm commands are allowed. if the non-volatile memory does not verify as erased, the bdm ?mware sets the enbdm bit, without asserting unsec, and the ?mware enters a loop. this causes the bdm hardware commands to become enabled, but does not enable the ?mware commands. this allows the bdm hardware to be used to erase the non-volatile memory. bdm operation is not possible in any other mode than special single chip mode when the device is secured. the device can be unsecured via bdm serial interface in special single chip mode only. for more information regarding security, please see the s12x_9sec block guide. 5.4.2 enabling and activating bdm the system must be in active bdm to execute standard bdm ?mware commands. bdm can be activated only after being enabled. bdm is enabled by setting the enbdm bit in the bdm status (bdmsts) register. the enbdm bit is set by writing to the bdm status (bdmsts) register, via the single-wire interface, using a hardware command such as write_bd_byte. after being enabled, bdm is activated by one of the following 3 : hardware background command cpu bgnd instruction external instruction tagging mechanism 4 breakpoint force or tag mechanism 4 when bdm is activated, the cpu ?ishes executing the current instruction and then begins executing the ?mware in the standard bdm ?mware lookup table. when bdm is activated by a breakpoint, the type of breakpoint used determines if bdm becomes active before or after execution of the next instruction. note if an attempt is made to activate bdm before being enabled, the cpu resumes normal instruction execution after a brief delay. if bdm is not enabled, any hardware background commands issued are ignored by the bdm and the cpu is not delayed. in active bdm, the bdm registers and standard bdm ?mware lookup table are mapped to addresses 0x7fff00 to 0x7fffff. bdm registers are mapped to addresses 0x7fff00 to 0x7fff0b. the bdm uses these registers which are readable anytime by the bdm. however, these registers are not readable by user programs. 3. bdm is enabled and active immediately out of special single-chip reset. 4. this method is provided by the s12x_dbg module.
background debug module (s12xbdmv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 207 5.4.3 bdm hardware commands hardware commands are used to read and write target system memory locations and to enter active background debug mode. target system memory includes all memory that is accessible by the cpu on the soc which can be on-chip ram, non-volatile memory (e.g. eeprom, flash eeprom), i/o and control registers, and all external memory. hardware commands are executed with minimal or no cpu intervention and do not require the system to be in active bdm for execution, although, they can still be executed in this mode. when executing a hardware command, the bdm sub-block waits for a free bus cycle so that the background access does not disturb the running application program. if a free cycle is not found within 128 clock cycles, the cpu is momentarily frozen so that the bdm can steal a cycle. when the bdm ?ds a free cycle, the operation does not intrude on normal cpu operation provided that it can be completed in a single cycle. however, if an operation requires multiple cycles the cpu is frozen until the operation is complete, even though the bdm found a free cycle. the bdm hardware commands are listed in table 5-6 . the read_bd and write_bd commands allow access to the bdm register locations. these locations are not normally in the system memory map but share addresses with the application in memory. to distinguish between physical memory locations that share the same address, bdm memory resources are enabled just for the read_bd and write_bd access cycle. this allows the bdm to access bdm locations unobtrusively, even if the addresses con?ct with the application memory map. table 5-6. hardware commands command opcode (hex) data description background 90 none enter background mode if ?mware is enabled. if enabled, an ack will be issued when the part enters active background mode. ack_enable d5 none enable handshake. issues an ack pulse after the command is executed. ack_disable d6 none disable handshake. this command does not issue an ack pulse. read_bd_byte e4 16-bit address 16-bit data out read from memory with standard bdm ?mware lookup table in map. odd address data on low byte; even address data on high byte. read_bd_word ec 16-bit address 16-bit data out read from memory with standard bdm ?mware lookup table in map. must be aligned access. read_byte e0 16-bit address 16-bit data out read from memory with standard bdm ?mware lookup table out of map. odd address data on low byte; even address data on high byte. read_word e8 16-bit address 16-bit data out read from memory with standard bdm ?mware lookup table out of map. must be aligned access. write_bd_byte c4 16-bit address 16-bit data in write to memory with standard bdm ?mware lookup table in map. odd address data on low byte; even address data on high byte. write_bd_word cc 16-bit address 16-bit data in write to memory with standard bdm ?mware lookup table in map. must be aligned access. write_byte c0 16-bit address 16-bit data in write to memory with standard bdm ?mware lookup table out of map. odd address data on low byte; even address data on high byte.
background debug module (s12xbdmv2) mc9s12xhy-family reference manual, rev. 1.01 208 freescale semiconductor 5.4.4 standard bdm firmware commands firmware commands are used to access and manipulate cpu resources. the system must be in active bdm to execute standard bdm ?mware commands, see section 5.4.2, ?nabling and activating bdm . normal instruction execution is suspended while the cpu executes the ?mware located in the standard bdm ?mware lookup table. the hardware command background is the usual way to activate bdm. as the system enters active bdm, the standard bdm ?mware lookup table and bdm registers become visible in the on-chip memory map at 0x7fff00?x7fffff, and the cpu begins executing the standard bdm ?mware. the standard bdm ?mware watches for serial commands and executes them as they are received. the ?mware commands are shown in table 5-7 . write_word c8 16-bit address 16-bit data in write to memory with standard bdm ?mware lookup table out of map. must be aligned access. note: if enabled, ack will occur when data is ready for transmission for all bdm read commands and will occur after the write is complete for all bdm write commands. table 5-6. hardware commands (continued) command opcode (hex) data description
background debug module (s12xbdmv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 209 5.4.5 bdm command structure hardware and ?mware bdm commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the command. all the read commands return 16 bits of data despite the byte or word implication in the command name. 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. if reading an even address, the valid data will appear in the msb. if reading an odd address, the valid data will appear in the lsb. table 5-7. firmware commands command 1 1 if enabled, ack will occur when data is ready for transmission for all bdm read commands and will occur after the write is complete for all bdm write commands. opcode (hex) data description read_next 2 2 when the ?mware command read_next or write_next is used to access the bdm address space the bdm resources are accessed rather than user code. writing bdm ?mware is not possible. 62 16-bit data out increment x index register by 2 (x = x + 2), then read word x points to. read_pc 63 16-bit data out read program counter. read_d 64 16-bit data out read d accumulator. read_x 65 16-bit data out read x index register. read_y 66 16-bit data out read y index register. read_sp 67 16-bit data out read stack pointer. write_next

42 16-bit data in increment x index register by 2 (x = x + 2), then write word to location pointed to by x. write_pc 43 16-bit data in write program counter. write_d 44 16-bit data in write d accumulator. write_x 45 16-bit data in write x index register. write_y 46 16-bit data in write y index register. write_sp 47 16-bit data in write stack pointer. go 08 none go to user program. if enabled, ack will occur when leaving active background mode. go_until 3 3 system stop disables the ack function and ignored commands will not have an ack-pulse (e.g., cpu in stop or wait mode). the go_until command will not get an acknowledge if cpu executes the wait or stop instruction before the ?ntil condition (bdm active again) is reached (see section 5.4.7, ?erial interface hardware handshake protocol last note). 0c none go to user program. if enabled, ack will occur upon returning to active background mode. trace1 10 none execute one user instruction then return to active bdm. if enabled, ack will occur upon returning to active background mode. taggo -> go 18 none (previous enable tagging and go to user program.) this command will be deprecated and should not be used anymore. opcode will be executed as a go command.
background debug module (s12xbdmv2) mc9s12xhy-family reference manual, rev. 1.01 210 freescale semiconductor 16-bit misaligned reads and writes are generally not allowed. if attempted by bdm hardware command, the bdm will ignore the least signi?ant bit of the address and will assume an even address from the remaining bits. for devices with external bus: the following cycle count information is only valid when the external wait function is not used (see wait bit of ebi sub-block). during an external wait the bdm can not steal a cycle. hence be careful with the external wait function if the bdm serial interface is much faster than the bus, because of the bdm soft-reset after time-out (see section 5.4.11, ?erial communication time out ). for hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting to obtain the read data. this is to be certain that valid data is available in the bdm shift register, ready to be shifted out. for hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before attempting to send a new command. this is to avoid disturbing the bdm shift register before the write has been completed. the 150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the bdm waits for a free cycle before stealing a cycle. for ?mware read commands, the external host should wait at least 48 bus clock cycles after sending the command opcode and before attempting to obtain the read data. this includes the potential of extra cycles when the access is external and stretched (+1 to maximum +7 cycles) or to registers of the pru (port replacement unit) in emulation modes (if modes available). the 48 cycle wait allows enough time for the requested data to be made available in the bdm shift register, ready to be shifted out. note this timing has increased from previous bdm modules due to the new capability in which the bdm serial interface can potentially run faster than the bus. on previous bdm modules this extra time could be hidden within the serial time. for ?mware write commands, the external host must wait 36 bus clock cycles after sending the data to be written before attempting to send a new command. this is to avoid disturbing the bdm shift register before the write has been completed. the external host should wait at least for 76 bus clock cycles after a trace1 or go command before starting any new serial command. this is to allow the cpu to exit gracefully from the standard bdm ?mware lookup table and resume execution of the user code. disturbing the bdm shift register prematurely may adversely affect the exit from the standard bdm ?mware lookup table. note if the bus rate of the target processor is unknown or could be changing or the external wait function is used, it is recommended that the ack (acknowledge function) is used to indicate when an operation is complete. when using ack, the delay times are automated.
background debug module (s12xbdmv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 211 figure 5-7 represents the bdm command structure. the command blocks illustrate a series of eight bit times starting with a falling edge. the bar across the top of the blocks indicates that the bkgd line idles in the high state. the time for an 8-bit command is 8 16 target clock cycles. 5 figure 5-7. bdm command structure 5.4.6 bdm serial interface the bdm communicates with external devices serially via the bkgd pin. during reset, this pin is a mode select input which selects between normal and special modes of operation. after reset, this pin becomes the dedicated serial interface pin for the bdm. the bdm serial interface is timed using the clock selected by the clksw bit in the status register see section 5.3.2.1, ?dm status register (bdmsts) . this clock will be referred to as the target clock in the following explanation. the bdm serial interface uses a clocking scheme in which the external host generates a falling edge on the bkgd pin to indicate the start of each bit time. this falling edge is sent for every bit whether data is transmitted or received. data is transferred most signi?ant bit (msb) ?st at 16 target clock cycles per bit. the interface times out if 512 clock cycles occur between falling edges from the host. the bkgd pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. it is assumed that there is an external pull-up and that drivers connected to bkgd do not typically drive the high level. since r-c rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive bkgd to a logic 1. the source of this speedup pulse is the host for transmit cases and the target for receive cases. 5. target clock cycles are cycles measured using the target mcus serial clock rate. see section 5.4.6, ?dm serial interface and section 5.3.2.1, ?dm status register (bdmsts) for information on how serial clock rate is selected. hardware hardware firmware firmware go, 48-bc bc = bus clock cycles command address 150-bc delay next delay 8 bits at ~ 16 tc/bit 16 bits at ~ 16 tc/bit 16 bits at ~ 16 tc/bit command address data next data read write read write trace command next command data 76-bc delay next command 150-bc delay 36-bc delay command command command command data next command tc = target clock cycles
background debug module (s12xbdmv2) mc9s12xhy-family reference manual, rev. 1.01 212 freescale semiconductor the timing for host-to-target is shown in figure 5-8 and that of target-to-host in figure 5-9 and figure 5-10 . all four cases begin when the host drives the bkgd pin low to generate a falling edge. since the host and target are operating from separate clocks, it can take the target system up to one full clock cycle to recognize this edge. the target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove bkgd low to start the bit up to one target clock cycle earlier. synchronization between the host and target is established in this manner at the start of every bit time. figure 5-8 shows an external host transmitting a logic 1 and transmitting a logic 0 to the bkgd pin of a target system. the host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. ten target clock cycles later, the target senses the bit level on the bkgd pin. internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission. since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals. figure 5-8. bdm host-to-target serial bit timing the receive cases are more complicated. figure 5-9 shows the host receiving a logic 1 from the target system. since the host is asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on bkgd to the perceived start of the bit time in the target. the host holds the bkgd pin low long enough for the target to recognize it (at least two target clock cycles). the host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. the host should sample the bit level about 10 target clock cycles after it started the bit time. target senses bit 10 cycles synchronization uncertainty bdm clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time earliest start of next bit
background debug module (s12xbdmv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 213 figure 5-9. bdm target-to-host serial bit timing (logic 1) high-impedance earliest start of next bit r-c rise 10 cycles 10 cycles host samples bkgd pin perceived start of bit time bkgd pin bdm clock (target mcu) host drive to bkgd pin target system speedup pulse high-impedance high-impedance
background debug module (s12xbdmv2) mc9s12xhy-family reference manual, rev. 1.01 214 freescale semiconductor figure 5-10 shows the host receiving a logic 0 from the target. since the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by the target. the host initiates the bit time but the target ?ishes it. since the target wants the host to receive a logic 0, it drives the bkgd pin low for 13 target clock cycles then brie? drives it high to speed up the rising edge. the host samples the bit level about 10 target clock cycles after starting the bit time. figure 5-10. bdm target-to-host serial bit timing (logic 0) 5.4.7 serial interface hardware handshake protocol bdm commands that require cpu execution are ultimately treated at the mcu bus rate. since the bdm clock source can be asynchronously related to the bus frequency, when clksw = 0, it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the cpu. the alternative is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. this sub-section will describe the hardware handshake protocol. the hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target. this protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the bkgd pin. this pulse is generated by the target mcu when a command, issued by the host, has been successfully executed (see figure 5-11 ). this pulse is referred to as the ack pulse. after the ack pulse has ?ished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command (background, go, go_until or trace1). the ack pulse is not issued earlier than 32 serial clock cycles after the bdm command was issued. the end of the bdm command is assumed to be the 16th tick of the last bit. this minimum delay assures enough time for the host to perceive the ack pulse. note also that, there is no upper limit for the delay between the command and the related ack pulse, since the command execution depends upon the cpu bus frequency, which in some cases could be very slow earliest start of next bit bdm clock (target mcu) host drive to bkgd pin bkgd pin perceived start of bit time 10 cycles 10 cycles host samples bkgd pin target system drive and speedup pulse speedup pulse high-impedance
background debug module (s12xbdmv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 215 compared to the serial communication rate. this protocol allows a great ?xibility for the pod designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication. figure 5-11. target acknowledge pulse (ack) note if the ack pulse was issued by the target, the host assumes the previous command was executed. if the cpu enters wait or stop prior to executing a hardware command, the ack pulse will not be issued meaning that the bdm command was not executed. after entering wait or stop mode, the bdm command is no longer pending. figure 5-12 shows the ack handshake protocol in a command level timing diagram. the read_byte instruction is used as an example. first, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. the target bdm decodes the instruction. a bus cycle is grabbed (free or stolen) by the bdm and it executes the read_byte operation. having retrieved the data, the bdm issues an ack pulse to the host controller, indicating that the addressed byte is ready to be retrieved. after detecting the ack pulse, the host initiates the byte retrieval process. note that data is sent in the form of a word and the host needs to determine which is the appropriate byte based on whether the address was odd or even. figure 5-12. handshake protocol at command level 16 cycles bdm clock (target mcu) target transmits ack pulse high-impedance bkgd pin minimum delay from the bdm command 32 cycles earliest start of next bit speedup pulse 16th tick of the last command bit high-impedance read_byte bdm issues the bkgd pin byte address bdm executes the read_byte command host target host target bdm decodes the command ack pulse (out of scale) host target (2) bytes are retrieved new bdm command
background debug module (s12xbdmv2) mc9s12xhy-family reference manual, rev. 1.01 216 freescale semiconductor differently from the normal bit transfer (where the host initiates the transmission), the serial interface ack handshake pulse is initiated by the target mcu by issuing a negative edge in the bkgd pin. the hardware handshake protocol in figure 5-11 speci?s the timing when the bkgd pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical con?ct in the bkgd pin. note the only place the bkgd pin can have an electrical con?ct is when one side is driving low and the other side is issuing a speedup pulse (high). other ?ighs are pulled rather than driven. however, at low rates the time of the speedup pulse can become lengthy and so the potential con?ct time becomes longer as well. the ack handshake protocol does not support nested ack pulses. if a bdm command is not acknowledge by an ack pulse, the host needs to abort the pending command ?st in order to be able to issue a new bdm command. when the cpu enters wait or stop while the host issues a hardware command (e.g., write_byte), the target discards the incoming command due to the wait or stop being detected. therefore, the command is not acknowledged by the target, which means that the ack pulse will not be issued in this case. after a certain time the host (not aware of stop or wait) should decide to abort any possible pending ack pulse in order to be sure a new command can be issued. therefore, the protocol provides a mechanism in which a command, and its corresponding ack, can be aborted. note the ack pulse does not provide a time out. this means for the go_until command that it can not be distinguished if a stop or wait has been executed (command discarded and ack not issued) or if the ?ntil?condition (bdm active) is just not reached yet. hence in any case where the ack pulse of a command is not issued the possible pending command should be aborted before issuing a new command. see the handshake abort procedure described in section 5.4.8, ?ardware handshake abort procedure . 5.4.8 hardware handshake abort procedure the abort procedure is based on the sync command. in order to abort a command, which had not issued the corresponding ack pulse, the host controller should generate a low pulse in the bkgd pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse. by detecting this long low pulse in the bkgd pin, the target executes the sync protocol, see section 5.4.9, ?ync ?request timed reference pulse , and assumes that the pending command and therefore the related ack pulse, are being aborted. therefore, after the sync protocol has been completed the host is free to issue new bdm commands. for firmware read or write commands it can not be guaranteed that the pending command is aborted when issuing a sync before the corresponding ack pulse. there is a short latency time from the time the read or write access begins until it is ?ished and the corresponding ack pulse is issued. the latency time depends on the ?mware read or write command that is issued and if the serial interface is running on a different clock rate than the bus. when the sync command starts during this latency time the read or write command will not be aborted, but the corresponding ack pulse will be aborted. a pending go, trace1 or
background debug module (s12xbdmv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 217 go_until command can not be aborted. only the corresponding ack pulse can be aborted by the sync command. although it is not recommended, the host could abort a pending bdm command by issuing a low pulse in the bkgd pin shorter than 128 serial clock cycles, which will not be interpreted as the sync command. the ack is actually aborted when a negative edge is perceived by the target in the bkgd pin. the short abort pulse should have at least 4 clock cycles keeping the bkgd pin low, in order to allow the negative edge to be detected by the target. in this case, the target will not execute the sync protocol but the pending command will be aborted along with the ack pulse. the potential problem with this abort procedure is when there is a con?ct between the ack pulse and the short abort pulse. in this case, the target may not perceive the abort pulse. the worst case is when the pending command is a read command (i.e., read_byte). if the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. in this case, host and target will run out of synchronism. however, if the command to be aborted is not a read command the short abort pulse could be used. after a command is aborted the target assumes the next negative edge, after the abort pulse, is the ?st bit of a new bdm command. note the details about the short abort pulse are being provided only as a reference for the reader to better understand the bdm internal behavior. it is not recommended that this procedure be used in a real application. since the host knows the target serial clock frequency, the sync command (used to abort a command) does not need to consider the lower possible target frequency. in this case, the host could issue a sync very close to the 128 serial clock cycles length. providing a small overhead on the pulse length in order to assure the sync pulse will not be misinterpreted by the target. see section 5.4.9, ?ync ?request timed reference pulse . figure 5-13 shows a sync command being issued after a read_byte, which aborts the read_byte command. note that, after the command is aborted a new command could be issued by the host computer. figure 5-13. ack abort procedure at the command level note figure 5-13 does not represent the signals in a true timing scale figure 5-14 shows a con?ct between the ack pulse and the sync request pulse. this con?ct could occur if a pod device is connected to the target bkgd pin and the target is already in debug active mode. read_byte read_status bkgd pin memory address new bdm command new bdm command host target host target host target sync response from the target (out of scale) bdm decode and starts to execute the read_byte command read_byte cmd is aborted by the sync request (out of scale)
background debug module (s12xbdmv2) mc9s12xhy-family reference manual, rev. 1.01 218 freescale semiconductor consider that the target cpu is executing a pending bdm command at the exact moment the pod is being connected to the bkgd pin. in this case, an ack pulse is issued along with the sync command. in this case, there is an electrical con?ct between the ack speedup pulse and the sync pulse. since this is not a probable situation, the protocol does not prevent this con?ct from happening. figure 5-14. ack pulse and sync request con?ct note this information is being provided so that the mcu integrator will be aware that such a con?ct could eventually occur. the hardware handshake protocol is enabled by the ack_enable and disabled by the ack_disable bdm commands. this provides backwards compatibility with the existing pod devices which are not able to execute the hardware handshake protocol. it also allows for new pod devices, that support the hardware handshake protocol, to freely communicate with the target device. if desired, without the need for waiting for the ack pulse. the commands are described as follows: ack_enable enables the hardware handshake protocol. the target will issue the ack pulse when a cpu command is executed by the cpu. the ack_enable command itself also has the ack pulse as a response. ack_disable disables the ack pulse protocol. in this case, the host needs to use the worst case delay time at the appropriate places in the protocol. the default state of the bdm after reset is hardware handshake protocol disabled. all the read commands will ack (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the bkgd serial pin. all the write commands will ack (if enabled) after the data has been received by the bdm through the bkgd serial pin and when the data bus cycle is complete. see section 5.4.3, ?dm hardware commands and section 5.4.4, ?tandard bdm firmware commands for more information on the bdm commands. bdm clock (target mcu) target mcu drives to bkgd pin bkgd pin 16 cycles speedup pulse high-impedance host drives sync to bkgd pin ack pulse host sync request pulse at least 128 cycles electrical con?ct host and target drive to bkgd pin
background debug module (s12xbdmv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 219 the ack_enable sends an ack pulse when the command has been completed. this feature could be used by the host to evaluate if the target supports the hardware handshake protocol. if an ack pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. if the target does not support the hardware handshake protocol the ack pulse is not issued. in this case, the ack_enable command is ignored by the target since it is not recognized as a valid command. the background command will issue an ack pulse when the cpu changes from normal to background mode. the ack pulse related to this command could be aborted using the sync command. the go command will issue an ack pulse when the cpu exits from background mode. the ack pulse related to this command could be aborted using the sync command. the go_until command is equivalent to a go command with exception that the ack pulse, in this case, is issued when the cpu enters into background mode. this command is an alternative to the go command and should be used when the host wants to trace if a breakpoint match occurs and causes the cpu to enter active background mode. note that the ack is issued whenever the cpu enters bdm, which could be caused by a breakpoint match or by a bgnd instruction being executed. the ack pulse related to this command could be aborted using the sync command. the trace1 command has the related ack pulse issued when the cpu enters background active mode after one instruction of the application program is executed. the ack pulse related to this command could be aborted using the sync command. 5.4.9 sync ?request timed reference pulse the sync command is unlike other bdm commands because the host does not necessarily know the correct communication speed to use for bdm communications until after it has analyzed the response to the sync command. to issue a sync command, the host should perform the following steps: 1. drive the bkgd pin low for at least 128 cycles at the lowest possible bdm serial communication frequency (the lowest serial communication frequency is determined by the crystal oscillator or the clock chosen by clksw.) 2. drive bkgd high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. remove all drive to the bkgd pin so it reverts to high impedance. 4. listen to the bkgd pin for the sync response pulse. upon detecting the sync request from the host, the target performs the following steps: 1. discards any incomplete command received or bit retrieved. 2. waits for bkgd to return to a logic one. 3. delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. drives bkgd low for 128 cycles at the current bdm serial communication frequency. 5. drives a one-cycle high speedup pulse to force a fast rise time on bkgd. 6. removes all drive to the bkgd pin so it reverts to high impedance. the host measures the low time of this 128 cycle sync response pulse and determines the correct speed for subsequent bdm communications. typically, the host can determine the correct communication speed
background debug module (s12xbdmv2) mc9s12xhy-family reference manual, rev. 1.01 220 freescale semiconductor within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. as soon as the sync request is detected by the target, any partially received command or bit retrieved is discarded. this is referred to as a soft-reset, equivalent to a time-out in the serial communication. after the sync response, the target will consider the next negative edge (issued by the host) as the start of a new bdm command or the start of new sync request. another use of the sync command pulse is to abort a pending ack pulse. the behavior is exactly the same as in a regular sync command. note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization problem. in this case, the command may not have been understood by the target and so an ack response pulse will not be issued. 5.4.10 instruction tracing when a trace1 command is issued to the bdm in active bdm, the cpu exits the standard bdm ?mware and executes a single instruction in the user code. once this has occurred, the cpu is forced to return to the standard bdm ?mware and the bdm is active and ready to receive a new command. if the trace1 command is issued again, the next user instruction will be executed. this facilitates stepping or tracing through the user code one instruction at a time. if an interrupt is pending when a trace1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. once back in standard bdm ?mware execution, the program counter points to the ?st instruction in the interrupt service routine. be aware when tracing through the user code that the execution of the user code is done step by step but all peripherals are free running. hence possible timing relations between cpu code execution and occurrence of events of other peripherals no longer exist. do not trace the cpu instruction bgnd used for soft breakpoints. tracing the bgnd instruction will result in a return address pointing to bdm ?mware address space. when tracing through user code which contains stop or wait instructions the following will happen when the stop or wait instruction is traced: the cpu enters stop or wait mode and the trace1 command can not be ?ished before leaving the low power mode. this is the case because bdm active mode can not be entered after cpu executed the stop instruction. however all bdm hardware commands except the background command are operational after tracing a stop or wait instruction and still being in stop or wait mode. if system stop mode is entered (all bus masters are in stop mode) no bdm command is operational. as soon as stop or wait mode is exited the cpu enters bdm active mode and the saved pc value points to the entry of the corresponding interrupt service routine. in case the handshake feature is enabled the corresponding ack pulse of the trace1 command will be discarded when tracing a stop or wait instruction. hence there is no ack pulse when bdm active mode is entered as part of the trace1 command after cpu exited from stop or wait mode. all valid commands sent during cpu being in stop or wait mode or after cpu exited from stop or wait mode will have an ack pulse. the handshake feature becomes disabled only when system
background debug module (s12xbdmv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 221 stop mode has been reached. hence after a system stop mode the handshake feature must be enabled again by sending the ack_enable command. 5.4.11 serial communication time out the host initiates a host-to-target serial transmission by generating a falling edge on the bkgd pin. if bkgd is kept low for more than 128 target clock cycles, the target understands that a sync command was issued. in this case, the target will keep waiting for a rising edge on bkgd in order to answer the sync request pulse. if the rising edge is not detected, the target will keep waiting forever without any time-out limit. consider now the case where the host returns bkgd to logic one before 128 cycles. this is interpreted as a valid bit transmission, and not as a sync request. the target will keep waiting for another falling edge marking the start of a new bit. if, however, a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting memory or the operating mode of the mcu. this is referred to as a soft-reset. if a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. the data is not available for retrieval after the time-out has occurred. this is the expected behavior if the handshake protocol is not enabled. however, consider the behavior where the bdm is running in a frequency much greater than the cpu frequency. in this case, the command could time out before the data is ready to be retrieved. in order to allow the data to be retrieved even with a large clock frequency mismatch (between bdm and cpu) when the hardware handshake protocol is enabled, the time out between a read command and the data retrieval is disabled. therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued read command. however, once the handshake pulse (ack pulse) is issued, the time-out feature is re-activated, meaning that the target will time out after 512 clock cycles. therefore, the host needs to retrieve the data within a 512 serial clock cycles time frame after the ack pulse had been issued. after that period, the read command is discarded and the data is no longer available for retrieval. any negative edge in the bkgd pin after the time-out period is considered to be a new command or a sync request. note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the serial communication is active. this means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarded. the next negative edge in the bkgd pin, after a soft-reset has occurred, is considered by the target as the start of a new bdm command, or the start of a sync request pulse.
background debug module (s12xbdmv2) mc9s12xhy-family reference manual, rev. 1.01 222 freescale semiconductor
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 223 chapter 6 s12x debug (s12xdbgv3) module table 6-1. revision history 6.1 introduction the s12xdbg module provides an on-chip trace buffer with ?xible triggering capability to allow non- intrusive debug of application software. the s12xdbg module is optimized for the s12x 16-bit architecture and allows debugging of cpu12x module operations. typically the s12xdbg module is used in conjunction with the s12xbdm module, whereby the user con?ures the s12xdbg module for a debugging session over the bdm interface. once con?ured the s12xdbg module is armed and the device leaves bdm mode returning control to the user program, which is then monitored by the s12xdbg module. alternatively the s12xdbg module can be con?ured over a serial interface using swi routines. 6.1.1 glossary revision number revision date sections affected description of changes v03.20 14 sep 2007 6.3.2.7/6-233 - clari?d reserved state sequencer encodings. v03.21 23 oct 2007 6.4.2.2/6-246 6.4.2.4/6-247 - added single databyte comparison limitation information - added statement about interrupt vector fetches whilst tagging. v03.22 12 nov 2007 6.4.5.2/6-251 6.4.5.5/6-255 - removed loop1 tracing restriction note. - added pin reset effect note. v03.23 13 nov 2007 general - text readability improved, typo removed. v03.24 04 jan 2008 6.4.5.3/6-253 - corrected bit name. v03.25 14 may 2008 - updated revision history table format. corrected other paragraph formats. table 6-2. glossary of terms term de?ition cof change of flow. change in the program ?w due to a conditional branch, indexed jump or interrupt bdm background debug mode dug device user guide, describing the features of the device into which the dbg is integrated word 16 bit data entity data line 64 bit data entity
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 224 freescale semiconductor 6.1.2 overview the comparators monitor the bus activity of the cpu12x. when a match occurs the control logic can trigger the state sequencer to a new state. on a transition to the final state, bus tracing is triggered and/or a breakpoint can be generated. independent of comparator matches a transition to final state with associated tracing and breakpoint can be triggered by writing to the trig control bit. the trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. tracing is disabled when the mcu system is secured. 6.1.3 features four comparators (a, b, c, and d) comparators a and c compare the full address bus and full 16-bit data bus comparators a and c feature a data bus mask register comparators b and d compare the full address bus only each comparator can be con?ured to monitor cpu12x buses each comparator features selection of read or write access cycles comparators b and d allow selection of byte or word access cycles comparisons can be used as triggers for the state sequencer three comparator modes simple address/data comparator match mode inside address range mode, addmin address addmax outside address range match mode, address < addmin or address > addmax two types of triggers tagged ?this triggers just before a speci? instruction begins execution force ?this triggers on the ?st instruction boundary after a match occurs. the following types of breakpoints cpu12x breakpoint entering bdm on breakpoint (bdm) cpu12x breakpoint executing swi on breakpoint (swi) trig immediate software trigger independent of comparators four trace modes normal: change of ?w (cof) pc information is stored (see section 6.4.5.2.1 ) for change of ?w de?ition. cpu cpu12x module tag tags can be attached to cpu opcodes as they enter the instruction pipe. if the tagged opcode reaches the execution stage a tag hit occurs. table 6-2. glossary of terms (continued) term de?ition
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 225 loop1: same as normal but inhibits consecutive duplicate source address entries detail: address and data for all cycles except free cycles and opcode fetches are stored pure pc: all program counter addresses are stored. 4-stage state sequencer for trace buffer control tracing session trigger linked to final state of state sequencer begin, end, and mid alignment of tracing to trigger 6.1.4 modes of operation the s12xdbg module can be used in all mcu functional modes. during bdm hardware accesses and whilst the bdm module is active, cpu12x monitoring is disabled. thus breakpoints, comparators, and cpu12x bus tracing are disabled . when the cpu12x enters active bdm mode through a background command, with the s12xdbg module armed, the s12xdbg remains armed. the s12xdbg module tracing is disabled if the mcu is secure. however, breakpoints can still be generated if the mcu is secure. table 6-3. mode dependent restriction summary bdm enable bdm active mcu secure comparator matches enabled breakpoints possible tagging possible tracing possible x x 1 yes yes yes no 0 0 0 yes only swi yes yes 0 1 0 active bdm not possible when not enabled 1 0 0 yes yes yes yes 110 no no no no
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 226 freescale semiconductor 6.1.5 block diagram figure 6-1. debug module block diagram 6.2 external signal description the s12xdbg sub-module features no external signals. 6.3 memory map and registers 6.3.1 module memory map a summary of the registers associated with the s12xdbg sub-block is shown in table 6-2 . detailed descriptions of the registers and bits are given in the subsections that follow. address name bit 7 6 5 4 3 2 1 bit 0 0x0020 dbgc1 r arm 0 reserved bdm dbgbrk reserved comrv w trig 0x0021 dbgsr r tbf 0 0 0 0 ssf2 ssf1 ssf0 w 0x0022 dbgtcr r reserved tsource trange trcmod talign w 0x0023 dbgc2 r0000 cdcm abcm w figure 6-2. quick reference to s12xdbg registers s12xcpu bus trace buffer bus interface trigger match0 state comparator b comparator c comparator d comparator a state sequencer match1 match2 match3 trace read trace data (dbg read data bus) control secure breakpoint requests comparator match control trigger tag & trigger control logic tag s taghits state s12xcpu
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 227 6.3.2 register descriptions this section consists of the s12xdbg control and trace buffer register descriptions in address order. each comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002f in the s12xdbg module register address map. when arm is set in dbgc1, the only bits in the s12xdbg module registers that can be written are arm, trig, and comrv[1:0] 0x0024 dbgtbh r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0025 dbgtbl r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0026 dbgcnt r 0 cnt w 0x0027 dbgscrx r0000 sc3 sc2 sc1 sc0 w 0x0027 dbgmfr r 0 0 0 0 mc3 mc2 mc1 mc0 w 0x0028 1 dbgxctl (compa/c) r0 ndb tag brk rw rwe reserved compe w 0x0028 2 dbgxctl (compb/d) r sze sz tag brk rw rwe reserved compe w 0x0029 dbgxah r0 bit 22 21 20 19 18 17 bit 16 w 0x002a dbgxam r bit 15 14 13 12 11 10 9 bit 8 w 0x002b dbgxal r bit 7 6 5 4 3 2 1 bit 0 w 0x002c dbgxdh r bit 15 14 13 12 11 10 9 bit 8 w 0x002d dbgxdl r bit 7 6 5 4 3 2 1 bit 0 w 0x002e dbgxdhm r bit 15 14 13 12 11 10 9 bit 8 w 0x002f dbgxdlm r bit 7 6 5 4 3 2 1 bit 0 w 1 this represents the contents if the comparator a or c control register is blended into this address. 2 this represents the contents if the comparator b or d control register is blended into this address address name bit 7 6 5 4 3 2 1 bit 0 figure 6-2. quick reference to s12xdbg registers
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 228 freescale semiconductor 6.3.2.1 debug control register 1 (dbgc1) read: anytime write: bits 7, 1, 0 anytime bit 6 can be written anytime but always reads back as 0. bits 5:2 anytime s12xdbg is not armed. note if a write access to dbgc1 with the arm bit position set occurs simultaneously to a hardware disarm from an internal trigger event, then the arm bit is cleared due to the hardware disarm. note when disarming the s12xdbg by clearing arm with software, the contents of bits[5:2] are not affected by the write, since up until the write operation, arm = 1 preventing these bits from being written. these bits must be cleared using a second write if required. address: 0x0020 76543210 r arm 0 reserved bdm dbgbrk reserved comrv w trig reset 00000000 figure 6-3. debug control register (dbgc1) table 6-4. dbgc1 field descriptions field description 7 arm arm bit ?the arm bit controls whether the s12xdbg module is armed. this bit can be set and cleared by user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with tracing not enabled. on setting this bit the state sequencer enters state1. 0 debugger disarmed 1 debugger armed 6 trig immediate trigger request bit ?this bit when written to 1 requests an immediate trigger independent of comparator signal status. when tracing is complete a forced breakpoint may be generated depending upon dbgbrk and bdm bit settings. this bit always reads back a 0. writing a 0 to this bit has no effect. if tsource is clear no tracing is carried out. if tracing has already commenced using begin- or mid trigger alignment, it continues until the end of the tracing session as de?ed by the talign bit settings, thus trig has no affect. in secure mode tracing is disabled and writing to this bit has no effect. 0 do not trigger until the state sequencer enters the final state. 1 trigger immediately . 5 reserved this bit is reserved, setting it has no meaning or effect. 4 bdm background debug mode enable ?this bit determines if an s12x breakpoint causes the system to enter background debug mode (bdm) or initiate a software interrupt (swi). if this bit is set but the bdm is not enabled by the enbdm bit in the bdm module, then breakpoints default to swi. 0 breakpoint to software interrupt if bdm inactive. otherwise no breakpoint. 1 breakpoint to bdm, if bdm enabled. otherwise breakpoint to swi
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 229 6.3.2.2 debug status register (dbgsr) read: anytime write: never 3 dbgbrk s12xdbg breakpoint enable bit the dbgbrk bit controls whether the debugger will request a breakpoint to s12xcpu upon reaching the state sequencer final state. if tracing is enabled, the breakpoint is generated on completion of the tracing session. if tracing is not enabled, the breakpoint is generated immediately. please refer to section 6.4.7 for further details. 0 no breakpoint on trigger. 1 breakpoint on trigger 1? comrv comparator register visibility bits these bits determine which bank of comparator register is visible in the 8-byte window of the s12xdbg module address map, located between 0x0028 to 0x002f. furthermore these bits determine which register is visible at the address 0x0027. see table 6-5 . table 6-5. comrv encoding comrv visible comparator visible register at 0x0027 00 comparator a dbgscr1 01 comparator b dbgscr2 10 comparator c dbgscr3 11 comparator d dbgmfr address: 0x0021 76543210 r tbf 0 0 0 0 ssf2 ssf1 ssf0 w reset por 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 6-4. debug status register (dbgsr) table 6-6. dbgsr field descriptions field description 7 tbf trace buffer full the tbf bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. if this bit is set, then all 64 lines will be valid data, regardless of the value of dbgcnt bits cnt[6:0]. the tbf bit is cleared when arm in dbgc1 is written to a one. the tbf is cleared by the power on reset initialization. other system generated resets have no affect on this bit 2? ssf[2:0] state sequencer flag bits the ssf bits indicate in which state the state sequencer is currently in. during a debug session on each transition to a new state these bits are updated. if the debug session is ended by software clearing the arm bit, then these bits retain their value to re?ct the last state of the state sequencer before disarming. if a debug session is ended by an internal trigger, then the state sequencer returns to state0 and these bits are cleared to indicate that state0 was entered during the session. on arming the module the state sequencer enters state1 and these bits are forced to ssf[2:0] = 001. see table 6-7 . table 6-4. dbgc1 field descriptions (continued) field description
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 230 freescale semiconductor 6.3.2.3 debug trace control register (dbgtcr) read: anytime write: bits 7:6 only when s12xdbg is neither secure nor armed. bits 5:0 anytime the module is disarmed. warning dbgtcr[7] is reserved. setting this bit maps the tracing to an unimplemented bus, thus preventing proper operation. table 6-7. ssf[2:0] ?state sequence flag bit encoding ssf[2:0] current state 000 state0 (disarmed) 001 state1 010 state2 011 state3 100 final state 101,110,111 reserved address: 0x0022 76543210 r reserved tsource trange trcmod talign w reset 00000000 figure 6-5. debug trace control register (dbgtcr) table 6-8. dbgtcr field descriptions field description 6 tsource trace source control bits the tsource enables the tracing session. if the mcu system is secured, this bit cannot be set and tracing is inhibited. 0 no tracing selected 1 tracing selected 5? trange trace range bits the trange bits allow ?tering of trace information from a selected address range when tracing from the cpu12x in detail mode. to use a comparator for range ?tering, the corresponding compe bits must remain cleared. if the compe bit is not clear then the comparator will also be used to generate state sequence triggers. see table 6-9 . 3? trcmod trace mode bits see section 6.4.5.2 for detailed trace mode descriptions. in normal mode, change of ?w information is stored. in loop1 mode, change of ?w information is stored but redundant entries into trace memory are inhibited. in detail mode, address and data for all memory and register accesses is stored. see table 6-10 . 1? talign trigger align bits ?these bits control whether the trigger is aligned to the beginning, end or the middle of a tracing session. see table 6-11 .
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 231 6.3.2.4 debug control register2 (dbgc2) read: anytime write: anytime the module is disarmed. this register con?ures the comparators for range matching. table 6-9. trange trace range encoding trange tracing range 00 trace from all addresses (no ?ter) 01 trace only in address range from $00000 to comparator d 10 trace only in address range from comparator c to $7fffff 11 trace only in range from comparator c to comparator d table 6-10. trcmod trace mode bit encoding trcmod description 00 normal 01 loop1 10 detail 11 pure pc table 6-11. talign trace alignment encoding talign description 00 trigger at end of stored data 01 trigger before storing data 10 trace buffer entries before and after trigger 11 reserved address: 0x0023 76543210 r0000 cdcm abcm w reset 00000000 = unimplemented or reserved figure 6-6. debug control register2 (dbgc2) table 6-12. dbgc2 field descriptions field description 3? cdcm[1:0] c and d comparator match control ?these bits determine the c and d comparator match mapping as described in table 6-13 . 1? abcm[1:0] a and b comparator match control ?these bits determine the a and b comparator match mapping as described in table 6-14 .
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 232 freescale semiconductor 6.3.2.5 debug trace buffer register (dbgtbh:dbgtbl) read: only when unlocked and not secured and not armed and with the tsource bit set. write: aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents. table 6-13. cdcm encoding cdcm description 00 match2 mapped to comparator c match....... match3 mapped to comparator d match. 01 match2 mapped to comparator c/d inside range....... match3 disabled. 10 match2 mapped to comparator c/d outside range....... match3 disabled. 11 reserved (1) 1. currently defaults to match2 mapped to comparator c : match3 mapped to comparator d table 6-14. abcm encoding abcm description 00 match0 mapped to comparator a match....... match1 mapped to comparator b match. 01 match 0 mapped to comparator a/b inside range....... match1 disabled. 10 match 0 mapped to comparator a/b outside range....... match1 disabled. 11 reserved (1) 1. currently defaults to match0 mapped to comparator a : match1 mapped to comparator b address: 0x0024, 0x0025 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w porxxxxxxxxxxxxxxxx other resets figure 6-7. debug trace buffer register (dbgtb) table 6-15. dbgtb field descriptions field description 15? bit[15:0] trace buffer data bits the trace buffer register is a window through which the 64-bit wide data lines of the trace buffer may be read 16 bits at a time. each valid read of dbgtb increments an internal trace buffer pointer which points to the next address to be read. when the arm bit is written to 1 the trace buffer is locked to prevent reading. the trace buffer can only be unlocked for reading by writing to dbgtb with an aligned word write when the module is disarmed. the dbgtb register can be read only as an aligned word, any byte reads or misaligned access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace buffer address. the same is true for word reads while the debugger is armed. the por state is unde?ed other resets do not affect the trace buffer contents. .
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 233 6.3.2.6 debug count register (dbgcnt) read: anytime write: never 6.3.2.7 debug state control registers there is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and de?es the address: 0x0026 76543210 r 0 cnt w reset por 0 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 6-8. debug count register (dbgcnt) table 6-16. dbgcnt field descriptions field description 6? cnt[6:0] count value the cnt bits [6:0] indicate the number of valid data 64-bit data lines stored in the trace buffer. table 6-17 shows the correlation between the cnt bits and the number of valid data lines in the trace buffer. when the cnt rolls over to zero, the tbf bit in dbgsr is set and incrementing of cnt will continue in end- trigger or mid-trigger mode. the dbgcnt register is cleared when arm in dbgc1 is written to a one. the dbgcnt register is cleared by power-on-reset initialization but is not cleared by other system resets. thus should a reset occur during a debug session, the dbgcnt register still indicates after the reset, the number of valid trace buffer entries stored before the reset occurred. the dbgcnt register is not decremented when reading from the trace buffer. table 6-17. cnt decoding table tbf (dbgsr) cnt[6:0] description 0 0000000 no data valid 0 0000001 32 bits of one line valid 0 0000010 0000100 0000110 .. 1111100 1 line valid 2 lines valid 3 lines valid .. 62 lines valid 0 1111110 63 lines valid 1 0000000 64 lines valid; if using begin trigger alignment, arm bit will be cleared and the tracing session ends. 1 0000010 .. .. 1111110 64 lines valid, oldest data has been overwritten by most recent data
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 234 freescale semiconductor next state for the state sequencer following a match. the three debug state control registers are located at the same address in the register address map (0x0027). each register can be accessed using the comrv bits in dbgc1 to blend in the required register. the comrv = 11 value blends in the match ?g register (dbgmfr). 6.3.2.7.1 debug state control register 1 (dbgscr1) read: if comrv[1:0] = 00 write: if comrv[1:0] = 00 and s12xdbg is not armed. this register is visible at 0x0027 only with comrv[1:0] = 00. the state control register 1 selects the targeted next state whilst in state1. the matches refer to the match channels of the comparator match control logic as depicted in figure 6-1 and described in section 6.3.2.8.1 . comparators must be enabled by setting the comparator enable bit in the associated dbgxctl control register. table 6-18. state control register access encoding comrv visible state control register 00 dbgscr1 01 dbgscr2 10 dbgscr3 11 dbgmfr address: 0x0027 76543210 r0000 sc3 sc2 sc1 sc0 w reset 00000000 = unimplemented or reserved figure 6-9. debug state control register 1 (dbgscr1) table 6-19. dbgscr1 field descriptions field description 3? sc[3:0] these bits select the targeted next state whilst in state1, based upon the match event. table 6-20. state1 sequencer next state selection sc[3:0] description 0000 any match triggers to state2 0001 any match triggers to state3 0010 any match triggers to final state 0011 match2 triggers to state2....... other matches have no effect 0100 match2 triggers to state3....... other matches have no effect 0101 match2 triggers to final state....... other matches have no effect 0110 match0 triggers to state2....... match1 triggers to state3....... other matches have no effect
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 235 the trigger priorities described in table 6-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. the sc[3:0] encoding ensures that a match leading to ?al state has priority over all other matches. 6.3.2.7.2 debug state control register 2 (dbgscr2) read: if comrv[1:0] = 01 write: if comrv[1:0] = 01 and s12xdbg is not armed. this register is visible at 0x0027 only with comrv[1:0] = 01. the state control register 2 selects the targeted next state whilst in state2. the matches refer to the match channels of the comparator match control logic as depicted in figure 6-1 and described in section 6.3.2.8.1 . comparators must be enabled by setting the comparator enable bit in the associated dbgxctl control register. 0111 match1 triggers to state3....... match0 triggers final state....... other matches have no effect 1000 match0 triggers to state2....... match2 triggers to state3....... other matches have no effect 1001 match2 triggers to state3....... match0 triggers final state....... other matches have no effect 1010 match1 triggers to state2....... match3 triggers to state3....... other matches have no effect 1011 match3 triggers to state3....... match1 triggers to final state....... other matches have no effect 1100 match3 has no effect....... all other matches (m0,m1,m2) trigger to state2 1101 reserved. (no match triggers state sequencer transition) 1110 reserved. (no match triggers state sequencer transition) 1111 reserved. (no match triggers state sequencer transition) address: 0x0027 76543210 r0000 sc3 sc2 sc1 sc0 w reset 00000000 = unimplemented or reserved figure 6-10. debug state control register 2 (dbgscr2) table 6-21. dbgscr2 field descriptions field description 3? sc[3:0] these bits select the targeted next state whilst in state2, based upon the match event. table 6-22. state2 ?equencer next state selection sc[3:0] description 0000 any match triggers to state1 0001 any match triggers to state3 0010 any match triggers to final state 0011 match3 triggers to state1....... other matches have no effect 0100 match3 triggers to state3....... other matches have no effect table 6-20. state1 sequencer next state selection (continued) sc[3:0] description
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 236 freescale semiconductor the trigger priorities described in table 6-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. the sc[3:0] encoding ensures that a match leading to ?al state has priority over all other matches. 6.3.2.7.3 debug state control register 3 (dbgscr3) read: if comrv[1:0] = 10 write: if comrv[1:0] = 10 and s12xdbg is not armed. this register is visible at 0x0027 only with comrv[1:0] = 10. the state control register three selects the targeted next state whilst in state3. the matches refer to the match channels of the comparator match control logic as depicted in figure 6-1 and described in section 6.3.2.8.1 . comparators must be enabled by setting the comparator enable bit in the associated dbgxctl control register. 0101 match3 triggers to final state....... other matches have no effect 0110 match0 triggers to state1....... match1 triggers to state3....... other matches have no effect 0111 match1 triggers to state3....... match0 triggers final state....... other matches have no effect 1000 match0 triggers to state1....... match2 triggers to state3....... other matches have no effect 1001 match2 triggers to state3....... match0 triggers final state....... other matches have no effect 1010 match1 triggers to state1....... match3 triggers to state3....... other matches have no effect 1011 match3 triggers to state3....... match1 triggers final state....... other matches have no effect 1100 match2 triggers to state1..... match3 trigger to final state 1101 match2 has no affect, all other matches (m0,m1,m3) trigger to final state 1110 reserved. (no match triggers state sequencer transition) 1111 reserved. (no match triggers state sequencer transition) address: 0x0027 76543210 r0000 sc3 sc2 sc1 sc0 w reset 00000000 = unimplemented or reserved figure 6-11. debug state control register 3 (dbgscr3) table 6-23. dbgscr3 field descriptions field description 3? sc[3:0] these bits select the targeted next state whilst in state3, based upon the match event. table 6-24. state3 ?sequencer next state selection sc[3:0] description 0000 any match triggers to state1 0001 any match triggers to state2 table 6-22. state2 ?equencer next state selection (continued) sc[3:0] description
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 237 the trigger priorities described in table 6-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. the sc[3:0] encoding ensures that a match leading to final state has priority over all other matches. 6.3.2.7.4 debug match flag register (dbgmfr) read: if comrv[1:0] = 11 write: never dbgmfr is visible at 0x0027 only with comrv[1:0] = 11. it features four ?g bits each mapped directly to a channel. should a match occur on the channel during the debug session, then the corresponding ?g is set and remains set until the next time the module is armed by writing to the arm bit. thus the contents are retained after a debug session for evaluation purposes. these ?gs cannot be cleared by software, they are cleared only when arming the module. a set ?g does not inhibit the setting of other ?gs. once a ?g is set, further triggers on the same channel have no affect. 6.3.2.8 comparator register descriptions each comparator has a bank of registers that are visible through an 8-byte window in the s12xdbg module register address map. comparators a and c consist of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers and a control register). 0010 any match triggers to final state 0011 match0 triggers to state1....... other matches have no effect 0100 match0 triggers to state2....... other matches have no effect 0101 match0 triggers to final state.......match1 triggers to state1...other matches have no effect 0110 match1 triggers to state1....... other matches have no effect 0111 match1 triggers to state2....... other matches have no effect 1000 match1 triggers to final state....... other matches have no effect 1001 match2 triggers to state2....... match0 triggers to final state....... other matches have no effect 1010 match1 triggers to state1....... match3 triggers to state2....... other matches have no effect 1011 match3 triggers to state2....... match1 triggers to final state....... other matches have no effect 1100 match2 triggers to final state....... other matches have no effect 1101 match3 triggers to final state....... other matches have no effect 1110 reserved. (no match triggers state sequencer transition) 1111 reserved. (no match triggers state sequencer transition) address: 0x0027 76543210 r0000mc3mc2mc1mc0 w reset 00000000 = unimplemented or reserved figure 6-12. debug match flag register (dbgmfr) table 6-24. state3 ?sequencer next state selection sc[3:0] description
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 238 freescale semiconductor comparators b and d consist of four register bytes (three address bus compare registers and a control register). each set of comparator registers is accessible in the same 8-byte window of the register address map and can be accessed using the comrv bits in the dbgc1 register. if the comparators b or d are accessed through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with data bus and data bus masking read as zero and cannot be written. furthermore the control registers for comparators b and d differ from those of comparators a and c. 6.3.2.8.1 debug comparator control register (dbgxctl) the contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the dbg module register address map. read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. warning dbgxctl[1] is reserved. setting this bit maps the corresponding comparator to an table 6-25. comparator register layout 0x0028 control read/write comparators a,b,c,d 0x0029 address high read/write comparators a,b,c,d 0x002a address medium read/write comparators a,b,c,d 0x002b address low read/write comparators a,b,c,d 0x002c data high comparator read/write comparator a and c only 0x002d data low comparator read/write comparator a and c only 0x002e data high mask read/write comparator a and c only 0x002f data low mask read/write comparator a and c only address: 0x0028 76543210 r0 ndb tag brk rw rwe reserved compe w reset 00000000 = unimplemented or reserved figure 6-13. debug comparator control register (comparators a and c) address: 0x0028 76543210 r sze sz tag brk rw rwe reserved compe w reset 00000000 figure 6-14. debug comparator control register (comparators b and d)
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 239 unimplemented bus, thus preventing proper operation. the dbgc1_comrv bits determine which comparator control, address, data and datamask registers are visible in the 8-byte window from 0x0028 to 0x002f as shown in section table 6-26. table 6-26. comparator address register visibility comrv visible comparator 00 dbgactl, dbgaah ,dbgaam, dbgaal, dbgadh, dbgadl, dbgadhm, dbgadlm 01 dbgbctl, dbgbah, dbgbam, dbgbal 10 dbgcctl, dbgcah, dbgcam, dbgcal, dbgcdh, dbgcdl, dbgcdhm, dbgcdlm 11 dbgdctl, dbgdah, dbgdam, dbgdal table 6-27. dbgxctl field descriptions field description 7 sze (comparators b and d) size comparator enable bit ?the sze bit controls whether access size comparison is enabled for the associated comparator. this bit is ignored if the tag bit in the same register is set. 0 word/byte access size is not used in comparison 1 word/byte access size is used in comparison 6 ndb (comparators a and c not data bus the ndb bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. furthermore data bus bits can be individually masked using the comparator data mask registers. this bit is only available for comparators a and c. this bit is ignored if the tag bit in the same register is set. this bit position has an sz functionality for comparators b and d. 0 match on data bus equivalence to comparator register contents 1 match on data bus difference to comparator register contents 6 sz (comparators b and d) size comparator value bit ?the sz bit selects either word or byte access size in comparison for the associated comparator. this bit is ignored if the sze bit is cleared or if the tag bit in the same register is set. this bit position has ndb functionality for comparators a and c 0 word access size will be compared 1 byte access size will be compared 5 tag tag select ?this bit controls whether the comparator match will cause a trigger or tag the opcode at the matched address. tagged opcodes trigger only if they reach the execution stage of the instruction queue. 0 trigger immediately on match 1 on match, tag the opcode. if the opcode is about to be executed a trigger is generated 4 brk break ?this bit controls whether a channel match terminates a debug session immediately, independent of state sequencer state. to generate an immediate breakpoint the module breakpoints must be enabled using dbgbrk. 0 the debug session termination is dependent upon the state sequencer and trigger conditions. 1 a match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing, if active, is terminated and the module disarmed. 3 rw read/write comparator value bit the rw bit controls whether read or write is used in compare for the associated comparator . the rw bit is not used if rwe = 0. 0 write cycle will be matched 1 read cycle will be matched 2 rwe read/write enable bit ?the rwe bit controls whether read or write comparison is enabled for the associated comparator. this bit is not used for tagged operations. 0 read/write is not used in comparison 1 read/write is used in comparison
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 240 freescale semiconductor table 6-28 shows the effect for rwe and rw on the comparison conditions. these bits are not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the instruction queue. thus these bits are ignored if tagged triggering is selected. 6.3.2.8.2 debug comparator address high register (dbgxah) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. 0 compe determines if comparator is enabled 0 the comparator is not enabled 1 the comparator is enabled for state sequence triggers or tag generation table 6-28. read or write comparison logic table rwe bit rw bit rw signal comment 0 x 0 rw not used in comparison 0 x 1 rw not used in comparison 1 0 0 write 1 0 1 no match 1 1 0 no match 1 1 1 read address: 0x0029 76543210 r0 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 w reset 00000000 = unimplemented or reserved figure 6-15. debug comparator address high register (dbgxah) table 6-29. dbgxah field descriptions field description 6? bit[22:16] comparator address high compare bits the comparator address high compare bits control whether the selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. . 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one table 6-27. dbgxctl field descriptions (continued) field description
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 241 6.3.2.8.3 debug comparator address mid register (dbgxam) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. 6.3.2.8.4 debug comparator address low register (dbgxal) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. address: 0x002a 76543210 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 00000000 figure 6-16. debug comparator address mid register (dbgxam) table 6-30. dbgxam field descriptions field description 7? bit[15:8] comparator address mid compare bits ?the comparator address mid compare bits control whether the selected comparator will compare the address bus bits [15:8] to a logic one or logic zero. 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one address: 0x002b 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 00000000 figure 6-17. debug comparator address low register (dbgxal) table 6-31. dbgxal field descriptions field description 7? bits[7:0] comparator address low compare bits ?the comparator address low compare bits control whether the selected comparator will compare the address bus bits [7:0] to a logic one or logic zero. 0 compare corresponding address bit to a logic zero 1 compare corresponding address bit to a logic one
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 242 freescale semiconductor 6.3.2.8.5 debug comparator data high register (dbgxdh) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. 6.3.2.8.6 debug comparator data low register (dbgxdl) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. address: 0x002c 76543210 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 00000000 figure 6-18. debug comparator data high register (dbgxdh) table 6-32. dbgxah field descriptions field description 7? bits[15:8] comparator data high compare bits the comparator data high compare bits control whether the selected comparator compares the data bus bits [15:8] to a logic one or logic zero. the comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. this register is available only for comparators a and c. 0 compare corresponding data bit to a logic zero 1 compare corresponding data bit to a logic one address: 0x002d 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 00000000 figure 6-19. debug comparator data low register (dbgxdl) table 6-33. dbgxdl field descriptions field description 7? bits[7:0] comparator data low compare bits the comparator data low compare bits control whether the selected comparator compares the data bus bits [7:0] to a logic one or logic zero. the comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. this register is available only for comparators a and c. 0 compare corresponding data bit to a logic zero 1 compare corresponding data bit to a logic one
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 243 6.3.2.8.7 debug comparator data high mask register (dbgxdhm) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. 6.3.2.8.8 debug comparator data low mask register (dbgxdlm) read: anytime. see table 6-26 for visible register encoding. write: if dbg not armed. see table 6-26 for visible register encoding. 6.4 functional description this section provides a complete functional description of the s12xdbg module. if the part is in secure mode, the s12xdbg module can generate breakpoints but tracing is not possible. address: 0x002e 76543210 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 00000000 figure 6-20. debug comparator data high mask register (dbgxdhm) table 6-34. dbgxdhm field descriptions field description 7? bits[15:8] comparator data high mask bits ?the comparator data high mask bits control whether the selected comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. this register is available only for comparators a and c. 0 do not compare corresponding data bit 1 compare corresponding data bit address: 0x002f 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 00000000 figure 6-21. debug comparator data low mask register (dbgxdlm) table 6-35. dbgxdlm field descriptions field description 7? bits[7:0] comparator data low mask bits ?the comparator data low mask bits control whether the selected comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. this register is available only for comparators a and c. 0 do not compare corresponding data bit 1 compare corresponding data bit
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 244 freescale semiconductor 6.4.1 s12xdbg operation arming the s12xdbg module by setting arm in dbgc1 allows triggering, and storing of data in the trace buffer and can be used to cause breakpoints to the cpu12x . the dbg module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. the comparators monitor the bus activity of the cpu12x . comparators can be con?ured to monitor address and databus. comparators can also be con?ured to mask out individual data bus bits during a compare and to use r/w and word/byte access quali?ation in the comparison. when a match with a comparator register value occurs the associated control logic can trigger the state sequencer to another state (see figure 6-22 ). either forced or tagged triggers are possible. using a forced trigger, the trigger is generated immediately on a comparator match. using a tagged trigger, at a comparator match, the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction queue is a trigger generated. in the case of a transition to final state, bus tracing is triggered and/or a breakpoint can be generated. independent of the state sequencer, a breakpoint can be triggered by writing to the trig bit in the dbgc1 control register. the trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. 6.4.2 comparator modes the s12xdbg contains four comparators, a, b, c, and d. each comparator compares the selected address bus with the address stored in dbgxah, dbgxam, and dbgxal. furthermore, comparators a and c also compare the data buses to the data stored in dbgxdh, dbgxdl and allow masking of individual data bus bits. s12x comparator matches are disabled in bdm and during bdm accesses. the comparator match control logic con?ures comparators to monitor the buses for an exact address or an address range. the comparator con?uration is controlled by the control register contents and the range control by the dbgc2 contents. on a match a trigger can initiate a transition to another state sequencer state (see section 6.4.3 ). the comparator control register also allows the type of access to be included in the comparison through the use of the rwe, rw, sze, and sz bits. the rwe bit controls whether read or write comparison is enabled for the associated comparator and the rw bit selects either a read or write access for a valid match. similarly the sze and sz bits allows the size of access (word or byte) to be considered in the compare. only comparators b and d feature sze and sz. the tag bit in each comparator control register is used to determine the triggering condition. by setting tag, the comparator will qualify a match with the output of opcode tracking logic and a trigger occurs before the tagged instruction executes (tagged-type trigger). whilst tagging, the rw, rwe, sze, and sz bits are ignored and the comparator register must be loaded with the exact opcode address. if the tag bit is clear (forced type trigger) a comparator match is generated when the selected address appears on the system address bus. if the selected address is an opcode address, the match is generated
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 245 when the opcode is fetched from the memory. this precedes the instruction execution by an inde?ite number of cycles due to instruction pipe lining. for a comparator match of an opcode at an odd address when tag = 0, the corresponding even address must be contained in the comparator register. thus for an opcode at odd address (n), the comparator register must contain address (n?). once a successful comparator match has occurred, the condition that caused the original match is not veri?d again on subsequent matches. thus if a particular data value is veri?d at a given address, this address may not still contain that data value when a subsequent match occurs. comparators c and d can also be used to select an address range to trace from. this is determined by the trange bits in the dbgtcr register. the trange encoding is shown in table 6-9 . if the trange bits select a range de?ition using comparator d, then comparator d is con?ured for trace range de?ition and cannot be used for address bus comparisons. similarly if the trange bits select a range de?ition using comparator c, then comparator c is con?ured for trace range de?ition and cannot be used for address bus comparisons. match[0, 1, 2, 3] map directly to comparators[a, b, c, d] respectively, except in range modes (see section 6.3.2.4 ). comparator priority rules are described in the trigger priority section ( section 6.4.3.4? . 6.4.2.1 exact address comparator match (comparators a and c) with range comparisons disabled, the match condition is an exact equivalence of address/data bus with the value stored in the comparator address/data registers. further quali?ation of the type of access (r/w, word/byte) is possible. comparators a and c do not feature sze or sz control bits, thus the access size is not compared. table 6- 37 lists access considerations without data bus compare. table 6-36 lists access considerations with data bus comparison. to compare byte accesses dbgxdh must be loaded with the data byte, the low byte must be masked out using the dbgxdlm mask register. on word accesses the data byte of the lower address is mapped to dbgxdh. code may contain various access forms of the same address, i.e. a word access of addr[n] or byte access of addr[n+1] both access n+1. at a word access of addr[n], address addr[n+1] does not appear on the address bus and so cannot cause a comparator match if the comparator contains addr[n]. thus it is not possible to monitor all data accesses of addr[n+1] with one comparator. to detect an access of addr[n+1] through a word access of addr[n] the comparator can be configured to addr[n], dbgxdl is loaded with the data pattern and dbgxdhm is cleared so only the data[n+1] is compared on accesses of addr[n]. table 6-36. comparator a and c data bus considerations access address dbgxdh dbgxdl dbgxdhm dbgxdlm example valid match word addr[n] data[n] data[n+1] $ff $ff movw #$word addr[n] con?1 byte addr[n] data[n] x $ff $00 movb #$byte addr[n] con?2 word addr[n] data[n] x $ff $00 movw #$word addr[n] con?2 word addr[n] x data[n+1] $00 $ff movw #$word addr[n] con?3
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 246 freescale semiconductor note using this configuration, a byte access of addr[n] can cause a comparator match if the databus low byte by chance contains the same value as addr[n+1] because the databus comparator does not feature access size comparison and uses the mask as a ?on? care?function. thus masked bits do not prevent a match. comparators a and c feature an ndb control bit to determine if a match occurs when the data bus differs to comparator register contents or when the data bus is equivalent to the comparator register contents. 6.4.2.2 exact address comparator match (comparators b and d) comparators b and d feature sz and sze control bits. if sze is clear, then the comparator address match quali?ation functions the same as for comparators a and c. if the sze bit is set the access size (word or byte) is compared with the sz bit value such that only the speci?d type of access causes a match. thus if con?ured for a byte access of a particular address, a word access covering the same address does not lead to match. 6.4.2.3 data bus comparison ndb dependency comparators a and c each feature an ndb control bit, which allows data bus comparators to be con?ured to either trigger on equivalence or trigger on difference. this allows monitoring of a difference in the contents of an address location from an expected value. when matching on an equivalence (ndb=0), each individual data bus bit position can be masked out by clearing the corresponding mask bit (dbgxdhm/dbgxdlm), so that it is ignored in the comparison. a match occurs when all data bus bits with corresponding mask bits set are equivalent. if all mask register bits are clear, then a match is based on the address bus only, the data bus is ignored. when matching on a difference, mask bits can be cleared to ignore bit positions. a match occurs when any data bus bit with corresponding mask bit set is different. clearing all mask bits, causes all bits to be ignored and prevents a match because no difference can be detected. in this case address bus equivalence does not cause a match. table 6-37. comparator access size considerations comparator address sze sz8 condition for valid match comparators a and c addr[n] word and byte accesses of addr[n] (1) movb #$byte addr[n] movw #$word addr[n] 1. a word access of addr[n-1] also accesses addr[n] but does not generate a match. the comparator address register must contain the exact address used in the code. comparators b and d addr[n] 0 x word and byte accesses of addr[n] 1 movb #$byte addr[n] movw #$word addr[n] comparators b and d addr[n] 1 0 word accesses of addr[n] 1 movw #$word addr[n] comparators b and d addr[n] 1 1 byte accesses of addr[n] movb #$byte addr[n]
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 247 6.4.2.4 range comparisons when using the ab comparator pair for a range comparison, the data bus can also be used for quali?ation by using the comparator a data and data mask registers. furthermore the dbgactl rw and rwe bits can be used to qualify the range comparison on either a read or a write access. the corresponding dbgbctl bits are ignored. similarly when using the cd comparator pair for a range comparison, the data bus can also be used for quali?ation by using the comparator c data and data mask registers. furthermore the dbgcctl rw and rwe bits can be used to qualify the range comparison on either a read or a write access if tagging is not selected. the corresponding dbgdctl bits are ignored. the sze and sz control bits are ignored in range mode. the comparator a and c tag bits are used to tag range comparisons for the ab and cd ranges respectively. the comparator b and d tag bits are ignored in range modes. in order for a range comparison using comparators a and b, both compea and compeb must be set; to disable range comparisons both must be cleared. similarly for a range cd comparison, both compec and comped must be set. the comparator a and c brk bits are used for the ab and cd ranges respectively, the comparator b and d brk bits are ignored in range mode. when con?ured for range comparisons and tagging, the ranges are accurate only to word boundaries. 6.4.2.4.1 inside range (compac_addr address compbd_addr) in the inside range comparator mode, either comparator pair a and b or comparator pair c and d can be con?ured for range comparisons by the control register (dbgc2). the match condition requires that a valid match for both comparators happens on the same bus cycle. a match condition on only one comparator is not valid. an aligned word access which straddles the range boundary will cause a trigger only if the aligned address is inside the range. 6.4.2.4.2 outside range (address < compac_addr or address > compbd_addr) in the outside range comparator mode, either comparator pair a and b or comparator pair c and d can be con?ured for range comparisons. a single match condition on either of the comparators is recognized as valid. an aligned word access which straddles the range boundary will cause a trigger only if the aligned address is outside the range. outside range mode in combination with tagged triggers can be used to detect if the opcode fetches are from an unexpected range. in forced trigger modes the outside range trigger would typically be activated at any interrupt vector fetch or register access. this can be avoided by setting the upper or lower range limit to $7fffff or $000000 respectively. interrupt vector fetches do not cause taghits table 6-38. ndb and mask bit dependency ndb dbgxdhm[n] / dbgxdlm[n] comment 0 0 do not compare data bus bit. 0 1 compare data bus bit. match on equivalence. 1 0 do not compare data bus bit. 1 1 compare data bus bit. match on difference.
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 248 freescale semiconductor 6.4.3 trigger modes trigger modes are used as quali?rs for a state sequencer change of state. the control logic determines the trigger mode and provides a trigger to the state sequencer. the individual trigger modes are described in the following sections. 6.4.3.1 forced trigger on comparator match if a forced trigger comparator match occurs, the trigger immediately initiates a transition to the next state sequencer state whereby the corresponding ?gs in dbgsr are set. the state control register for the current state determines the next state for each trigger. forced triggers are generated as soon as the matching address appears on the address bus, which in the case of opcode fetches occurs several cycles before the opcode execution. for this reason a forced trigger at an opcode address precedes a tagged trigger at the same address by several cycles. 6.4.3.2 trigger on comparator related taghit if a cpu12x taghit occurs, a transition to another state sequencer state is initiated and the corresponding dbgsr ?gs are set. for a comparator related taghit to occur, the s12xdbg must ?st generate tags based on comparator matches. when the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the cpu12x. the state control register for the current state determines the next state for each trigger. 6.4.3.3 trig immediate trigger independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing the trig bit in dbgc1 to a logic ?? if con?ured for begin or mid aligned tracing, this triggers the state sequencer into the final state, if con?ured for end alignment, setting the trig bit disarms the module, ending the session. if breakpoints are enabled, a forced breakpoint request is issued immediately (end alignment) or when tracing has completed (begin or mid alignment). 6.4.3.4 trigger priorities in case of simultaneous triggers, the priority is resolved according to table 6-39 . the lower priority trigger is suppressed. it is thus possible to miss a lower priority trigger if it occurs simultaneously with a trigger of a higher priority. the trigger priorities described in table 6-39 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. the sc[3:0] encoding ensures that a match leading to ?al state has priority over all other matches in each state sequencer state. when con?ured for range modes a simultaneous match of comparators a and c generates an active match0 whilst match2 is suppressed. if a write access to dbgc1 with the arm bit position set occurs simultaneously to a hardware disarm from an internal trigger event, then the arm bit is cleared due to the hardware disarm. table 6-39. trigger priorities priority source action
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 249 6.4.4 state sequence control figure 6-22. state sequencer diagram the state sequencer allows a de?ed sequence of events to provide a trigger point for tracing of data in the trace buffer. once the s12xdbg module has been armed by setting the arm bit in the dbgc1 register, then state1 of the state sequencer is entered. further transitions between the states are then controlled by the state control registers and depend upon a selected trigger mode condition being met. from final state the only permitted transition is back to the disarmed state0. transition between any of the states 1 to 3 is not restricted. each transition updates the ssf[2:0] ?gs in dbgsr accordingly to indicate the current state. alternatively by setting the trig bit in dbgsc1, the state machine can be triggered to state0 or final state depending on tracing alignment. independent of the state sequencer, each comparator channel can be individually con?ured to generate an immediate breakpoint when a match occurs through the use of the brk bits in the dbgxctl registers. thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer transition can be initiated by a match on other channels. if a debug session is ended by a trigger on a channel with brk = 1, the state sequencer transitions through final state for a clock cycle to state0. this is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and the debug module is disarmed. highest trig trigger immediately to ?al state (begin or mid aligned tracing enabled) trigger immediately to state 0 (end aligned or no tracing enabled) match0 (force or tag hit) trigger to next state as de?ed by state control registers match1 (force or tag hit) trigger to next state as de?ed by state control registers match2 (force or tag hit) trigger to next state as de?ed by state control registers lowest match3 (force or tag hit) trigger to next state as de?ed by state control registers table 6-39. trigger priorities state1 final state state3 arm = 1 session complete (disarm) state2 state 0 (disarmed) arm = 0 arm = 0 arm = 0
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 250 freescale semiconductor 6.4.4.1 final state on entering final state a trigger may be issued to the trace buffer according to the trace position control as de?ed by the talign ?ld (see section 6.3.2.3 ). if tsource in the trace control register dbgtcr is cleared then the trace buffer is disabled and the transition to final state can only generate a breakpoint request. in this case or upon completion of a tracing session when tracing is enabled, the arm bit in the dbgc1 register is cleared, returning the module to the disarmed state0. if tracing is enabled, a breakpoint request can occur at the end of the tracing session. if neither tracing nor breakpoints are enabled then when the ?al state is reached it returns automatically to state0 and the debug module is disarmed. 6.4.5 trace buffer operation the trace buffer is a 64 lines deep by 64-bits wide ram array. the s12xdbg module stores trace information in the ram array in a circular buffer format. the ram array can be accessed through a register window (dbgtbh:dbgtbl) using 16-bit wide word accesses. after each complete 64-bit trace buffer line is read, an internal pointer into the ram is incremented so that the next read will receive fresh information. data is stored in the format shown in table 6-40 . after each store the counter register bits dbgcnt[6:0] are incremented. tracing of cpu12x activity is disabled when the bdm is active. reading the trace buffer whilst the dbg is armed returns invalid data and the trace buffer pointer is not incremented. 6.4.5.1 trace trigger alignment using the talign bits (see section 6.3.2.3 ) it is possible to align the trigger with the end, the middle, or the beginning of a tracing session. if end or mid tracing is selected, tracing begins when the arm bit in dbgc1 is set and state1 is entered. the transition to final state if end is selected signals the end of the tracing session. the transition to final state if mid is selected signals that another 32 lines will be traced before ending the tracing session. tracing with begin-trigger starts at the opcode of the trigger. 6.4.5.1.1 storing with begin-trigger storing with begin-trigger, data is not stored in the trace buffer until the final state is entered. once the trigger condition is met the s12xdbg module will remain armed until 64 lines are stored in the trace buffer. if the trigger is at the address of the change-of-?w instruction the change of ?w associated with the trigger will be stored in the trace buffer. using begin-trigger together with tagging, if the tagged instruction is about to be executed then the trace is started. upon completion of the tracing session the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 6.4.5.1.2 storing with mid-trigger storing with mid-trigger, data is stored in the trace buffer as soon as the s12xdbg module is armed. when the trigger condition is met, another 32 lines will be traced before ending the tracing session, irrespective of the number of lines stored before the trigger occurred, then the s12xdbg module is disarmed and no more data is stored. using mid-trigger with tagging, if the tagged instruction is about to
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 251 be executed then the trace is continued for another 32 lines. upon tracing completion the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 6.4.5.1.3 storing with end-trigger storing with end-trigger, data is stored in the trace buffer until the final state is entered, at which point the s12xdbg module will become disarmed and no more data will be stored. if the trigger is at the address of a change of ?w instruction the trigger event will not be stored in the trace buffer. 6.4.5.2 trace modes the s12xdbg module can operate in four trace modes. the mode is selected using the trcmod bits in the dbgtcr register. the modes are described in the following subsections. the trace buffer organization is shown in table 6-40 . 6.4.5.2.1 normal mode in normal mode, change of ?w (cof) program counter (pc) addresses will be stored. cof addresses are de?ed as follows : source address of taken conditional branches (long, short, bit-conditional, and loop primitives) destination address of indexed jmp, jsr, and call instruction destination address of rti, rts, and rtc instructions. vector address of interrupts, except for swi and bdm vectors lbra, bra, bsr, bgnd as well as non-indexed jmp, jsr, and call instructions are not classi?d as change of ?w and are not stored in the trace buffer. change-of-?w addresses stored include the full 23-bit address bus of cpu12x and an information byte, which contains a source/destination bit to indicate whether the stored address was a source address or destination address. note when an cpu12x cof instruction with destination address is executed, the destination address is stored to the trace buffer on instruction completion, indicating the cof has taken place. if an interrupt occurs simultaneously then the next instruction carried out is actually from the interrupt service routine. the instruction at the destination address of the original program ?w gets exectuted after the interrupt service routine. in the following example an irq interrupt occurs during execution of the indexed jmp at address mark1. the brn at the destination (sub_1) is not executed until after the irq service routine but the destination address is entered into the trace buffer to indicate that the indexed jmp cof has taken place. ldx #sub_1 mark1 jmp 0,x ; irq interrupt occurs during execution of this mark2 nop ;
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 252 freescale semiconductor sub_1 brn * ; jmp destination address trace buffer entry 1 ; rti destination address trace buffer entry 3 nop ; addr1 dbne a,part5 ; source address trace buffer entry 4 irq_isr ldab #$f0 ; irq vector $fff2 = trace buffer entry 2 stab var_c1 rti ; the execution ?w taking into account the irq is as follows ldx #sub_1 mark1 jmp 0,x ; irq_isr ldab #$f0 ; stab var_c1 rti ; sub_1 brn * nop ; addr1 dbne a,part5 ; 6.4.5.2.2 loop1 mode loop1 mode, similarly to normal mode also stores only cof address information to the trace buffer, it however allows the ?tering out of redundant information. the intent of loop1 mode is to prevent the trace buffer from being ?led entirely with duplicate information from a looping construct such as delays using the dbne instruction or polling loops using brset/brclr instructions. immediately after address information is placed in the trace buffer, the s12xdbg module writes this value into a background register. this prevents consecutive duplicate address entries in the trace buffer resulting from repeated branches. loop1 mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. it does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the users code that the s12xdbg module is designed to help ?d. 6.4.5.2.3 detail mode in detail mode, address and data for all memory and register accesses is stored in the trace buffer. this mode also features information byte entries to the trace buffer, for each address byte entry. the information byte indicates the size of access (word or byte) and the type of access (read or write). when tracing cpu12x activity in detail mode, all cycles are traced except those when the cpu12x is either in a free or opcode fetch cycle, the address range can be limited to a range speci?d by the trange bits in dbgtcr. this function uses comparators c and d to de?e an address range inside which cpu12x activity should be traced (see table 6-40 ). thus the traced cpu12x activity can be restricted to particular register range accesses. 6.4.5.2.4 pure pc mode in pure pc mode, tracing from the cpu the pc addresses of all executed opcodes, including illegal opcodes, are stored.
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 253 6.4.5.3 trace buffer organization referring to table 6-40 . adrh, adrm, adrl denote address high, middle and low byte respectively. inf bytes contain control information (r/w, s/d etc.). the numerical suf? indicates which tracing step. the information format for loop1 mode and purepc mode is the same as that of normal mode. whilst tracing in normal or loop1 modes each array line contains 2 data entries, thus in this case the dbgcnt[0] is incremented after each separate entry. in detail mode dbgcnt[0] remains cleared whilst the other dbgcnt bits are incremented on each trace buffer entry. when a cof occurs a trace buffer entry is made and the corresponding cdv bit is set. single byte data accesses in detail mode are always stored to the low byte of the trace buffer (cdatal ) and the high byte is cleared. when tracing word accesses, the byte at the lower address is always stored to trace buffer byte3 and the byte at the higher address is stored to byte2 table 6-40. trace buffer organization mode 8-byte wide word buffer 76543210 s12xcpu detail cxinf1 cadrh1 cadrm1 cadrl1 cdatah1 cdatal1 cxinf2 cadrh2 cadrm2 cadrl2 cdatah2 cdatal2 cpu12x other modes cinf1 cpch1 cpcm1 cpcl1 cinf0 cpch0 cpcm0 cpcl0 cinf3 cpch3 cpcm3 cpcl3 cinf2 cpch2 cpcm2 cpcl2
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 254 freescale semiconductor 6.4.5.3.1 information byte organization the format of the control information byte is dependent upon the active trace mode as described below. in normal, loop1, or pure pc modes tracing of cpu12x activity, cinf is used to store control information. in detail mode, cxinf contains the control information cpu12x information byte cxinf information byte this describes the format of the information byte used only when tracing in detail mode. when tracing from the cpu12x in detail mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. in this case the csz and crw bits indicate the type of access being made by the cpu12x. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csd cva 0 cdv 0 0 0 0 figure 6-23. cpu12x information byte cinf table 6-41. cinf field descriptions field description 7 csd source destination indicator this bit indicates if the corresponding stored address is a source or destination address. this is only used in normal and loop1 mode tracing. 0 source address 1 destination address 6 cva vector indicator this bit indicates if the corresponding stored address is a vector address.. vector addresses are destination addresses, thus if cva is set, then the corresponding csd is also set. this is only used in normal and loop1 mode tracing. this bit has no meaning in pure pc mode. 0 indexed jump destination address 1 vector destination address 4 cdv data invalid indicator ?this bit indicates if the trace buffer entry is invalid. it is only used when tracing from both sources in normal, loop1 and pure pc modes, to indicate that the cpu12x trace buffer entry is valid. 0 trace buffer entry is invalid 1 trace buffer entry is valid bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csz crw figure 6-24. information byte cxinf table 6-42. cxinf field descriptions field description 6 csz access type indicator this bit indicates if the access was a byte or word size access.this bit only contains valid information when tracing cpu12x activity in detail mode. 0 word access 1 byte access
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 255 6.4.5.4 reading data from trace buffer the data stored in the trace buffer can be read using either the background debug module (bdm) module or the cpu12x provided the s12xdbg module is not armed, is con?ured for tracing and the system not secured. when the arm bit is written to 1 the trace buffer is locked to prevent reading. the trace buffer can only be unlocked for reading by an aligned word write to dbgtb when the module is disarmed. the trace buffer can only be read through the dbgtb register using aligned word reads, any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. the trace buffer data is read out ?st-in ?st-out. by reading cnt in dbgcnt the number of valid 64-bit lines can be determined. dbgcnt will not decrement as data is read. whilst reading an internal pointer is used to determine the next line to be read. after a tracing session, the pointer points to the oldest data entry, thus if no over?w has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry. the pointer is initialized by each aligned write to dbgtbh to point to the oldest data again. this enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. the least signi?ant word of each 64-bit wide array line is read out ?st. this corresponds to the bytes 1 and 0 of table 6-40 . the bytes containing invalid information (shaded in table 6-40 ) are also read out. reading the trace buffer while the s12xdbg module is armed will return invalid data and no shifting of the ram pointer will occur. 6.4.5.5 trace buffer reset state the trace buffer contents are not initialized by a system reset. thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out. the dbgcnt bits are not cleared by a system reset. thus should a reset occur, the number of valid lines in the trace buffer is indicated by dbgcnt. the internal pointer to the current trace buffer address is initialized by unlocking the trace buffer thus points to the oldest valid data even if a reset occurred during the tracing session. generally debugging occurrences of system resets is best handled using mid or end trigger alignment since the reset may occur before the trace trigger, which in the begin trigger alignment case means no information would be stored in the trace buffer. note an external pin reset that occurs simultaneous to a trace buffer entry can, in very seldom cases, lead to either that entry being corrupted or the ?st entry of the session being corrupted. in such cases the other contents of the trace buffer still contain valid tracing information. the case occurs when the reset assertion coincides with the trace buffer entry clock edge. 5 crw read write indicator ?this bit indicates if the corresponding stored address corresponds to a read or write access. this bit only contains valid information when tracing cpu12x activity in detail mode. 0 write access 1 read access table 6-42. cxinf field descriptions (continued) field description
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 256 freescale semiconductor 6.4.6 tagging a tag follows program information as it advances through the instruction queue. when a tagged instruction reaches the head of the queue a tag hit occurs and triggers the state sequencer. each comparator control register features a tag bit, which controls whether the comparator match will cause a trigger immediately or tag the opcode at the matched address. if a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address for the trigger to occur. using begin trigger together with tagging, if the tagged instruction is about to be executed then the transition to the next state sequencer state occurs. if the transition is to the final state, tracing is started. only upon completion of the tracing session can a breakpoint be generated. similarly using mid trigger with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32 lines. upon tracing completion the breakpoint is generated. using end trigger, when the tagged instruction is about to be executed and the next transition is to final state then a breakpoint is generated immediately, before the tagged instruction is carried out. read/write (r/w), access size (sz) monitoring and data bus monitoring is not useful if tagged triggering is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on the type of access. thus these bits are ignored if tagged triggering is selected. when con?ured for range comparisons and tagging, the ranges are accurate only to word boundaries. s12x tagging is disabled when the bdm becomes active. 6.4.7 breakpoints breakpoints can be generated as follows. from comparator channel triggers to ?al state. using software to write to the trig bit in the dbgc1 register. breakpoints generated via the bdm background command have no affect on the cpu12x in stop or wait mode. 6.4.7.1 breakpoints from internal comparator channel final state triggers breakpoints can be generated when internal comparator channels trigger the state sequencer to the final state. if con?ured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. if a tracing session is selected by tsource, breakpoints are requested when the tracing session has completed, thus if begin or mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see table 6-43 ). if no tracing session is selected, breakpoints are requested immediately. if the brk bit is set on the triggering channel, then the breakpoint is generated immediately independent of tracing trigger alignment.
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 257 6.4.7.2 breakpoints generated via the trig bit if a trig triggers occur, the final state is entered. if a tracing session is selected by tsource, breakpoints are requested when the tracing session has completed, thus if begin or mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see table 6-43 ). if no tracing session is selected, breakpoints are requested immediately. trig breakpoints are possible even if the s12xdbg module is disarmed. 6.4.7.3 s12xdbg breakpoint priorities if a trig trigger occurs after begin or mid aligned tracing has already been triggered by a comparator instigated transition to final state, then trig no longer has an effect. when the associated tracing session is complete, the breakpoint occurs. similarly if a trig is followed by a subsequent trigger from a comparator channel, it has no effect, since tracing has already started. 6.4.7.3.1 s12xdbg breakpoint priorities and bdm interfacing breakpoint operation is dependent on the state of the s12xbdm module. if the s12xbdm module is active, the cpu12x is executing out of bdm ?mware and s12x breakpoints are disabled. in addition, while executing a bdm trace command, tagging into bdm is disabled. if bdm is not active, the breakpoint will give priority to bdm requests over swi requests if the breakpoint coincides with a swi instruction in the users code. on returning from bdm, the swi from user code gets executed. table 6-43. breakpoint setup brk talign dbgbrk breakpoint alignment 0 00 0 fill trace buffer until trigger (no breakpoints ?keep running) 0 00 1 fill trace buffer until trigger, then breakpoint request occurs 0 01 0 start trace buffer at trigger (no breakpoints ?keep running) 0 01 1 start trace buffer at trigger a breakpoint request occurs when trace buffer is full 0 10 0 store a further 32 trace buffer line entries after trigger (no breakpoints ?keep running) 0 10 1 store a further 32 trace buffer line entries after trigger request breakpoint after the 32 further trace buffer entries 1 00,01,10 1 terminate tracing and generate breakpoint immediately on trigger 1 00,01,10 0 terminate tracing immediately on trigger x 11 x reserved table 6-44. breakpoint mapping summary dbgbrk (dbgc1[3]) bdm bit (dbgc1[4]) bdm enabled bdm active s12x breakpoint mapping 0 x x x no breakpoint 1 0 x 0 breakpoint to swi 1 0 x 1 no breakpoint
s12x debug (s12xdbgv3) module mc9s12xhy-family reference manual, rev. 1.01 258 freescale semiconductor bdm cannot be entered from a breakpoint unless the enable bit is set in the bdm. if entry to bdm via a bgnd instruction is attempted and the enable bit in the bdm is cleared, the cpu12x actually executes the bdm ?mware code. it checks the enable and returns if enable is not set. if not serviced by the monitor then the breakpoint is re-asserted when the bdm returns to normal cpu12x ?w. if the comparator register contents coincide with the swi/bdm vector address then an swi in user code and dbg breakpoint could occur simultaneously. the cpu12x ensures that bdm requests have a higher priority than swi requests. returning from the bdm/swi service routine care must be taken to avoid re triggering a breakpoint. note when program control returns from a tagged breakpoint using an rti or bdm go command without program counter modi?ation it will return to the instruction whose tag generated the breakpoint. to avoid re triggering a breakpoint at the same location recon?ure the s12xdbg module in the swi routine, if con?ured for an swi breakpoint, or over the bdm interface by executing a trace command before the go to increment the program ?w past the tagged instruction. 1 1 0 x breakpoint to swi 1 1 1 0 breakpoint to bdm 1 1 1 1 no breakpoint table 6-44. breakpoint mapping summary
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 259 chapter 7 s12xe clocks and reset generator (s12xecrgv2) 7.1 introduction this speci?ation describes the function of the clocks and reset generator (s12xecrg). 7.1.1 features the main features of this block are: phase locked loop (ipll) frequency multiplier with internal ?ter reference divider post divider con?urable internal ?ter (no external pin) optional frequency modulation for de?ed jitter and reduced emission automatic frequency lock detector interrupt request on entry or exit from locked condition self clock mode in absence of reference clock system clock generator clock quality check user selectable fast wake-up from stop in self-clock mode for power saving and immediate program execution clock switch for either oscillator or pll based system clocks computer operating properly (cop) watchdog timer with time-out clear window. system reset generation from the following possible sources: power on reset low voltage reset illegal address reset cop reset loss of clock reset table 7-1. revision history revision number revision date sections affected description of changes v02.00 18 sep. 2009 initial release derived from s12xecrg v01.04 plus modi?ations for lcd clock output.
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 260 freescale semiconductor external pin reset real-time interrupt (rti) 7.1.2 modes of operation this subsection lists and brie? describes all operating modes supported by the s12xecrg. run mode all functional parts of the s12xecrg are running during normal run mode. if rti or cop functionality is required the individual bits of the associated rate select registers (copctl, rtictl) have to be set to a non zero value. wait mode in this mode the ipll can be disabled automatically depending on the pllwai bit. stop mode depending on the setting of the pstp bit stop mode can be differentiated between full stop mode (pstp = 0) and pseudo stop mode (pstp = 1). full stop mode the oscillator is disabled and thus all system and core clocks are stopped. the cop and the rti remain frozen. pseudo stop mode the oscillator continues to run and most of the system and core clocks are stopped. if the respective enable bits are set the cop and rti will continue to run, else they remain frozen. self clock mode self clock mode will be entered if the clock monitor enable bit (cme) and the self clock mode enable bit (scme) are both asserted and the clock monitor in the oscillator block detects a loss of clock. as soon as self clock mode is entered the s12xecrg starts to perform a clock quality check. self clock mode remains active until the clock quality check indicates that the required quality of the incoming clock signal is met (frequency and amplitude). self clock mode should be used for safety purposes only. it provides reduced functionality to the mcu in case a loss of clock is causing severe system conditions. 7.1.3 block diagram figure 7-1 shows a block diagram of the s12xecrg.
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 261 figure 7-1. block diagram of s12xecrg 7.2 signal description this section lists and describes the signals that connect off chip. 7.2.1 v ddpll , v sspll these pins provides operating voltage (v ddpll ) and ground (v sspll ) for the ipll circuitry. this allows the supply voltage to the ipll to be independently bypassed. even if ipll usage is not required v ddpll and v sspll must be connected to properly. 7.2.2 reset reset is an active low bidirectional reset pin. as an input it initializes the mcu asynchronously to a known start-up state. as an open-drain output it indicates that an system reset (internal to mcu) has been triggered. icrg registers cop reset rti ipll v ddpll v sspll extal xtal bus clock system reset oscillator clock pllclk oscclk core clock cm fail xclks power on reset low voltage reset cop timeout real time interrupt pll lock interrupt self clock mode interrupt s12x_mmc illegal address reset reset generator clock quality checker clock and reset control voltage regulator clock monitor oscillator lcd clock
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 262 freescale semiconductor 7.3 memory map and registers this section provides a detailed description of all registers accessible in the s12xecrg. 7.3.1 module memory map figure 7-2 gives an overview on all s12xecrg registers. note register address = base address + address offset, where the base address is de?ed at the mcu level and the address offset is de?ed at the module level. address name bit 7 6 5 4 3 2 1 bit 0 0x0000 synr r vcofrq[1:0] syndiv[5:0] w 0x0001 refdv r reffrq[1:0] refdiv[5:0] w 0x0002 postdiv r0 0 0 postdiv[4:0] w 0x0003 crgflg r rtif porf lvrf lockif lock ilaf scmif scm w 0x0004 crgint r rtie 00 lockie 00 scmie 0 w 0x0005 clksel r pllsel pstp xclks 0 pllwai 0 rtiwai copwai w 0x0006 pllctl r cme pllon fm1 fm0 fstwkp pre pce scme w 0x0007 rtictl r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w 0x0008 copctl r wcop rsbck 000 cr2 cr1 cr0 w wrtmask 0x0009 forbyp 2 r0 0 0 000 0 0 w 0x000a ctctl 2 r0 0 0 000 0 0 w 0x000b armcop r0 0 0 000 0 0 w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2. forbyp and ctctl are intended for factory test purposes only. = unimplemented or reserved figure 7-2. crg register summary
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 263 7.3.2 register descriptions this section describes in address order all the s12xecrg registers and their individual bits. 7.3.2.1 s12xecrg synthesizer register (synr) the synr register controls the multiplication factor of the ipll and selects the vco frequency range. read: anytime write: anytime except if pllsel = 1 note write to this register initializes the lock detector bit. note f vco must be within the speci?d vco frequency lock range. f. bus (bus clock) must not exceed the speci?d maximum. if postdiv = $00 then f pll is same as f vco (divide by one). the vcofrq[1:0] bit are used to con?ure the vco gain for optimal stability and lock time. for correct ipll operation the vcofrq[1:0] bits have to be selected according to the actual target vcoclk frequency as shown in table 7-2 . setting the vcofrq[1:0] bits wrong can result in a non functional ipll (no locking and/or insuf?ient stability). module base + 0x0000 76543210 r vcofrq[1:0] syndiv[5:0] w reset 0 0 0 00000 figure 7-3. s12xecrg synthesizer register (synr) table 7-2. vco clock frequency selection vcoclk frequency ranges vcofrq[1:0] 32mhz <= f vco <= 48mhz 00 48mhz < f vco <= 80mhz 01 reserved 10 80mhz < f vco <= 120mhz 11 f vco 2f osc syndiv 1 + () refdiv 1 + () ------------------------------------- = f pll f vco 2 postdiv ----------------------------------- - = f bus f pll 2 ------------ - =
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 264 freescale semiconductor 7.3.2.2 s12xecrg reference divider register (refdv) the refdv register provides a ?er granularity for the ipll multiplier steps. read: anytime write: anytime except when pllsel = 1 note write to this register initializes the lock detector bit. the reffrq[1:0] bit are used to con?ure the internal pll ?ter for optimal stability and lock time. for correct ipll operation the reffrq[1:0] bits have to be selected according to the actual refclk frequency as shown in figure 7-3 . setting the reffrq[1:0] bits wrong can result in a non functional ipll (no locking and/or insuf?ient stability). 7.3.2.3 s12xecrg post divider register (postdiv) the postdiv register controls the frequency ratio between the vcoclk and pllclk. the count in the ?al divider divides vcoclk frequency by 1 or 2*postdiv. note that if postdiv = $00 f pll =f vco (divide by one). module base + 0x0001 76543210 r reffrq[1:0] refdiv[5:0] w reset 0 0 0 00000 figure 7-4. s12xecrg reference divider register (refdv) table 7-3. reference clock frequency selection refclk frequency ranges reffrq[1:0] 1mhz <= f ref <= 2mhz 00 2mhz < f ref <= 6mhz 01 6mhz < f ref <= 12mhz 10 f ref >12mhz 11 f ref f osc refdiv 1 + () ------------------------------------ =
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 265 read: anytime write: anytime except if pllsel = 1 note if postdiv = $00 then f pll is identical to f vco (divide by one). 7.3.2.4 s12xecrg flags register (crgflg) this register provides s12xecrg status bits and ?gs. read: anytime write: refer to each bit for individual write conditions module base + 0x0002 76543210 r000 postdiv[4:0] w reset 0 0 0 00000 = unimplemented or reserved figure 7-5. s12xecrg post divider register (postdiv) module base + 0x0003 76543210 r rtif porf lvrf lockif lock ilaf scmif scm w reset 0 note 1 note 2 note 3 0000 1. porf is set to 1 when a power on reset occurs. unaffected by system reset. 2. lvrf is set to 1 when a low voltage reset occurs. unaffected by system reset. 3. ilaf is set to 1 when an illegal address reset occurs. unaffected by system reset. cleared by power on or low voltage reset. = unimplemented or reserved figure 7-6. s12xecrg flags register (crgflg) f pll f vco 2xpostdiv () -------------------------------------- =
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 266 freescale semiconductor 7.3.2.5 s12xecrg interrupt enable register (crgint) this register enables s12xecrg interrupt requests. table 7-4. crgflg field descriptions field description 7 rtif real time interrupt flag rtif is set to 1 at the end of the rti period. this ?g can only be cleared by writing a 1. writing a 0 has no effect. if enabled (rtie=1), rtif causes an interrupt request. 0 rti time-out has not yet occurred. 1 rti time-out has occurred. 6 porf power on reset flag porf is set to 1 when a power on reset occurs. this ?g can only be cleared by writing a 1. writing a 0 has no effect. 0 power on reset has not occurred. 1 power on reset has occurred. 5 lvrf low voltage reset flag lvrf is set to 1 when a low voltage reset occurs. this ?g can only be cleared by writing a 1. writing a 0 has no effect. 0 low voltage reset has not occurred. 1 low voltage reset has occurred. 4 lockif ipll lock interrupt flag lockif is set to 1 when lock status bit changes. this ?g can only be cleared by writing a 1. writing a 0 has no effect.if enabled (lockie=1), lockif causes an interrupt request. 0 no change in lock bit. 1 lock bit has changed. 3 lock lock status bit lock re?cts the current state of ipll lock condition. this bit is cleared in self clock mode. writes have no effect. 0 vcoclk is not within the desired tolerance of the target frequency. 1 vcoclk is within the desired tolerance of the target frequency. 2 ilaf illegal address reset flag ilaf is set to 1 when an illegal address reset occurs. refer to s12xmmc block guide for details. this ?g can only be cleared by writing a 1. writing a 0 has no effect. 0 illegal address reset has not occurred. 1 illegal address reset has occurred. 1 scmif self clock mode interrupt flag ?scmif is set to 1 when scm status bit changes. this ?g can only be cleared by writing a 1. writing a 0 has no effect. if enabled (scmie=1), scmif causes an interrupt request. 0 no change in scm bit. 1 scm bit has changed. 0 scm self clock mode status bit ?scm re?cts the current clocking mode. writes have no effect. 0 mcu is operating normally with oscclk available. 1 mcu is operating in self clock mode with oscclk in an unknown state. all clocks are derived from pllclk running at its minimum frequency f scm . module base + 0x0004 76543210 r rtie 00 lockie 00 scmie 0 w reset 0 0 0 00000 = unimplemented or reserved figure 7-7. s12xecrg interrupt enable register (crgint)
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 267 read: anytime write: anytime 7.3.2.6 s12xecrg clock select register (clksel) this register controls s12xecrg clock selection. refer to figure 7-16 for more details on the effect of each bit. read: anytime write: refer to each bit for individual write conditions table 7-5. crgint field descriptions field description 7 rtie real time interrupt enable bit 0 interrupt requests from rti are disabled. 1 interrupt will be requested whenever rtif is set. 4 lockie lock interrupt enable bit 0 lock interrupt requests are disabled. 1 interrupt will be requested whenever lockif is set. 1 scmie self clock mode interrupt enable bit 0 scm interrupt requests are disabled. 1 interrupt will be requested whenever scmif is set. module base + 0x0005 76543210 r pllsel pstp xclks 0 pllwai 0 rtiwai copwai w reset 0 0 0 00000 = unimplemented or reserved figure 7-8. s12xecrg clock select register (clksel)
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 268 freescale semiconductor 7.3.2.7 s12xecrg ipll control register (pllctl) this register controls the ipll functionality. table 7-6. clksel field descriptions field description 7 pllsel pll select bit write: anytime. writing a one when lock=0 has no effect. this prevents the selection of an unstable pllclk as sysclk. pllsel bit is cleared when the mcu enters self clock mode, stop mode or wait mode with pllwai bit set. it is recommended to read back the pllsel bit to make sure pllclk has really been selected as sysclk, as lock status bit could theoretically change at the very moment writing the pllsel bit. 0 system clocks are derived from oscclk (f bus = f osc / 2). 1 system clocks are derived from pllclk (f bus = f pll / 2). 6 pstp pseudo stop bit write: anytime this bit controls the functionality of the oscillator during stop mode. 0 oscillator is disabled in stop mode. 1 oscillator continues to run in stop mode (pseudo stop). note: pseudo stop mode allows for faster stop recovery and reduces the mechanical stress and aging of the resonator in case of frequent stop conditions at the expense of a slightly increased power consumption. 5 xclks oscillator con?uration status bit ?this read-only bit shows the oscillator con?uration status. 0 loop controlled pierce oscillator is selected. 1 external clock / full swing pierce oscillator is selected. 3 pllwai pll stops in wait mode bit write: anytime if pllwai is set, the s12xecrg will clear the pllsel bit before entering wait mode. the pllon bit remains set during wait mode but the ipll is powered down. upon exiting wait mode, the pllsel bit has to be set manually if pll clock is required. 0 ipll keeps running in wait mode. 1 ipll stops in wait mode. 1 rtiwai rti stops in wait mode bit write: anytime 0 rti keeps running in wait mode. 1 rti stops and initializes the rti dividers whenever the part goes into wait mode. 0 copwai cop stops in wait mode bit normal modes: write once special modes: write anytime 0 cop keeps running in wait mode. 1 cop stops and initializes the cop counter whenever the part goes into wait mode. module base + 0x0006 76543210 r cme pllon fm1 fm0 fstwkp pre pce scme w reset 1 1 0 00001 figure 7-9. s12xecrg ipll control register (pllctl)
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 269 read: anytime write: refer to each bit for individual write conditions table 7-7. pllctl field descriptions field description 7 cme clock monitor enable bit ?cme enables the clock monitor. write anytime except when scm = 1. 0 clock monitor is disabled. 1 clock monitor is enabled. slow or stopped clocks will cause a clock monitor reset sequence or self clock mode. note: operating with cme=0 will not detect any loss of clock. in case of poor clock quality this could cause unpredictable operation of the mcu! in stop mode (pstp=0) the clock monitor is disabled independently of the cme bit setting and any loss of external clock will not be detected. also after wake-up from stop mode (pstp = 0) with fast wake-up enabled (fstwkp = 1) the clock monitor is disabled independently of the cme bit setting and any loss of external clock will not be detected. 6 pllon phase lock loop on bit pllon turns on the ipll circuitry. in self clock mode, the ipll is turned on, but the pllon bit reads the last written value. write anytime except when pllsel = 1. 0 ipll is turned off. 1 ipll is turned on. 5, 4 fm1, fm0 ipll frequency modulation enable bit ?fm1 and fm0 enable additional frequency modulation on the vcoclk. this is to reduce noise emission. the modulation frequency is f ref divided by 16. write anytime except when pllsel = 1. see table 7-8 for coding. 3 fstwkp fast wake-up from full stop bit fstwkp enables fast wake-up from full stop mode. write anytime. if self- clock mode is disabled (scme = 0) this bit has no effect. 0 fast wake-up from full stop mode is disabled. 1 fast wake-up from full stop mode is enabled. when waking up from full stop mode the system will immediately resume operation in self-clock mode (see section 7.4.1.4, ?lock quality checker ). the scmif ?g will not be set. the system will remain in self-clock mode with oscillator and clock monitor disabled until fstwkp bit is cleared. the clearing of fstwkp will start the oscillator, the clock monitor and the clock quality check. if the clock quality check is successful, the s12xecrg will switch all system clocks to oscclk. the scmif ?g will be set. see application examples in figure 7-19 and figure 7-20 . 2 pre rti enable during pseudo stop bit ?pre enables the rti during pseudo stop mode. write anytime. 0 rti stops running during pseudo stop mode. 1 rti continues running during pseudo stop mode. note: if the pre bit is cleared the rti dividers will go static while pseudo stop mode is active. the rti dividers will not initialize like in wait mode with rtiwai bit set. 1 pce cop enable during pseudo stop bit ?pce enables the cop during pseudo stop mode. write anytime. 0 cop stops running during pseudo stop mode 1 cop continues running during pseudo stop mode note: if the pce bit is cleared the cop dividers will go static while pseudo stop mode is active. the cop dividers will not initialize like in wait mode with copwai bit set. 0 scme self clock mode enable bit normal modes: write once special modes: write anytime scme can not be cleared while operating in self clock mode (scm = 1). 0 detection of crystal clock failure causes clock monitor reset (see section 7.5.1.1, ?lock monitor reset ). 1 detection of crystal clock failure forces the mcu in self clock mode (see section 7.4.2.2, ?elf clock mode ).
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 270 freescale semiconductor 7.3.2.8 s12xecrg rti control register (rtictl) this register selects the timeout period for the real time interrupt. read: anytime write: anytime note a write to this register initializes the rti counter. table 7-8. fm amplitude selection fm1 fm0 fm amplitude / f vco variation 0 0 fm off 01 1% 10 2% 11 4% module base + 0x0007 76543210 r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w reset 0 0 0 00000 figure 7-10. s12xecrg rti control register (rtictl) table 7-9. rtictl field descriptions field description 7 rtdec decimal or binary divider select bit ?rtdec selects decimal or binary based prescaler values. 0 binary based divider value. see table 7-10 1 decimal based divider value. see table 7-11 6? rtr[6:4] real time interrupt prescale rate select bits these bits select the prescale rate for the rti. see ta bl e 7 - 10 and table 7-11 . 3? rtr[3:0] real time interrupt modulus counter select bits ?these bits select the modulus counter target value to provide additional granularity. table 7-10 and table 7-11 show all possible divide values selectable by the rtictl register. the source clock for the rti is oscclk. table 7-10. rti frequency divide rates for rtdec = 0 rtr[3:0] rtr[6:4] = 000 (off) 001 (2 10 ) 010 (2 11 ) 011 (2 12 ) 100 (2 13 ) 101 (2 14 ) 110 (2 15 ) 111 (2 16 ) 0000 ( 1) off (1) 2 10 2 11 2 12 2 13 2 14 2 15 2 16
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 271 0001 ( 2) off 2x2 10 2x2 11 2x2 12 2x2 13 2x2 14 2x2 15 2x2 16 0010 ( 3) off 3x2 10 3x2 11 3x2 12 3x2 13 3x2 14 3x2 15 3x2 16 0011 ( 4) off 4x2 10 4x2 11 4x2 12 4x2 13 4x2 14 4x2 15 4x2 16 0100 ( 5) off 5x2 10 5x2 11 5x2 12 5x2 13 5x2 14 5x2 15 5x2 16 0101 ( 6) off 6x2 10 6x2 11 6x2 12 6x2 13 6x2 14 6x2 15 6x2 16 0110 ( 7) off 7x2 10 7x2 11 7x2 12 7x2 13 7x2 14 7x2 15 7x2 16 0111 ( 8) off 8x2 10 8x2 11 8x2 12 8x2 13 8x2 14 8x2 15 8x2 16 1000 ( 9) off 9x2 10 9x2 11 9x2 12 9x2 13 9x2 14 9x2 15 9x2 16 1001 ( 10) off 10x2 10 10x2 11 10x2 12 10x2 13 10x2 14 10x2 15 10x2 16 1010 ( 11) off 11x2 10 11x2 11 11x2 12 11x2 13 11x2 14 11x2 15 11x2 16 1011 ( 12) off 12x2 10 12x2 11 12x2 12 12x2 13 12x2 14 12x2 15 12x2 16 1100 ( 13) off 13x2 10 13x2 11 13x2 12 13x2 13 13x2 14 13x2 15 13x2 16 1101 ( 14) off 14x2 10 14x2 11 14x2 12 14x2 13 14x2 14 14x2 15 14x2 16 1110 ( 15) off 15x2 10 15x2 11 15x2 12 15x2 13 15x2 14 15x2 15 15x2 16 1111 ( 16) off 16x2 10 16x2 11 16x2 12 16x2 13 16x2 14 16x2 15 16x2 16 1. denotes the default value out of reset.this value should be used to disable the rti to ensure future backwards compatibility . table 7-11. rti frequency divide rates for rtdec=1 rtr[3:0] rtr[6:4] = 000 (1x10 3 ) 001 (2x10 3 ) 010 (5x10 3 ) 011 (10x10 3 ) 100 (20x10 3 ) 101 (50x10 3 ) 110 (100x10 3 ) 111 (200x10 3 ) 0000 ( 1) 1x10 3 2x10 3 5x10 3 10x10 3 20x10 3 50x10 3 100x10 3 200x10 3 0001 ( 2) 2x10 3 4x10 3 10x10 3 20x10 3 40x10 3 100x10 3 200x10 3 400x10 3 0010 ( 3) 3x10 3 6x10 3 15x10 3 30x10 3 60x10 3 150x10 3 300x10 3 600x10 3 0011 ( 4) 4x10 3 8x10 3 20x10 3 40x10 3 80x10 3 200x10 3 400x10 3 800x10 3 0100 ( 5) 5x10 3 10x10 3 25x10 3 50x10 3 100x10 3 250x10 3 500x10 3 1x10 6 0101 ( 6) 6x10 3 12x10 3 30x10 3 60x10 3 120x10 3 300x10 3 600x10 3 1.2x10 6 table 7-10. rti frequency divide rates for rtdec = 0 rtr[3:0] rtr[6:4] = 000 (off) 001 (2 10 ) 010 (2 11 ) 011 (2 12 ) 100 (2 13 ) 101 (2 14 ) 110 (2 15 ) 111 (2 16 )
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 272 freescale semiconductor 7.3.2.9 s12xecrg cop control register (copctl) this register controls the cop (computer operating properly) watchdog. read: anytime write: 1. rsbck: anytime in special modes; write to ??but not to ??in all other modes 2. wcop, cr2, cr1, cr0: anytime in special modes write once in all other modes writing cr[2:0] to ?00?has no effect, but counts for the ?rite once?condition. writing wcop to ??has no effect, but counts for the ?rite once?condition. 0110 ( 7) 7x10 3 14x10 3 35x10 3 70x10 3 140x10 3 350x10 3 700x10 3 1.4x10 6 0111 ( 8) 8x10 3 16x10 3 40x10 3 80x10 3 160x10 3 400x10 3 800x10 3 1.6x10 6 1000 ( 9) 9x10 3 18x10 3 45x10 3 90x10 3 180x10 3 450x10 3 900x10 3 1.8x10 6 1001 ( 10) 10 x10 3 20x10 3 50x10 3 100x10 3 200x10 3 500x10 3 1x10 6 2x10 6 1010 ( 11) 11 x10 3 22x10 3 55x10 3 110x10 3 220x10 3 550x10 3 1.1x10 6 2.2x10 6 1011 ( 12) 12x10 3 24x10 3 60x10 3 120x10 3 240x10 3 600x10 3 1.2x10 6 2.4x10 6 1100 ( 13) 13x10 3 26x10 3 65x10 3 130x10 3 260x10 3 650x10 3 1.3x10 6 2.6x10 6 1101 ( 14) 14x10 3 28x10 3 70x10 3 140x10 3 280x10 3 700x10 3 1.4x10 6 2.8x10 6 1110 ( 15) 15x10 3 30x10 3 75x10 3 150x10 3 300x10 3 750x10 3 1.5x10 6 3x10 6 1111 ( 16) 16x10 3 32x10 3 80x10 3 160x10 3 320x10 3 800x10 3 1.6x10 6 3.2x10 6 module base + 0x0008 76543210 r wcop rsbck 000 cr2 cr1 cr0 w wrtmask reset 1 00000000 1. refer to device user guide (section: s12xecrg) for reset values of wcop, cr2, cr1 and cr0. = unimplemented or reserved figure 7-11. s12xecrg cop control register (copctl) table 7-11. rti frequency divide rates for rtdec=1 rtr[3:0] rtr[6:4] = 000 (1x10 3 ) 001 (2x10 3 ) 010 (5x10 3 ) 011 (10x10 3 ) 100 (20x10 3 ) 101 (50x10 3 ) 110 (100x10 3 ) 111 (200x10 3 )
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 273 the cop time-out period is restarted if one these two conditions is true: 1. writing a non zero value to cr[2:0] (anytime in special modes, once in all other modes) with wrtmask = 0. or 2. changing rsbck bit from ??to ?? table 7-12. copctl field descriptions field description 7 wcop window cop mode bit when set, a write to the armcop register must occur in the last 25% of the selected period. a write during the ?st 75% of the selected period will reset the part. as long as all writes occur during this window, $55 can be written as often as desired. once $aa is written after the $55, the time-out logic restarts and the user must wait until the next window before writing to armcop. table 7-13 shows the duration of this window for the seven available cop rates. 0 normal cop operation 1 window cop operation 6 rsbck cop and rti stop in active bdm mode bit 0 allows the cop and rti to keep running in active bdm mode. 1 stops the cop and rti counters whenever the part is in active bdm mode. 5 wrtmask write mask for wcop and cr[2:0] bit this write-only bit serves as a mask for the wcop and cr[2:0] bits while writing the copctl register. it is intended for bdm writing the rsbck without touching the contents of wcop and cr[2:0]. 0 write of wcop and cr[2:0] has an effect with this write of copctl 1 write of wcop and cr[2:0] has no effect with this write of copctl. (does not count for ?rite once?) 2? cr[2:0] cop watchdog timer rate select ?these bits select the cop time-out rate (see table 7-13 ). writing a nonzero value to cr[2:0] enables the cop counter and starts the time-out period. a cop counter time-out causes a system reset. this can be avoided by periodically (before time-out) reinitialize the cop counter via the armcop register. while all of the following four conditions are true the cr[2:0], wcop bits are ignored and the cop operates at highest time-out period ( 2 24 cycles) in normal cop mode (window cop mode disabled): 1) cop is enabled (cr[2:0] is not 000) 2) bdm mode active 3) rsbck = 0 4) operation in emulation or special modes table 7-13. cop watchdog rates (1) cr2 cr1 cr0 oscclk cycles to timeout 0 0 0 cop disabled 001 2 14 010 2 16 011 2 18 100 2 20 101 2 22 110 2 23
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 274 freescale semiconductor 7.3.2.10 reserved register (forbyp) note this reserved register is designed for factory test purposes only, and is not intended for general user access. writing to this register when in special modes can alter the s12xecrgs functionality. read: always read $00 except in special modes write: only in special modes 7.3.2.11 reserved register (ctctl) note this reserved register is designed for factory test purposes only, and is not intended for general user access. writing to this register when in special test modes can alter the s12xecrgs functionality. read: always read $00 except in special modes 111 2 24 1. oscclk cycles are referenced from the previous cop time-out reset (writing $55/$aa to the armcop register) module base + 0x0009 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 7-12. reserved register (forbyp) module base + 0x000a 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 7-13. reserved register (ctctl) table 7-13. cop watchdog rates (1) cr2 cr1 cr0 oscclk cycles to timeout
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 275 write: only in special modes 7.3.2.12 s12xecrg cop timer arm/reset register (armcop) this register is used to restart the cop time-out period. read: always reads $00 write: anytime when the cop is disabled (cr[2:0] = ?00? writing to this register has no effect. when the cop is enabled by setting cr[2:0] nonzero, the following applies: writing any value other than $55 or $aa causes a cop reset. to restart the cop time-out period you must write $55 followed by a write of $aa. other instructions may be executed between these writes but the sequence ($55, $aa) must be completed prior to cop end of time-out period to avoid a cop reset. sequences of $55 writes or sequences of $aa writes are allowed. when the wcop bit is set, $55 and $aa writes must be done in the last 25% of the selected time-out period; writing any value in the ?st 75% of the selected period will cause a cop reset. module base + 0x000b 76543210 r00000000 w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset 0 0 0 00000 figure 7-14. s12xecrg armcop register diagram
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 276 freescale semiconductor 7.4 functional description 7.4.1 functional blocks 7.4.1.1 phase locked loop with internal filter (ipll) the ipll is used to run the mcu from a different time base than the incoming oscclk. figure 7-15 shows a block diagram of the ipll. figure 7-15. ipll functional diagram for increased ?xibility, oscclk can be divided in a range of 1 to 64 to generate the reference frequency refclk using the refdiv[5:0] bits. this offers a ?er multiplication granularity. based on the syndiv[5:0] bits the ipll generates the vcoclk by multiplying the reference clock by a multiple of 2, 4, 6,... 126, 128. based on the postdiv[4:0] bits the vcoclk can be divided in a range of 1,2,4,6,8,... to 62 to generate the pllclk. . note although it is possible to set the dividers to command a very high clock frequency, do not exceed the speci?d bus frequency limit for the mcu. if (pllsel = 1) then f bus = f pll / 2. if postdiv = $00 the f pll is identical to f vco (divide by one) several examples of ipll divider settings are shown in table 7-14 . shaded rows indicated that these settings are not recommended. the following rules help to achieve optimum stability and shortest lock time: use lowest possible f vco / f ref ratio (syndiv value). use highest possible refclk frequency f ref . reduced consumption oscillator extal xtal oscclk pllclk reference programmable divider pdet phase detector refdiv[5:0] loop programmable divider syndiv[5:0] vco lock up down lock detector refclk fbclk v ddpll /v sspll clock monitor v ddpll /v sspll v dd /v ss supplied by: cpump and filter post programmable divider postdiv[4:0] vcoclk f pll 2f osc syndiv 1 + refdiv 1 + [] 2 postdiv [] ------------------------------------------------------------------------------ =
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 277 7.4.1.1.1 ipll operation the oscillator output clock signal (oscclk) is fed through the reference programmable divider and is divided in a range of 1 to 64 (refdiv+1) to output the refclk. the vco output clock, (vcoclk) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2 x (syndiv +1)] to output the fbclk. the vcoclk is fed to the ?al programmable divider and is divided in a range of 1,2,4,6,8,... to 62 (2*postdiv) to output the pllclk. see figure 7-15 . the phase detector then compares the fbclk, with the refclk. correction pulses are generated based on the phase difference between the two signals. the loop ?ter then slightly alters the dc voltage on the internal ?ter capacitor, based on the width and direction of the correction pulse. the user must select the range of the refclk frequency and the range of the vcoclk frequency to ensure that the correct ipll loop bandwidth is set. the lock detector compares the frequencies of the fbclk, and the refclk. therefore, the speed of the lock detector is directly proportional to the reference clock frequency. the circuit determines the lock condition based on this comparison. if ipll lock interrupt requests are enabled, the software can wait for an interrupt request and then check the lock bit. if interrupt requests are disabled, software can poll the lock bit continuously (during ipll start-up, usually) or at periodic intervals. in either case, only when the lock bit is set, the pllclk can be selected as the source for the system and core clocks. if the ipll is selected as the source for the system and core clocks and the lock bit is clear, the ipll has suffered a severe noise hit and the software must take appropriate action, depending on the application. the lock bit is a read-only indicator of the locked state of the ipll. the lock bit is set when the vco frequency is within a certain tolerance, ? lock , and is cleared when the vco frequency is out of a certain tolerance, ? unl . interrupt requests can occur if enabled (lockie = 1) when the lock condition changes, toggling the lock bit. table 7-14. examples of ipll divider settings f osc refdiv[5:0] f ref reffrq[1:0] syndiv[5:0] f vco vcofrq[1:0] postdiv[4:0] f pll f bus 4mhz $01 2mhz 01 $18 100mhz 11 $00 100mhz 50 mhz 8mhz $03 2mhz 01 $18 100mhz 11 $00 100mhz 50 mhz 4mhz $00 4mhz 01 $09 80mhz 01 $00 80mhz 40mhz 8mhz $00 8mhz 10 $04 80mhz 01 $00 80mhz 40mhz 4mhz $00 4mhz 01 $03 32mhz 00 $01 16mhz 8mhz 4mhz $01 2mhz 01 $18 100mhz 11 $01 50mhz 25mhz 4mhz $03 1mhz 00 $18 50mhz 01 $00 50mhz 25mhz 4mhz $03 1mhz 00 $31 100mhz 11 $01 50mhz 25mhz
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 278 freescale semiconductor 7.4.1.2 system clocks generator figure 7-16. system clocks generator the clock generator creates the clocks used in the mcu (see figure 7-16 ). the gating condition placed on top of the individual clock gates indicates the dependencies of different modes (stop, wait) and the setting of the respective con?uration bits. the peripheral modules use the bus clock. some peripheral modules also use the oscillator clock. if the mcu enters self clock mode (see section 7.4.2.2, ?elf clock mode ) oscillator clock source is switched to pllclk running at its minimum frequency f scm . the bus clock is used to generate the clock visible at the eclk pin. the core clock signal is the clock for the cpu. the core clock is twice the bus clock. but note that a cpu cycle corresponds to one bus clock. ipll clock mode is selected with pllsel bit in the clksel register. when selected, the ipll output clock drives sysclk for the main system including the cpu and peripherals. the ipll cannot be turned off by clearing the pllon bit, if the ipll clock is selected. when pllsel is changed, it takes a maximum of 4 oscclk plus 4 pllclk cycles to make the transition. during the transition, all clocks freeze and cpu activity ceases. oscillator phase lock loop (iipll) extal xtal sysclk rti oscclk pllclk clock phase generator bus clock clock monitor 1 0 pllsel or scm 2 core clock cop oscillator = clock gate gating condition wait(rtiwai), stop( pstp, pre), rti enable wait(copwai), stop( pstp, pce), cop enable stop 1 0 scm clock stop stop( pstp), lcd enable lcd clock
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 279 7.4.1.3 clock monitor (cm) if no oscclk edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event. the s12xecrg then asserts self clock mode or generates a system reset depending on the state of scme bit. if the clock monitor is disabled or the presence of clocks is detected no failure is indicated by the oscillator block.the clock monitor function is enabled/disabled by the cme control bit. 7.4.1.4 clock quality checker the clock monitor performs a coarse check on the incoming clock signal. the clock quality checker provides a more accurate check in addition to the clock monitor. a clock quality check is triggered by any of the following events: power on reset ( por ) low voltage reset ( lvr ) wake-up from full stop mode ( exit full stop ) clock monitor fail indication ( cm fail ) a time window of 50000 pllclk cycles 6 is called check window . a number greater equal than 4096 rising oscclk edges within a check window is called osc ok . note that osc ok immediately terminates the current check window . see figure 7-17 as an example. figure 7-17. check window example 6. ipll is running at self clock mode frequency f scm . 12 49999 50000 pllclk check window 12345 4095 4096 3 oscclk osc ok
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 280 freescale semiconductor the sequence for clock quality check is shown in figure 7-18 . figure 7-18. sequence for clock quality check note remember that in parallel to additional actions caused by self clock mode or clock monitor reset 7 handling the clock quality checker continues to check the oscclk signal. note the clock quality checker enables the ipll and the voltage regulator (vreg) anytime a clock check has to be performed. an ongoing clock quality check could also cause a running ipll (f scm ) and an active vreg during pseudo stop mode. 7. a clock monitor reset will always set the scme bit to logical?? check window osc ok ? scm active? switch to oscclk exit scm clock ok num = 50 num > 0 ? num = num-1 yes no yes scme = 1 ? no enter scm scm active? yes clock monitor reset no yes no num = 0 yes no por exit full stop cm fail lvr scme=1 & ? fstwkp=1 yes no ? fstwkp = 0 no num = 0 enter scm yes
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 281 7.4.1.5 computer operating properly watchdog (cop) the cop (free running watchdog timer) enables the user to check that a program is running and sequencing properly. when the cop is being used, software is responsible for keeping the cop from timing out. if the cop times out it is an indication that the software is no longer being executed in the intended sequence; thus a system reset is initiated (see section 7.4.1.5, ?omputer operating properly watchdog (cop) ). the cop runs with a gated oscclk. three control bits in the copctl register allow selection of seven cop time-out periods. when cop is enabled, the program must write $55 and $aa (in this order) to the armcop register during the selected time-out period. once this is done, the cop time-out period is restarted. if the program fails to do this and the cop times out, the part will reset. also, if any value other than $55 or $aa is written, the part is immediately reset. windowed cop operation is enabled by setting wcop in the copctl register. in this mode, writes to the armcop register to clear the cop timer must occur in the last 25% of the selected time-out period. a premature write will immediately reset the part. if pce bit is set, the cop will continue to run in pseudo stop mode. 7.4.1.6 real time interrupt (rti) the rti can be used to generate a hardware interrupt at a ?ed periodic rate. if enabled (by setting rtie=1), this interrupt will occur at the rate selected by the rtictl register. the rti runs with a gated oscclk. at the end of the rti time-out period the rtif ?g is set to one and a new rti time-out period starts immediately. a write to the rtictl register restarts the rti time-out period. if the pre bit is set, the rti will continue to run in pseudo stop mode. 7.4.2 operation modes 7.4.2.1 normal mode the s12xecrg block behaves as described within this speci?ation in all normal modes. 7.4.2.2 self clock mode if the external clock frequency is not available due to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the pllclk running at self clock mode frequency f scm ; this mode of operation is called self clock mode. this requires cme = 1 and scme = 1, which is the default after reset. if the mcu was clocked by the pllclk prior to entering self clock mode, the pllsel bit will be cleared. if the external clock signal has stabilized again, the s12xecrg will automatically select oscclk to be the system clock and return to normal mode. see section 7.4.1.4, ?lock quality checker for more information on entering and leaving self clock mode.
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 282 freescale semiconductor note in order to detect a potential clock loss the cme bit should always be enabled (cme = 1). if cme bit is disabled and the mcu is con?ured to run on pllclk, a loss of external clock (oscclk) will not be detected and will cause the system clock to drift towards lower frequencies. as soon as the external clock is available again the system clock ramps up to its ipll target frequency. if the mcu is running on external clock any loss of clock will cause the system to go static. 7.4.3 low power options this section summarizes the low power options available in the s12xecrg. 7.4.3.1 run mode this is the default mode after reset. the rti can be stopped by setting the associated rate select bits to zero. the cop can be stopped by setting the associated rate select bits to zero. 7.4.3.2 wait mode the wai instruction puts the mcu in a low power consumption stand-by mode depending on setting of the individual bits in the clksel register. all individual wait mode con?uration bits can be superposed. this provides enhanced granularity in reducing the level of power consumption during wait mode. table 7-15 lists the individual con?uration bits and the parts of the mcu that are affected in wait mode. after executing the wai instruction the core requests the s12xecrg to switch mcu into wait mode. the s12xecrg then checks whether the pllwai bit is asserted. depending on the con?uration the s12xecrg switches the system and core clocks to oscclk by clearing the pllsel bit and disables the ipll. there are two ways to restart the mcu from wait mode: 1. any reset 2. any interrupt table 7-15. mcu con?uration during wait mode pllwai rtiwai copwai ipll stopped rti stopped cop stopped
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 283 7.4.3.3 stop mode all clocks are stopped in stop mode, dependent of the setting of the pce, pre, lcd enable (see documentation of lcd module) and pstp bit. the oscillator is disabled in stop mode unless the pstp bit is set. if the pre or pce bits are set, the rti or cop continues to run in pseudo stop mode. in addition to disabling system and core clocks the s12xecrg requests other functional units of the mcu (e.g. voltage-regulator) to enter their individual power saving modes (if available). if the pllsel bit is still set when entering stop mode, the s12xecrg will switch the system and core clocks to oscclk by clearing the pllsel bit. then the s12xecrg disables the ipll, disables the core clock and ?ally disables the remaining system clocks. if pseudo stop mode is entered from self-clock mode the s12xecrg will continue to check the clock quality until clock check is successful. in this case the ipll and the voltage regulator (vreg) will remain enabled. if full stop mode (pstp = 0) is entered from self-clock mode the ongoing clock quality check will be stopped. a complete timeout window check will be started when stop mode is left again. there are two ways to restart the mcu from stop mode: 1. any reset 2. any interrupt if the mcu is woken-up from full stop mode by an interrupt and the fast wake-up feature is enabled (fstwkp=1 and scme=1), the system will immediately (no clock quality check) resume operation in self-clock mode (see section 7.4.1.4, ?lock quality checker ). the scmif ?g will not be set for this special case. the system will remain in self-clock mode with oscillator disabled until fstwkp bit is cleared. the clearing of fstwkp will start the oscillator and the clock quality check. if the clock quality check is successful, the s12xecrg will switch all system clocks to oscillator clock. the scmif ?g will be set. see application examples in figure 7-19 and figure 7-20 . because the ipll has been powered-down during stop mode the pllsel bit is cleared and the mcu runs on oscclk after leaving stop-mode. the software must manually set the pllsel bit again, in order to switch system and core clocks to the pllclk. note in full stop mode or self-clock mode caused by the fast wake-up feature the clock monitor and the oscillator are disabled.
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 284 freescale semiconductor figure 7-19. fast wake-up from full stop mode: example 1 . figure 7-20. fast wake-up from full stop mode: example 2 7.5 resets all reset sources are listed in table 7-16 . refer to mcu speci?ation for related vector addresses and priorities. table 7-16. reset summary reset source local enable power on reset none low voltage reset none external reset none illegal address reset none clock monitor reset pllctl (cme=1, scme=0) oscillator clock pll clock core clock instruction stop irq service fstwkp=1 irq service stop stop irq service oscillator disabled power saving self-clock mode scme=1 cpu resumes program execution immediately interrupt interrupt interrupt oscillator clock pll clock core clock instruction clock quality check stop irq service fstwkp=1 irq interrupt fstwkp=0 scmie=1 osc startup oscillator disabled cpu resumes program execution immediately self-clock mode scme=1 frequent uncritical instructions frequent critical instructions possible scm interrupt
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 285 7.5.1 description of reset operation the reset sequence is initiated by any of the following events: low level is detected at the reset pin (external reset). power on is detected. low voltage is detected. illegal address reset is detected (see s12xmmc block guide for details). cop watchdog times out. clock monitor failure is detected and self-clock mode was disabled (scme=0). upon detection of any reset event, an internal circuit drives the reset pin low for 128 sysclk cycles (see figure 7-21 ). since entry into reset is asynchronous it does not require a running sysclk. however, the internal reset circuit of the s12xecrg cannot sequence out of current reset condition without a running sysclk. the number of 128 sysclk cycles might be increased by n = 3 to 6 additional sysclk cycles depending on the internal synchronization latency. after 128+n sysclk cycles the reset pin is released. the reset generator of the s12xecrg waits for additional 64 sysclk cycles and then samples the reset pin to determine the originating source. table 7-17 shows which vector will be fetched. note external circuitry connected to the reset pin should be able to raise the signal to a valid logic one within 64 sysclk cycles after the low drive is released by the mcu. if this requirement is not adhered to the reset source will always be recognized as ?xternal reset even if the reset was initially caused by an other reset source. cop watchdog reset copctl (cr[2:0] nonzero) table 7-17. reset vector selection sampled reset pin (64 cycles after release) clock monitor reset pending cop reset pending vector fetch 1 0 0 por / lvr / illegal address reset/ external reset 1 1 x clock monitor reset 1 0 1 cop reset 0 x x por / lvr / illegal address reset/ external reset with rise of reset pin table 7-16. reset summary reset source local enable
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 286 freescale semiconductor the internal reset of the mcu remains asserted while the reset generator completes the 192 sysclk long reset sequence. in case the reset pin is externally driven low for more than these 192 sysclk cycles (external reset), the internal reset remains asserted longer. figure 7-21. reset timing 7.5.1.1 clock monitor reset the s12xecrg generates a clock monitor reset in case all of the following conditions are true: clock monitor is enabled (cme = 1) loss of clock is detected self-clock mode is disabled (scme = 0). the reset event asynchronously forces the con?uration registers to their default settings. in detail the cme and the scme are reset to logical ? (which changes the state of the scme bit. as a consequence the s12xecrg immediately enters self clock mode and starts its internal reset sequence. in parallel the clock quality check starts. as soon as clock quality check indicates a valid oscillator clock the s12xecrg switches to oscclk and leaves self clock mode. since the clock quality checker is running in parallel to the reset generator, the s12xecrg may leave self clock mode while still completing the internal reset sequence. 7.5.1.2 computer operating properly watchdog (cop) reset when cop is enabled, the s12xecrg expects sequential write of $55 and $aa (in this order) to the armcop register during the selected time-out period. once this is done, the cop time-out period restarts. if the program fails to do this the s12xecrg will generate a reset. 7.5.1.3 power on reset, low voltage reset the on-chip voltage regulator detects when v dd to the mcu has reached a certain level and asserts power on reset or low voltage reset or both. as soon as a power on reset or low voltage reset is triggered the ) ( ) ( ) ( ) sysclk 128+ n cycles 64 cycles with n being min 3 / max 6 cycles depending on internal synchronization delay icrg drives reset pin low possibly sysclk not running possibly reset driven low externally ) ( ( reset reset pin released
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 287 s12xecrg performs a quality check on the incoming clock signal. as soon as clock quality check indicates a valid oscillator clock signal the reset sequence starts using the oscillator clock. if after 50 check windows the clock quality check indicated a non-valid oscillator clock the reset sequence starts using self-clock mode. figure 7-22 and figure 7-23 show the power-up sequence for cases when the reset pin is tied to v dd and when the reset pin is held low. figure 7-22. reset pin tied to v dd (by a pull-up resistor) figure 7-23. reset pin held low externally 7.6 interrupts the interrupts/reset vectors requested by the s12xecrg are listed in table 7-18 . refer to mcu speci?ation for related vector addresses and priorities. table 7-18. s12xecrg interrupt vectors interrupt source ccr mask local enable real time interrupt i bit crgint (rtie) lock interrupt i bit crgint (lockie) scm interrupt i bit crgint (scmie) reset internal por 128 sysclk 64 sysclk internal reset clock quality check (no self-clock mode) ) ( ) ( ) ( clock quality check reset internal por internal reset 128 sysclk 64 sysclk (no self clock mode) ) ( ) ( ) (
s12xe clocks and reset generator (s12xecrgv2) mc9s12xhy-family reference manual, rev. 1.01 288 freescale semiconductor 7.6.1 description of interrupt operation 7.6.1.1 real time interrupt the s12xecrg generates a real time interrupt when the selected interrupt time period elapses. rti interrupts are locally disabled by setting the rtie bit to zero. the real time interrupt ?g (rtif) is set to1 when a timeout occurs, and is cleared to 0 by writing a 1 to the rtif bit. the rti continues to run during pseudo stop mode if the pre bit is set to 1. this feature can be used for periodic wakeup from pseudo stop if the rti interrupt is enabled. 7.6.1.2 ipll lock interrupt the s12xecrg generates a ipll lock interrupt when the lock condition of the ipll has changed, either from a locked state to an unlocked state or vice versa. lock interrupts are locally disabled by setting the lockie bit to zero. the ipll lock interrupt ?g (lockif) is set to1 when the lock condition has changed, and is cleared to 0 by writing a 1 to the lockif bit. 7.6.1.3 self clock mode interrupt the s12xecrg generates a self clock mode interrupt when the scm condition of the system has changed, either entered or exited self clock mode. scm conditions are caused by a failing clock quality check after power on reset (por) or low voltage reset (lvr) or recovery from full stop mode (pstp = 0) or clock monitor failure. for details on the clock quality check refer to section 7.4.1.4, ?lock quality checker . if the clock monitor is enabled (cme = 1) a loss of external clock will also cause a scm condition (scme = 1). scm interrupts are locally disabled by setting the scmie bit to zero. the scm interrupt ?g (scmif) is set to1 when the scm condition has changed, and is cleared to 0 by writing a 1 to the scmif bit.
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 289 chapter 8 pierce oscillator (s12xosclcpv2) 8.1 introduction the pierce oscillator (xosc) module provides a robust, low-noise and low-power clock source. the module will be operated from the v ddpll supply rail (1.8 v nominal) and require the minimum number of external components. it is designed for optimal start-up margin with typical crystal oscillators. 8.1.1 features the xosc will contain circuitry to dynamically control current gain in the output amplitude. this ensures a signal with low harmonic distortion, low power and good noise immunity. high noise immunity due to input hysteresis low rf emissions with peak-to-peak swing limited dynamically transconductance (gm) sized for optimum start-up margin for typical oscillators dynamic gain control eliminates the need for external current limiting resistor integrated resistor eliminates the need for external bias resistor in loop controlled pierce mode. low power consumption: operates from 1.8 v (nominal) supply amplitude control limits power clock monitor 8.1.2 modes of operation two modes of operation exist: 1. loop controlled pierce (lcp) oscillator 2. external square wave mode featuring also full swing pierce (fsp) without internal bias resistor the oscillator mode selection is described in the device overview section, subsection oscillator con?uration. table 8-1. revision history revision number revision date sections affected description of changes v01.05 19 jul 2006 - all xclks info was removed v02.00 04 aug 2006 - incremented revision to match the design system spec revision
pierce oscillator (s12xosclcpv2) mc9s12xhy-family reference manual, rev. 1.01 290 freescale semiconductor 8.1.3 block diagram figure 8-1 shows a block diagram of the xosc. figure 8-1. xosc block diagram 8.2 external signal description this section lists and describes the signals that connect off chip 8.2.1 vddpll and vsspll ?operating and ground voltage pins theses pins provides operating voltage (v ddpll ) and ground (v sspll ) for the xosc circuitry. this allows the supply voltage to the xosc to use an independent bypass capacitor. 8.2.2 extal and xtal ?input and output pins these pins provide the interface for either a crystal or a 1.8v cmos compatible clock to control the internal clock generator circuitry. extal is the external clock input or the input to the crystal oscillator ampli?r. xtal is the output of the crystal oscillator ampli?r. the mcu internal system clock is derived extal xtal gain control v ddpll = 1.8 v rf oscclk monitor_failure clock monitor peak detector
pierce oscillator (s12xosclcpv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 291 from the extal input frequency. in full stop mode (pstp = 0), the extal pin is pulled down by an internal resistor of typical 200 k ? . note freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. loop controlled circuit is not suited for overtone resonators and crystals. figure 8-2. loop controlled pierce oscillator connections (lcp mode selected) note full swing pierce circuit is not suited for overtone resonators and crystals without a careful component selection. figure 8-3. full swing pierce oscillator connections (fsp mode selected) figure 8-4. external clock connections (fsp mode selected) mcu extal xtal v sspll crystal or ceramic resonator c2 c1 * r s can be zero (shorted) when use with higher frequency crystals. refer to manufacturer? data. mcu extal xtal rs* rb v sspll crystal or ceramic resonator c2 c1 mcu extal xtal not connected cmos compatible external oscillator (v ddpll level)
pierce oscillator (s12xosclcpv2) mc9s12xhy-family reference manual, rev. 1.01 292 freescale semiconductor 8.3 memory map and register de?ition the crg contains the registers and associated bits for controlling and monitoring the oscillator module. 8.4 functional description the xosc module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal level which is determined by the amount of hysteresis being used and the maximum oscillation range. the oscillator block has two external pins, extal and xtal. the oscillator input pin, extal, is intended to be connected to either a crystal or an external clock source. the xtal pin is an output signal that provides crystal circuit feedback. a buffered extal signal becomes the internal clock. to improve noise immunity, the oscillator is powered by the vddpll and vsspll power supply pins. 8.4.1 gain control in lcp mode a closed loop control system will be utilized whereby the ampli?r is modulated to keep the output waveform sinusoidal and to limit the oscillation amplitude. the output peak to peak voltage will be kept above twice the maximum hysteresis level of the input buffer. electrical speci?ation details are provided in the electrical characteristics appendix. 8.4.2 clock monitor the clock monitor circuit is based on an internal rc time delay so that it can operate without any mcu clocks. if no oscclk edges are detected within this rc time delay, the clock monitor indicates failure which asserts self-clock mode or generates a system reset depending on the state of scme bit. if the clock monitor is disabled or the presence of clocks is detected no failure is indicated.the clock monitor function is enabled/disabled by the cme control bit, described in the crg block description chapter. 8.4.3 wait mode operation during wait mode, xosc is not impacted. 8.4.4 stop mode operation xosc is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled. during pseudo-stop mode, xosc is not impacted.
pierce oscillator (s12xosclcpv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 293
pierce oscillator (s12xosclcpv2) mc9s12xhy-family reference manual, rev. 1.01 294 freescale semiconductor
pierce oscillator (s12xosclcpv2) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 295
pierce oscillator (s12xosclcpv2) mc9s12xhy-family reference manual, rev. 1.01 296 freescale semiconductor
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 297 chapter 9 voltage regulator (s12vregl3v3v1) table 9-1. revision history table 9.1 introduction module vreg_3v3 is a tri output voltage regulator that provides two separate 1.84v (typical) supplies differing in the amount of current that can be sourced and a 2.82v (typical) supply. the regulator input voltage range is from 3.3v up to 5v (typical). 9.1.1 features module vreg_3v3 includes these distinctive features: three parallel, linear voltage regulators with bandgap reference low-voltage detect (lvd) with low-voltage interrupt (lvi) power-on reset (por) low-voltage reset (lvr) high temperature detect (htd) with high temperature interrupt (hti) autonomous periodical interrupt (api) 9.1.2 modes of operation there are three modes vreg_3v3 can operate in: 1. full performance mode (fpm) (mcu is not in stop mode) the regulator is active, providing the nominal supply voltages with full current sourcing capability. features lvd (low-voltage detect), lvr (low-voltage reset), and por (power-on reset) and htd (high temperature detect) are available. the api is available. 2. reduced power mode (rpm) (mcu is in stop mode) the purpose is to reduce power consumption of the device. the output voltage may degrade to a lower value than in full performance mode, additionally the current sourcing capability is substantially reduced. only the por is available in this mode, lvd, lvr and htd are disabled. the api is available. rev. no. (item no.) date (submitted by) sections affected substantial change(s) v01.02 09 sep 2005 updates for api external access and lvr ?gs. v01.03 23 sep 2005 vae reset value is 1. v01.04 08 jun 2007 added temperature sensor to customer information
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual, rev. 1.01 298 freescale semiconductor 3. shutdown mode controlled by vregen (see device level speci?ation for connectivity of vregen). this mode is characterized by minimum power consumption. the regulator outputs are in a high-impedance state, only the por feature is available, lvd, lvr and htd are disabled. the api internal rc oscillator clock is not available. this mode must be used to disable the chip internal regulator vreg_3v3, i.e., to bypass the vreg_3v3 to use external supplies. 9.1.3 block diagram figure 9-1 shows the function principle of vreg_3v3 by means of a block diagram. the regulator core reg consists of three parallel subblocks, reg1, reg2 and reg3, providing three independent output voltages.
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 299 figure 9-1. vreg_3v3 block diagram lv r lv d por vddr vdd lvi por lvr ctrl vss vddpll vsspll vregen reg pin vdda reg: regulator core ctrl: regulator control lvd: low voltage detect lvr: low voltage reset por: power-on reset htd: high temperature detect c hti htd api api api: auto. periodical interrupt v bg api rate select bus clock reg2 reg1 reg3 vddf vssa vddx
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual, rev. 1.01 300 freescale semiconductor 9.2 external signal description due to the nature of vreg_3v3 being a voltage regulator providing the chip internal power supply voltages, most signals are power supply signals connected to pads. table 9-2 shows all signals of vreg_3v3 associated with pins. note check device level speci?ation for connectivity of the signals. 9.2.1 vddr ?regulator power input pins signal vddr is the power input of vreg_3v3. all currents sourced into the regulator loads ?w through this pin. a chip external decoupling capacitor (100 nf...220 nf, x7r ceramic) between vddr and vssr (if vssr is not available vss) can smooth ripple on vddr. for entering shutdown mode, pin vddr should also be tied to ground on devices without vregen pin. 9.2.2 vdda, vssa ?regulator reference supply pins signals vdda/vssa , which are supposed to be relatively quiet, are used to supply the analog parts of the regulator. internal precision reference circuits are supplied from these signals. a chip external decoupling capacitor (100 nf...220 nf, x7r ceramic) between vdda and vssa can further improve the quality of this supply. 9.2.3 vdd, vss ?regulator output1 (core logic) pins signals vdd/vss are the primary outputs of vreg_3v3 that provide the power supply for the core logic. these signals are connected to device pins to allow external decoupling capacitors (220 nf, x7r ceramic). table 9-2. signal properties name function reset state pull up vddr power input (positive supply) vdda quiet input (positive supply) vssa quiet input (ground) vddx power input (positive supply) vdd primary output (positive supply) vss primary output (ground) vddf secondary output (positive supply) vddpll tertiary output (positive supply) vsspll tertiary output (ground) vregen (optional) optional regulator enable vreg_api (optional) vreg autonomous periodical interrupt output
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 301 in shutdown mode an external supply driving vdd/vss can replace the voltage regulator. 9.2.4 vddf ?regulator output2 (nvm logic) pins signals vddf/vss are the secondary outputs of vreg_3v3 that provide the power supply for the nvm logic. these signals are connected to device pins to allow external decoupling capacitors (220 nf, x7r ceramic). in shutdown mode an external supply driving vddf/vss can replace the voltage regulator. 9.2.5 vddpll, vsspll ?regulator output3 (pll) pins signals vddpll/vsspll are the secondary outputs of vreg_3v3 that provide the power supply for the pll and oscillator. these signals are connected to device pins to allow external decoupling capacitors (100 nf...220 nf, x7r ceramic). in shutdown mode, an external supply driving vddpll/vsspll can replace the voltage regulator. 9.2.6 vddx ?power input pin signals vddx/vss are monitored by vreg_3v3 with the lvr feature. 9.2.7 vregen optional regulator enable pin this optional signal is used to shutdown vreg_3v3. in that case, vdd/vss and vddpll/vsspll must be provided externally. shutdown mode is entered with vregen being low. if vregen is high, the vreg_3v3 is either in full performance mode or in reduced power mode. for the connectivity of vregen, see device speci?ation. note switching from fpm or rpm to shutdown of vreg_3v3 and vice versa is not supported while mcu is powered. 9.2.8 vreg_api optional autonomous periodical interrupt output pin this pin provides the signal selected via apiea if system is set accordingly. see 9.3.2.3, autonomous periodical interrupt control register (vregapicl) and 9.4.8, autonomous periodical interrupt (api) for details. for the connectivity of vreg_api, see device speci?ation. 9.3 memory map and register de?ition this section provides a detailed description of all registers accessible in vreg_3v3. if enabled in the system, the vreg_3v3 will abort all read and write accesses to reserved registers within its memory slice. see device level speci?ation for details.
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual, rev. 1.01 302 freescale semiconductor 9.3.1 module memory map a summary of the registers associated with the vreg_3v3 sub-block is shown in table 9-3 . detailed descriptions of the registers and bits are given in the subsections that follow address name bit 7 6 54321 bit 0 0x02f0 vreghtcl r0 0 vsel vae hten htds htie htif w 0x02f1 vregctrl r00000lvds lvie lvif w 0x02f2 vregapic l r apiclk 00 apifes apiea apife apie apif w 0x02f3 vregapit r r apitr5 apitr4 apitr3 apitr2 apitr1 apitr0 00 w 0x02f4 vregapir h r apir15 apir14 apir13 apir12 apir11 apir10 apir9 apir8 w 0x02f5 vregapir l r apir7 apir6 apir5 apir4 apir3 apir2 apir1 apir0 w 0x02f6 reserved 06 r00000000 w 0x02f7 vreghttr r htoen 000 httr3 httr2 httr1 httr0 w table 9-3. register summary
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 303 9.3.2 register descriptions this section describes all the vreg_3v3 registers and their individual bits. 9.3.2.1 h igh t emperature control register (vreghtcl) the vreghtcl register allows to con?ure the vreg temperature sense features. 0x02f0 76543210 r0 0 vsel vae hten htds htie htif w reset 0 0 0 10000 = unimplemented or reserved table 9-4. vreghtcl field descriptions field description 7, 6 reserved these reserved bits are used for test purposes and writable only in special modes. they must remain clear for correct temperature sensor operation. 5 vsel voltage access select bit ?if set, the bandgap reference voltage v bg can be accessed internally (i.e. multiplexed to an internal analog to digital converter channel). the internal access must be enabled by bit vae. see device level speci?ation for connectivity. 0 an internal temperature proportional voltage v ht can be accessed internally if vae is set. 1 bandgap reference voltage v bg can be accessed internally if vae is set. 4 vae voltage access enable bit ?if set, the voltage selected by bit vsel can be accessed internally (i.e. multiplexed to an internal analog to digital converter channel). see device level speci?ation for connectivity. 0 voltage selected by vsel can not be accessed internally (i.e. external analog input is connected to analog to digital converter channel). 1 voltage selected by vsel can be accessed internally. 3 hten high temperature enable bit ?if set the temperature sense is enabled. 0 the temperature sense is disabled. 1 the temperature sense is enabled. 2 htds high temperature detect status bit this read-only status bit re?cts the temperature status. writes have no effect. 0 temperature t die is below level t htid or rpm or shutdown mode. 1 temperature t die is above level t htia and fpm. 1 htie high temperature interrupt enable bit 0 interrupt request is disabled. 1 interrupt will be requested whenever htif is set. 0 htif high temperature interrupt flag ?htif ?high temperature interrupt flag htif is set to 1 when htds status bit changes. this ?g can only be cleared by writing a 1.}writing a 0 has no effect. if enabled (htie=1), htif causes an interrupt request. 0 no change in htds bit. 1 htds bit has changed. note: on entering the reduced power mode the htif is not cleared by the vreg.
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual, rev. 1.01 304 freescale semiconductor 9.3.2.2 control register (vregctrl) the vregctrl register allows the con?uration of the vreg_3v3 low-voltage detect features. 0x02f1 76543210 r00000lvds lvie lvif w reset 0 0 0 00000 = unimplemented or reserved figure 9-2. control register (vregctrl) table 9-5. vregctrl field descriptions field description 2 lvds low-voltage detect status bit ?this read-only status bit re?cts the input voltage. writes have no effect. 0 input voltage v dda is above level v lvid or rpm or shutdown mode. 1 input voltage v dda is below level v lvia and fpm. 1 lvie low-voltage interrupt enable bit 0 interrupt request is disabled. 1 interrupt will be requested whenever lvif is set. 0 lvif low-voltage interrupt flag lvif is set to 1 when lvds status bit changes. this ?g can only be cleared by writing a 1. writing a 0 has no effect. if enabled (lvie = 1), lvif causes an interrupt request. 0 no change in lvds bit. 1 lvds bit has changed. note: on entering the reduced power mode the lvif is not cleared by the vreg_3v3.
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 305 9.3.2.3 autonomous periodical interrupt control register (vregapicl) the vregapicl register allows the con?uration of the vreg_3v3 autonomous periodical interrupt features. 0x02f2 76543210 r apiclk 00 apies apiea apife apie apif w reset 0 0 0 00000 = unimplemented or reserved figure 9-3. autonomous periodical interrupt control register (vregapicl) table 9-6. vregapicl field descriptions field description 7 apiclk autonomous periodical interrupt clock select bit ?selects the clock source for the api. writable only if apife = 0; apiclk cannot be changed if apife is set by the same write operation. 0 autonomous periodical interrupt clock used as source. 1 bus clock used as source. 4 apies autonomous periodical interrupt external select bit selects the waveform at the external pin.if set, at the external pin a clock is visible with 2 times the selected api period ( table 9-10 ). if not set, at the external pin will be a high pulse at the end of every selected period with the size of half of the min period ( table 9-10 ). see device level speci?ation for connectivity. 0 at the external periodic high pulses are visible, if apiea and apife is set. 1 at the external pin a clock is visible, if apiea and apife is set. 3 apiea autonomous periodical interrupt external access enable bit if set, the waveform selected by bit apies can be accessed externally. see device level speci?ation for connectivity. 0 waveform selected by apies can not be accessed externally. 1 waveform selected by apies can be accessed externally, if apife is set. 2 apife autonomous periodical interrupt feature enable bit ?enables the api feature and starts the api timer when set. 0 autonomous periodical interrupt is disabled. 1 autonomous periodical interrupt is enabled and timer starts running. 1 apie autonomous periodical interrupt enable bit 0 api interrupt request is disabled. 1 api interrupt will be requested whenever apif is set. 0 apif autonomous periodical interrupt flag ?apif is set to 1 when the in the api con?ured time has elapsed. this ?g can only be cleared by writing a 1 to it. clearing of the ?g has precedence over setting. writing a 0 has no effect. if enabled (apie = 1), apif causes an interrupt request. 0 api timeout has not yet occurred. 1 api timeout has occurred.
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual, rev. 1.01 306 freescale semiconductor 9.3.2.4 autonomous periodical interrupt trimming register (vregapitr) the vregapitr register allows to trim the api timeout period. 0x02f3 76543210 r apitr5 apitr4 apitr3 apitr2 apitr1 apitr0 00 w reset 0 1 0 1 0 1 0 1 0 1 0 1 00 1. reset value is either 0 or preset by factory. see section 1 (device overview) for details. = unimplemented or reserved figure 9-4. autonomous periodical interrupt trimming register (vregapitr) table 9-7. vregapitr field descriptions field description 7? apitr[5:0] autonomous periodical interrupt period trimming bits ?see table 9-8 for trimming effects. table 9-8. trimming effect of apit bit trimming effect apitr[5] increases period apitr[4] decreases period less than apitr[5] increased it apitr[3] decreases period less than apitr[4] apitr[2] decreases period less than apitr[3] apitr[1] decreases period less than apitr[2] apitr[0] decreases period less than apitr[1]
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 307 9.3.2.5 autonomous periodical interrupt rate high and low register (vregapirh / vregapirl) the vregapirh and vregapirl register allows the con?uration of the vreg_3v3 autonomous periodical interrupt rate. 0x02f4 76543210 r apir15 apir14 apir13 apir12 apir11 apir10 apir9 apir8 w reset 0 0 0 00000 = unimplemented or reserved figure 9-5. autonomous periodical interrupt rate high register (vregapirh) 0x02f5 76543210 r apir7 apir6 apir5 apir4 apir3 apir2 apir1 apir0 w reset 0 0 0 00000 figure 9-6. autonomous periodical interrupt rate low register (vregapirl) table 9-9. vregapirh / vregapirl field descriptions field description 15-0 apir[15:0] autonomous periodical interrupt rate bits these bits de?e the timeout period of the api. see table 9-10 for details of the effect of the autonomous periodical interrupt rate bits. writable only if apife = 0 of vregapicl register.
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual, rev. 1.01 308 freescale semiconductor the period can be calculated as follows depending of apiclk: period = 2*(apir[15:0] + 1) * 0.1 ms or period = 2*(apir[15:0] + 1) * bus clock period table 9-10. selectable autonomous periodical interrupt periods apiclk apir[15:0] selected period 0 0000 0.2 ms 1 1 when trimmed within speci?d accuracy. see electrical speci?ations for details. 0 0001 0.4 ms 1 0 0002 0.6 ms 1 0 0003 0.8 ms 1 0 0004 1.0 ms 1 0 0005 1.2 ms 1 0 ..... ..... 0 fffd 13106.8 ms 1 0 fffe 13107.0 ms 1 0 ffff 13107.2 ms 1 1 0000 2 * bus clock period 1 0001 4 * bus clock period 1 0002 6 * bus clock period 1 0003 8 * bus clock period 1 0004 10 * bus clock period 1 0005 12 * bus clock period 1 ..... ..... 1 fffd 131068 * bus clock period 1 fffe 131070 * bus clock period 1 ffff 131072 * bus clock period
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 309 9.3.2.6 reserved 06 the reserved 06 is reserved for test purposes. 9.3.2.7 high temperature trimming register (vreghttr) the vreghttr register allows to trim the vreg temperature sense. fiption table 9-12. trimming effect 0x02f6 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 9-7. reserved 06 0x02f7 76543210 r htoen 000 httr3 httr2 httr1 httr0 w reset 0 0 0 0 0 1 0 1 0 1 0 1 1. reset value is either 0 or preset by factory. see section 1 (device overview) for details. = unimplemented or reserved figure 9-8. vreghttr table 9-11. vreghttr ?ld descriptions field description 7 htoen high temperature offset enable bit ?if set the temperature sense offset is enabled 0 the temperature sense offset is disabled 1 the temperature sense offset is enabled 3? httr[3:0] high temperature trimming bits ?see table 23-16 for trimming effects. bit trimming effect httr[3] increases v ht twice of httr[2] httr[2] increases v ht twice of httr[1] httr[1] increases v ht twice of httr[0] httr[0] increases v ht (to compensate temperature offset)
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual, rev. 1.01 310 freescale semiconductor 9.4 functional description 9.4.1 general module vreg_3v3 is a voltage regulator, as depicted in figure 9-1 . the regulator functional elements are the regulator core (reg), a low-voltage detect module (lvd), a control block (ctrl), a power-on reset module (por), and a low-voltage reset module (lvr)and a high temperature sensor (htd). 9.4.2 regulator core (reg) respectively its regulator core has three parallel, independent regulation loops (reg1,reg2 and reg3). reg1 and reg3 differ only in the amount of current that can be delivered. the regulators are linear regulator with a bandgap reference when operated in full performance mode. they act as a voltage clamp in reduced power mode. all load currents ?w from input vddr to vss or vsspll. the reference circuits are supplied by vdda and vssa. 9.4.2.1 full performance mode in full performance mode, the output voltage is compared with a reference voltage by an operational ampli?r. the ampli?d input voltage difference drives the gate of an output transistor. 9.4.2.2 reduced power mode in reduced power mode, the gate of the output transistor is connected directly to a reference voltage to reduce power consumption. mode switching from reduced power to full performance requires a transition time of t vup , if the voltage regulator is enabled. 9.4.3 low-voltage detect (lvd) subblock lvd is responsible for generating the low-voltage interrupt (lvi). lvd monitors the input voltage (v dda ? ssa ) and continuously updates the status ?g lvds. interrupt ?g lvif is set whenever status ?g lvds changes its value. the lvd is available in fpm and is inactive in reduced power mode or shutdown mode. 9.4.4 power-on reset (por) this functional block monitors vdd. if v dd is below v pord , por is asserted; if v dd exceeds v pord , the por is deasserted. por asserted forces the mcu into reset. por deasserted will trigger the power-on sequence. 9.4.5 low-voltage reset (lvr) block lvr monitors the supplies vdd, vddx and vddf. if one (or more) drops below its corresponding assertion level, signal lvr asserts; if all vdd,vddx and vddf supplies are above their
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 311 corresponding deassertion levels, signal lvr deasserts. the lvr function is available only in full performance mode. 9.4.6 htd - high temperature detect subblock htd is responsible for generating the high temperature interrupt (hti). htd monitors the die temperature t die and continuously updates the status ?g htds. interrupt ?g htif is set whenever status ?g htds changes its value. the htd is available in fpm and is inactive in reduced power mode and shutdown mode. the ht trimming bits httr[3:0] can be set so that the temperature offset is zero, if accurate temperature measurement is desired. see table 23-16 for the trimming effect of apitr. 9.4.7 regulator control (ctrl) this part contains the register block of vreg_3v3 and further digital functionality needed to control the operating modes. ctrl also represents the interface to the digital core logic. 9.4.8 autonomous periodical interrupt (api) subblock api can generate periodical interrupts independent of the clock source of the mcu. to enable the timer, the bit apife needs to be set. the api timer is either clocked by a trimmable internal rc oscillator or the bus clock. timer operation will freeze when mcu clock source is selected and bus clock is turned off. see crg speci?ation for details. the clock source can be selected with bit apiclk. apiclk can only be written when apife is not set. the apir[15:0] bits determine the interrupt period. apir[15:0] can only be written when apife is cleared. as soon as apife is set, the timer starts running for the period selected by apir[15:0] bits. when the con?ured time has elapsed, the ?g apif is set. an interrupt, indicated by ?g apif = 1, is triggered if interrupt enable bit apie = 1. the timer is started automatically again after it has set apif. the procedure to change apiclk or apir[15:0] is ?st to clear apife, then write to apiclk or apir[15:0], and afterwards set apife. the api trimming bits apitr[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired. see table 9-8 for the trimming effect of apitr. note the ?st period after enabling the counter by apife might be reduced by api start up delay t sdel . the api internal rc oscillator clock is not available if vreg_3v3 is in shutdown mode.
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual, rev. 1.01 312 freescale semiconductor it is possible to generate with the api a waveform at an external pin by enabling the api by setting apife and enabling the external access with setting apiea. by setting apies the waveform can be selected. if apies is set, then at the external pin a clock is visible with 2 times the selected api period ( table 9-10 ). if apies is not set, then at the external pin will be a high pulse at the end of every selected period with the size of half of the min period ( table 9-10 ). see device level speci?ation for connectivity. 9.4.9 resets this section describes how vreg_3v3 controls the reset of the mcu.the reset values of registers and signals are provided in section 9.3, ?emory map and register de?ition . possible reset sources are listed in table 9-13 . 9.4.10 description of reset operation 9.4.10.1 power-on reset (por) during chip power-up the digital core may not work if its supply voltage v dd is below the por deassertion level (v pord ). therefore, signal por, which forces the other blocks of the device into reset, is kept high until v dd exceeds v pord . the mcu will run the start-up sequence after por deassertion. the power-on reset is active in all operation modes of vreg_3v3. 9.4.10.2 low-voltage reset (lvr) for details on low-voltage reset, see section 9.4.5, ?ow-voltage reset (lvr) . 9.4.11 interrupts this section describes all interrupts originated by vreg_3v3. the interrupt vectors requested by vreg_3v3 are listed in table 9-14 . vector addresses and interrupt priorities are de?ed at mcu level. table 9-13. reset sources reset source local enable power-on reset always active low-voltage reset available only in full performance mode table 9-14. interrupt vectors interrupt source local enable low-voltage interrupt (lvi) lvie = 1; available only in full performance mode high temperature interrupt (hti) htie=1; available only in full performance mode autonomous periodical interrupt (api) apie = 1
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 313 9.4.11.1 low-voltage interrupt (lvi) in fpm, vreg_3v3 monitors the input voltage v dda . whenever v dda drops below level v lvia, the status bit lvds is set to 1. on the other hand, lvds is reset to 0 when v dda rises above level v lvid .an interrupt, indicated by ?g lvif = 1, is triggered by any change of the status bit lvds if interrupt enable bit lvie = 1. note on entering the reduced power mode, the lvif is not cleared by the vreg_3v3. 9.4.11.2 hti - high temperature interrupt in fpm vreg monitors the die temperature t die . whenever t die exceeds level t htia the status bit htds is set to 1. vice versa, htds is reset to 0 when t die get below level t htid . an interrupt, indicated by ?g htif=1, is triggered by any change of the status bit htds if interrupt enable bit htie=1. note on entering the reduced power mode the htif is not cleared by the vreg. 9.4.11.3 autonomous periodical interrupt (api) as soon as the con?ured timeout period of the api has elapsed, the apif bit is set. an interrupt, indicated by ?g apif = 1, is triggered if interrupt enable bit apie = 1.
voltage regulator (s12vregl3v3v1) mc9s12xhy-family reference manual, rev. 1.01 314 freescale semiconductor
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 315 chapter 10 analog-to-digital converter (adc12b12cv1) block description revision history 10.1 introduction the adc12b12c is a 12-channel, 12-bit, multiplexed input successive approximation analog-to-digital converter. refer to device electrical speci?ations for atd accuracy. 10.1.1 features 8-, 10-, or 12-bit resolution. conversion in stop mode using internally generated clock automatic return to low power after conversion sequence automatic compare with interrupt for higher than or less/equal than programmable value programmable sample time. left/right justi?d result data. external trigger control. sequence complete interrupt. analog input multiplexer for 8 analog input channels. special conversions for v rh , v rl , (v rl +v rh )/2. version number revision date effective date author description of changes v01.00 25 july 2007 25 july 2007 initial version v01.01 14 sept 2007 14 sept 2007 added reserved registers at the end the memory map. v01.02 1 oct 2007 1 oct 2007 added following mention where applies: ( n conversion number, not channel number!) v01.03 9 oct 2007 9 oct 2007 modi?d table ?nalog input channel select coding?due to new customer feature (special17). v01.04 30 apr 2008 30 apr 2008 updated document for 8 channels. v01.05 1 oct 2008 1 oct 2008 updated document for 12 channels.
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 316 freescale semiconductor 1-to-12 conversion sequence lengths. continuous conversion mode. multiple channel scans. con?urable external trigger functionality on any ad channel or any of four additional trigger inputs. the four additional trigger inputs can be chip external or internal. refer to device speci?ation for availability and connectivity. con?urable location for channel wrap around (when converting multiple channels in a sequence).
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 317 10.1.2 modes of operation 10.1.2.1 conversion modes there is software programmable selection between performing single or continuous conversion on a single channel or multiple channels . 10.1.2.2 mcu operating modes stop mode iclkstp=0 (in atdctl2 register) entering stop mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode. this has the same effect/consequences as starting a conversion sequence with write to atdctl5. so after exiting from stop mode with a previously aborted sequence all ?gs are cleared etc. iclkstp=1 (in atdctl2 register) a/d conversion sequence seamless continues in stop mode based on the internally generated clock iclk as atd clock. for conversions during transition from run to stop mode or vice versa the result is not written to the results register, no ccf ?g is set and no compare is done. when converting in stop mode (iclkstp=1) an atd stop recovery time t atdstprcv is required to switch back to bus clock based atdclk when leaving stop mode. do not access atd registers during this time . wait mode adc12b12c behaves same in run and wait mode. for reduced power consumption continuous conversions should be aborted before entering wait mode. freeze mode in freeze mode the adc12b12c will either continue or ?ish or stop converting according to the frz1 and frz0 bits. this is useful for debugging and emulation.
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 318 freescale semiconductor 10.1.3 block diagram figure 10-1. adc12b12c block diagram v ssa an6 atd_12b12c analog mux mode and successive approximation register (sar) results atd 0 atd 1 atd 2 atd 3 atd 4 atd 5 atd 6 atd 7 and dac sample & hold v dda v rl v rh sequence complete + - comparator clock prescaler bus clock atd clock an5 an4 an3 an1 an0 an7 etrig0 (see device speci? cation for availability etrig1 etrig2 etrig3 and connectivity) timing control atddien atdctl1 trigger mux internal clock interrupt compare interrupt iclk an2 an8 an9 an10 an11 atd 8 atd 9 atd 10 atd 11
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 319 10.2 signal description this section lists all inputs to the adc12b12c block. 10.2.1 detailed signal descriptions 10.2.1.1 an x ( x = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) this pin serves as the analog input channel x . it can also be con?ured as digital port or external trigger for the atd conversion. 10.2.1.2 etrig3, etrig2, etrig1, etrig0 these inputs can be con?ured to serve as an external trigger for the atd conversion. refer to device speci?ation for availability and connection of these inputs! 10.2.1.3 v rh , v rl v rh is the high reference voltage, v rl is the low reference voltage for atd conversion. 10.2.1.4 v dda , v ssa these pins are the power supplies for the analog circuitry of the adc12b12c block. 10.3 memory map and register de?ition this section provides a detailed description of all registers accessible in the adc12b12c. 10.3.1 module memory map figure 10-2 gives an overview on all adc12b12c registers. note register address = base address + address offset, where the base address is de?ed at the mcu level and the address offset is de?ed at the module level. address name bit 7 6 5 4 3 2 1 bit 0 0x0000 atdctl0 r reserved 000 wrap3 wrap2 wrap1 wrap0 w 0x0001 atdctl1 r etrigsel sres1 sres0 smp_dis etrigch3 etrigch2 etrigch1 etrigch0 w 0x0002 atdctl2 r0 affc iclkstp etrigle etrigp etrige ascie acmpie w = unimplemented or reserved figure 10-2. adc12b12c register summary (sheet 1 of 3)
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 320 freescale semiconductor 0x0003 atdctl3 r djm s8c s4c s2c s1c fifo frz1 frz0 w 0x0004 atdctl4 r smp2 smp1 smp0 prs[4:0] w 0x0005 atdctl5 r0 sc scan mult cd cc cb ca w 0x0006 atdstat0 r scf 0 etorf fifor cc3 cc2 cc1 cc0 w 0x0007 unimple- mented r0 000 0 0 0 0 w 0x0008 atdcmpeh r0 000 cmpe[11:8] w 0x0009 atdcmpel r cmpe[7:0] w 0x000a atdstat2h r 0 0 0 0 ccf[11:8] w 0x000b atdstat2l r ccf[7:0] w 0x000c atddienh r0 000 ien[11:8] w 0x000d atddienl r ien[7:0] w 0x000e atdcmphth r0 000 cmpht[11:8] w 0x000f atdcmphtl r cmpht[7:0] w 0x0010 atddr0 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0012 atddr1 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0014 atddr2 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0016 atddr3 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0018 atddr4 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x001a atddr5 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x001c atddr6 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x001e atddr7 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0020 atddr8 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0022 atddr9 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w address name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 10-2. adc12b12c register summary (sheet 2 of 3)
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 321 0x0024 atddr10 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0026 atddr11 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0028 - 0x002f unimple- mented r 00000000 w address name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 10-2. adc12b12c register summary (sheet 3 of 3)
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 322 freescale semiconductor 10.3.2 register descriptions this section describes in address order all the adc12b12c registers and their individual bits. 10.3.2.1 atd control register 0 (atdctl0) writes to this register will abort current conversion sequence. read: anytime write: anytime, in special modes always write 0 to reserved bit 7. module base + 0x0000 76543210 r reserved 000 wrap3 wrap2 wrap1 wrap0 w reset 0 0 0 01111 = unimplemented or reserved figure 10-3. atd control register 0 (atdctl0) table 10-1. atdctl0 field descriptions field description 3-0 wrap[3-0] wrap around channel select bits ?these bits determine the channel for wrap around when doing multi-channel conversions. the coding is summarized in table 10-2 . table 10-2. multi-channel wrap around coding wrap3 wrap2 wrap1 wrap0 multiple channel conversions (mult = 1) wraparound to an0 after converting 0000 reserved 1 0001 an1 0010 an2 0011 an3 0100 an4 0101 an5 0110 an6 0111 an7 1000 an8 1001 an9 1010 an10 1011 an11 1100 an11 1101 an11 1110 an11 1111 an11
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 323 10.3.2.2 atd control register 1 (atdctl1) writes to this register will abort current conversion sequence. read: anytime write: anytime 1 if only an0 should be converted use mult=0. module base + 0x0001 76543210 r etrigsel sres1 sres0 smp_dis etrigch3 etrigch2 etrigch1 etrigch0 w reset 0 0 1 01111 figure 10-4. atd control register 1 (atdctl1) table 10-3. atdctl1 field descriptions field description 7 etrigsel external trigger source select ?this bit selects the external trigger source to be either one of the ad channels or one of the etrig3-0 inputs. see device speci?ation for availability and connectivity of etrig3-0 inputs. if a particular etrig3-0 input option is not available, writing a 1 to etrisel only sets the bit but has not effect, this means that one of the ad channels (selected by etrigch3-0) is con?ured as the source for external trigger. the coding is summarized in table 10-5 . 6? sres[1:0] a/d resolution select ?these bits select the resolution of a/d conversion results. see table 10-4 for coding. 4 smp_dis discharge before sampling bit 0 no discharge before sampling. 1 the internal sample capacitor is discharged before sampling the channel. this adds 2 atd clock cycles to the sampling time. this can help to detect an open circuit instead of measuring the previous sampled channel. 3? etrigch[3:0] external trigger channel select these bits select one of the ad channels or one of the etrig3-0 inputs as source for the external trigger. the coding is summarized in table 10-5 . table 10-4. a/d resolution coding sres1 sres0 a/d resolution 0 0 8-bit data 0 1 10-bit data 1 0 12-bit data 1 1 reserved
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 324 freescale semiconductor 10.3.2.3 atd control register 2 (atdctl2) writes to this register will abort current conversion sequence. read: anytime write: anytime table 10-5. external trigger channel select coding etrigsel etrigch3 etrigch2 etrigch1 etrigch0 external trigger source is 0 0 0 0 0 an0 0 0 0 0 1 an1 0 0 0 1 0 an2 0 0 0 1 1 an3 0 0 1 0 0 an4 0 0 1 0 1 an5 0 0 1 1 0 an6 0 0 1 1 1 an7 0 1 0 0 0 an8 0 1 0 0 1 an9 0 1 0 1 0 an10 0 1 0 1 1 an11 0 1 1 0 0 an11 0 1 1 0 1 an11 0 1 1 1 0 an11 0 1 1 1 1 an11 1 0 0 0 0 etrig0 1 1 only if etrig3-0 input option is available (see device speci?ation), else etrisel is ignored, that means external trigger source is still on one of the ad channels selected by etrigch3-0 1 0 0 0 1 etrig1 1 1 0 0 1 0 etrig2 1 1 0 0 1 1 etrig3 1 1 0 1 x x reserved 1 1 x x x reserved module base + 0x0002 76543210 r0 affc iclkstp etrigle etrigp etrige ascie acmpie w reset 0 0 0 00000 = unimplemented or reserved figure 10-5. atd control register 2 (atdctl2)
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 325 table 10-6. atdctl2 field descriptions field description 6 affc atd fast flag clear all 0 atd ?g clearing done by write 1 to respective ccf[ n ] ?g. 1 changes all atd conversion complete ?gs to a fast clear sequence. for compare disabled (cmpe[ n ]=0) a read access to the result register will cause the associated ccf[ n ] ?g to clear automatically. for compare enabled (cmpe[ n ]=1) a write access to the result register will cause the associated ccf[ n ] ?g to clear automatically. 5 iclkstp internal clock in stop mode bit this bit enables a/d conversions in stop mode. when going into stop mode and iclkstp=1 the atd conversion clock is automatically switched to the internally generated clock iclk. current conversion sequence will seamless continue. conversion speed will change from prescaled bus frequency to the iclk frequency (see atd electrical characteristics in device description). the prescaler bits prs4-0 in atdctl4 have no effect on the iclk frequency. for conversions during stop mode the automatic compare interrupt or the sequence complete interrupt can be used to inform software handler about changing a/d values. external trigger will not work while converting in stop mode. for conversions during transition from run to stop mode or vice versa the result is not written to the results register, no ccf ?g is set and no compare is done. when converting in stop mode (iclkstp=1) an atd stop recovery time t atdstprcv is required to switch back to bus clock based atdclk when leaving stop mode. do not access atd registers during this time. 0 if a/d conversion sequence is ongoing when going into stop mode, the actual conversion sequence will be aborted and automatically restarted when exiting stop mode. 1 a/d continues to convert in stop mode using internally generated clock (iclk) 4 etrigle external trigger level/edge control ?this bit controls the sensitivity of the external trigger signal. see table 10-7 for details. 3 etrigp external trigger polarity this bit controls the polarity of the external trigger signal. see table 10-7 for details. 2 etrige external trigger mode enable this bit enables the external trigger on one of the ad channels or one of the etrig3-0 inputs as described in table 10-5 . if external trigger source is one of the ad channels, the digital input buffer of this channel is enabled. the external trigger allows to synchronize the start of conversion with external events. external trigger will not work while converting in stop mode. 0 disable external trigger 1 enable external trigger 1 ascie atd sequence complete interrupt enable 0 atd sequence complete interrupt requests are disabled. 1 atd sequence complete interrupt will be requested whenever scf=1 is set. 0 acmpie atd compare interrupt enable if automatic compare is enabled for conversion n (cmpe[ n ]=1 in atdcmpe register) this bit enables the compare interrupt. if the ccf[ n ] ?g is set (showing a successful compare for conversion n ), the compare interrupt is triggered. 0 atd compare interrupt requests are disabled. 1 for the conversions in a sequence for which automatic compare is enabled (cmpe[ n ]=1), atd compare interrupt will be requested whenever any of the respective ccf ?gs is set. table 10-7. external trigger con?urations etrigle etrigp external trigger sensitivity 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 326 freescale semiconductor 10.3.2.4 atd control register 3 (atdctl3) writes to this register will abort current conversion sequence. read: anytime write: anytime module base + 0x0003 76543210 r djm s8c s4c s2c s1c fifo frz1 frz0 w reset 0 0 1 00000 = unimplemented or reserved figure 10-6. atd control register 3 (atdctl3) table 10-8. atdctl3 field descriptions field description 7 djm result register data justi?ation ?result data format is always unsigned. this bit controls justi?ation of conversion data in the result registers. 0 left justi?d data in the result registers. 1 right justi?d data in the result registers. table 10-9 gives examples atd results for an input signal range between 0 and 5.12 volts. 6? s8c, s4c, s2c, s1c conversion sequence length ?these bits control the number of conversions per sequence. table 10-10 shows all combinations. at reset, s4c is set to 1 (sequence length is 4). this is to maintain software continuity to hc12 family. 2 fifo result register fifo mode if this bit is zero (non-fifo mode), the a/d conversion results map into the result registers based on the conversion sequence; the result of the ?st conversion appears in the ?st result register (atddr0), the second result in the second result register (atddr1), and so on. if this bit is one (fifo mode) the conversion counter is not reset at the beginning or ending of a conversion sequence; sequential conversion results are placed in consecutive result registers. in a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register ?e. the conversion counter value (cc3-0 in atdstat0) can be used to determine where in the result register ?e, the current conversion result will be placed. aborting a conversion or starting a new conversion clears the conversion counter even if fifo=1. so the ?st result of a new conversion sequence, started by writing to atdctl5, will always be place in the ?st result register (atdddr0). intended usage of fifo mode is continuos conversion (scan=1) or triggered conversion (etrig=1). which result registers hold valid data can be tracked using the conversion complete ?gs. fast ?g clear mode may or may not be useful in a particular application to track valid data. if this bit is one, automatic compare of result registers is always disabled, that is adc12b12c will behave as if acmpie and all cpme[ n ] were zero. 0 conversion results are placed in the corresponding result register up to the selected sequence length. 1 conversion results are placed in consecutive result registers (wrap around at end). 1? frz[1:0] background debug freeze enable ?when debugging an application, it is useful in many cases to have the atd pause when a breakpoint (freeze mode) is encountered. these 2 bits determine how the atd will respond to a breakpoint as shown in table 10-11 . leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 327 table 10-9. examples of ideal decimal atd results input signal v rl = 0 volts v rh = 5.12 volts 8-bit codes (resolution=20mv) 10-bit codes (resolution=5mv) 12-bit codes (transfer curve has 1.25mv offset) (resolution=1.25mv) 5.120 volts ... 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 255 ... 1 1 1 1 1 1 1 0 0 0 0 0 0 1023 ... 4 4 4 3 3 2 2 2 1 1 0 0 0 4095 ... 17 16 14 12 11 9 8 6 4 3 2 1 0 table 10-10. conversion sequence length coding s8c s4c s2c s1c number of conversions per sequence 00 0 0 12 00 0 1 1 00 1 0 2 00 1 1 3 01 0 0 4 01 0 1 5 01 1 0 6 01 1 1 7 10 0 0 8 10 0 1 9 10 1 0 10 10 1 1 11 11 0 0 12 11 0 1 12 11 1 0 12 11 1 1 12
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 328 freescale semiconductor 10.3.2.5 atd control register 4 (atdctl4) writes to this register will abort current conversion sequence. read: anytime write: anytime table 10-11. atd behavior in freeze mode (breakpoint) frz1 frz0 behavior in freeze mode 0 0 continue conversion 0 1 reserved 1 0 finish current conversion, then freeze 1 1 freeze immediately module base + 0x0004 76543210 r smp2 smp1 smp0 prs[4:0] w reset 0 0 0 00101 figure 10-7. atd control register 4 (atdctl4) table 10-12. atdctl4 field descriptions field description 7? smp[2:0] sample time select ?these three bits select the length of the sample time in units of atd conversion clock cycles. note that the atd conversion clock period is itself a function of the prescaler value (bits prs4-0). table 10-13 lists the available sample time lengths. 4? prs[4:0] atd clock prescaler these 5 bits are the binary prescaler value prs. the atd conversion clock frequency is calculated as follows: refer to device speci?ation for allowed frequency range of f atdclk . table 10-13. sample time select smp2 smp1 smp0 sample time in number of atd clock cycles 000 4 001 6 010 8 011 10 100 12 101 16 110 20 f atdclk f bus 2 prs 1 + () ------------------------------------- =
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 329 10.3.2.6 atd control register 5 (atdctl5) writes to this register will abort current conversion sequence and start a new conversion sequence. if external trigger is enabled (etrige=1) an initial write to atdctl5 is required to allow starting of a conversion sequence which will then occur on each trigger event. start of conversion means the beginning of the sampling phase. read: anytime write: anytime 111 24 module base + 0x0005 76543210 r0 sc scan mult cd cc cb ca w reset 0 0 0 00000 = unimplemented or reserved figure 10-8. atd control register 5 (atdctl5) table 10-14. atdctl5 field descriptions field description 6 sc special channel conversion bit if this bit is set, then special channel conversion can be selected using cd, cc, cb and ca of atdctl5. table 10-15 lists the coding. 0 special channel conversions disabled 1 special channel conversions enabled 5 scan continuous conversion sequence mode ?this bit selects whether conversion sequences are performed continuously or only once. if external trigger is enabled (etrige=1) setting this bit has no effect, that means external trigger always starts a single conversion sequence. 0 single conversion sequence 1 continuous conversion sequences (scan mode) table 10-13. sample time select smp2 smp1 smp0 sample time in number of atd clock cycles
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 330 freescale semiconductor 4 mult multi-channel sample mode when mult is 0, the atd sequence controller samples only from the speci?d analog input channel for an entire conversion sequence. the analog channel is selected by channel selection code (control bits cd/cc/cb/ca located in atdctl5). when mult is 1, the atd sequence controller samples across channels. the number of channels sampled is determined by the sequence length value (s8c, s4c, s2c, s1c). the ?st analog channel examined is determined by channel selection code (cd, cc, cb, ca control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code or wrapping around to an0 (channel 0). 0 sample only one channel 1 sample across several channels 3? cd, cc, cb, ca analog input channel select code ?these bits select the analog input channel(s) whose signals are sampled and converted to digital codes. table 10-15 lists the coding used to select the various analog input channels. in the case of single channel conversions (mult=0), this selection code speci?s the channel to be examined. in the case of multiple channel conversions (mult=1), this selection code speci?s the ?st channel to be examined in the conversion sequence. subsequent channels are determined by incrementing the channel selection code or wrapping around to an0 (after converting the channel de?ed by the wrap around channel select bits wrap3-0 in atdctl0). in case of starting with a channel number higher than the one de?ed by wrap3-0 the ?st wrap around will be an7 to an0. table 10-15. analog input channel select coding sc cd cc cb ca analog input channel 00000 an0 0001 an1 0010 an2 0011 an3 0100 an4 0101 an5 0110 an6 0111 an7 1000 an8 1001 an9 1 0 1 0 an10 1 0 1 1 an11 1 1 0 0 an11 1 1 0 1 an11 1 1 1 0 an11 1 1 1 1 an11 table 10-14. atdctl5 field descriptions (continued) field description
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 331 1 0 0 0 0 reserved 0 0 0 1 special17 0 0 1 x reserved 0100 v rh 0101 v rl 0110 (v rh +v rl ) / 2 0 1 1 1 reserved 1 x x x reserved table 10-15. analog input channel select coding sc cd cc cb ca analog input channel
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 332 freescale semiconductor 10.3.2.7 atd status register 0 (atdstat0) this register contains the sequence complete flag, overrun ?gs for external trigger and fifo mode, and the conversion counter. read: anytime write: anytime (no effect on (cc3, cc2, cc1, cc0)) module base + 0x0006 76543210 r scf 0 etorf fifor cc3 cc2 cc1 cc0 w reset 0 0 0 00000 = unimplemented or reserved figure 10-9. atd status register 0 (atdstat0) table 10-16. atdstat0 field descriptions field description 7 scf sequence complete flag ?this ?g is set upon completion of a conversion sequence. if conversion sequences are continuously performed (scan=1), the ?g is set after each one is completed. this ?g is cleared when one of the following occurs: a) write ??to scf b) write to atdctl5 (a new conversion sequence is started) c) if affc=1 and read of a result register 0 conversion sequence not completed 1 conversion sequence has completed 5 etorf external trigger overrun flag ?while in edge trigger mode (etrigle=0), if additional active edges are detected while a conversion sequence is in process the overrun ?g is set. this ?g is cleared when one of the following occurs: a) write ??to etorf b) write to atdctl0,1,2,3,4, atdcmpe or atdcmpht (a conversion sequence is aborted) c) write to atdctl5 (a new conversion sequence is started) 0 no external trigger over run error has occurred 1 external trigger over run error has occurred 4 fifor result register over run flag ?this bit indicates that a result register has been written to before its associated conversion complete ?g (ccf) has been cleared. this ?g is most useful when using the fifo mode because the ?g potentially indicates that result registers are out of sync with the input channels. however, it is also practical for non-fifo modes, and indicates that a result register has been over written before it has been read (i.e. the old data has been lost). this ?g is cleared when one of the following occurs: a) write ??to fifor b) write to atdctl0,1,2,3,4, atdcmpe or atdcmpht (a conversion sequence is aborted) c) write to atdctl5 (a new conversion sequence is started) 0 no over run has occurred 1 overrun condition exists (result register has been written while associated ccfx ?g was still set)
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 333 10.3.2.8 atd compare enable register (atdcmpe) writes to this register will abort current conversion sequence. read: anytime write: anytime 3? cc[3:0] conversion counter these 4 read-only bits are the binary value of the conversion counter. the conversion counter points to the result register that will receive the result of the current conversion. e.g. cc3=0, cc2=1, cc1=1, cc0=0 indicates that the result of the current conversion will be in atd result register 6. if in non-fifo mode (fifo=0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. if in fifo mode (fifo=1) the register counter is not initialized. the conversion counters wraps around when its maximum value is reached. aborting a conversion or starting a new conversion clears the conversion counter even if fifo=1. module base + 0x0008 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 cmpe[11:0] w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 10-10. atd compare enable register (atdcmpe) table 10-17. atdcmpe field descriptions field description 11? cmpe[11:0] compare enable for conversion number n ( n = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a sequence ( n conversion number, not channel number!) these bits enable automatic compare of conversion results individually for conversions of a sequence. the sense of each comparison is determined by the cmpht[ n ] bit in the atdcmpht register. for each conversion number with cmpe[ n ]=1 do the following: 1) write compare value to atddr n result register 2) write compare operator with cmpht[ n ] in atdcpmht register ccf[ n ] in atdstat2 register will ?g individual success of any comparison. 0 no automatic compare 1 automatic compare of results for conversion n of a sequence is enabled. table 10-16. atdstat0 field descriptions (continued) field description
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 334 freescale semiconductor 10.3.2.9 atd status register 2 (atdstat2) this read-only register contains the conversion complete flags ccf[11:0]. read: anytime write: anytime, no effect module base + 0x000a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 ccf[11:0] w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 10-11. atd status register 2 (atdstat2) table 10-18. atdstat2 field descriptions field description 11? ccf[11:0] conversion complete flag n ( n = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) ( n conversion number, not channel number!) ?a conversion complete ?g is set at the end of each conversion in a sequence. the ?gs are associated with the conversion position in a sequence (and also the result register number). therefore in non-?o mode, ccf[4] is set when the ?th conversion in a sequence is complete and the result is available in result register atddr4; ccf[5] is set when the sixth conversion in a sequence is complete and the result is available in atddr5, and so forth. if automatic compare of conversion results is enabled (cmpe[ n ]=1 in atdcmpe), the conversion complete ?g is only set if comparison with atddr n is true and if acmpie=1 a compare interrupt will be requested. in this case, as the atddr n result register is used to hold the compare value, the result will not be stored there at the end of the conversion but is lost. a ?g ccf[ n ] is cleared when one of the following occurs: a) write to atdctl5 (a new conversion sequence is started) b) if affc=0, write ??to ccf[ n ] c) if affc=1 and cmpe[ n ]=0, read of result register atddr n d) if affc=1 and cmpe[ n ]=1, write to result register atddr n in case of a concurrent set and clear on ccf[ n ]: the clearing by method a) will overwrite the set. the clearing by methods b) or c) or d) will be overwritten by the set. 0 conversion number n not completed or successfully compared 1 if (cmpe[ n ]=0): conversion number n has completed. result is ready in atddr n . if (cmpe[ n ]=1): compare for conversion result number n with compare value in atddr n , using compare operator cmpgt[ n ] is true. (no result available in atddr n )
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 335 10.3.2.10 atd input enable register (atddien) read: anytime write: anytime 10.3.2.11 atd compare higher than register (atdcmpht) writes to this register will abort current conversion sequence. read: anytime write: anytime module base + 0x000c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 ien[11:0] w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 10-12. atd input enable register (atddien) table 10-19. atddien field descriptions field description 11? ien[11:0] atd digital input enable on channel x ( x = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) this bit controls the digital input buffer from the analog input pin (an x ) to the digital data register. 0 disable digital input buffer to an x pin 1 enable digital input buffer on an x pin. note: setting this bit will enable the corresponding digital input buffer continuously. if this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region. module base + 0x000e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 cmpht[11:0] w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 10-13. atd compare higher than register (atdcmpht) table 10-20. atdcmpht field descriptions field description 11? cmpht[11:0] compare operation higher than enable for conversion number n ( n = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a sequence ( n conversion number, not channel number!) this bit selects the operator for comparison of conversion results. 0 if result of conversion n is lower or same than compare value in atddr n , this is ?gged in atdstat2 1 if result of conversion n is higher than compare value in atddr n , this is ?gged in atdstat2
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 336 freescale semiconductor 10.3.2.12 atd conversion result registers (atddr n ) the a/d conversion results are stored in 12 result registers. results are always in unsigned data representation. left and right justi?ation is selected using the djm control bit in atdctl3. if automatic compare of conversions results is enabled (cmpe[ n ]=1 in atdcmpe), these registers must be written with the compare values in left or right justi?d format depending on the actual value of the djm bit. in this case, as the atddr n register is used to hold the compare value, the result will not be stored there at the end of the conversion but is lost. attention, n is the conversion number, not the channel number! read: anytime write: anytime note for conversions not using automatic compare, results are stored in the result registers after each conversion. in this case avoid writing to atddrn except for initial values, because an a/d result might be overwritten. 10.3.2.12.1 left justi?d result data (djm=0) 10.3.2.12.2 right justi?d result data (djm=1) module base + 0x0010 = atddr0, 0x0012 = atddr1, 0x0014 = atddr2, 0x0016 = atddr3 0x0018 = atddr4, 0x001a = atddr5, 0x001c = atddr6, 0x001e = atddr7 0x0020 = atddr8, 0x0022 = atddr9, 0x0024 = atddr10, 0x0026 = atddr11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 000 w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 10-14. left justi?d atd conversion result register (atddr n ) module base + 0x0010 = atddr0, 0x0012 = atddr1, 0x0014 = atddr2, 0x0016 = atddr3 0x0018 = atddr4, 0x001a = atddr5, 0x001c = atddr6, 0x001e = atddr7 0x0020 = atddr8, 0x0022 = atddr9, 0x0024 = atddr10, 0x0026 = atddr11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 000 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi1 1 bit 0 w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 10-15. right justi?d atd conversion result register (atddr n )
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 337 table 10-21 shows how depending on the a/d resolution the conversion result is transferred to the atd result registers. compare is always done using all 12 bits of both the conversion result and the compare value in atddrn. table 10-21. conversion result mapping to atddrn a/d resolution djm conversion result mapping to atddr n 8-bit data 0 bit[11:4] = result, bit[3:0]=0000 8-bit data 1 bit[7:0] = result, bit[11:8]=0000 10-bit data 0 bit[11:2] = result, bit[1:0]=00 10-bit data 1 bit[9:0] = result, bit[11:10]=00 12-bit data x bit[11:0] = result
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 338 freescale semiconductor 10.4 functional description the adc12b12c is structured into an analog sub-block and a digital sub-block. 10.4.1 analog sub-block the analog sub-block contains all analog electronics required to perform a single conversion. separate power supplies v dda and v ssa allow to isolate noise of other mcu circuitry from the analog sub-block. 10.4.1.1 sample and hold machine the sample and hold (s/h) machine accepts analog signals from the external world and stores them as capacitor charge on a storage node. during the sample process the analog input connects directly to the storage node. the input analog signals are unipolar and must fall within the potential range of v ssa to v dda . during the hold process the analog input is disconnected from the storage node. 10.4.1.2 analog input multiplexer the analog input multiplexer connects one of the 8 external analog input channels to the sample and hold machine. 10.4.1.3 analog-to-digital (a/d) machine the a/d machine performs analog to digital conversions. the resolution is program selectable at either 8 or 10 or 12 bits. the a/d machine uses a successive approximation architecture. it functions by comparing the stored analog sample potential with a series of digitally generated analog potentials. by following a binary search algorithm, the a/d machine locates the approximating potential that is nearest to the sampled potential. when not converting the a/d machine is automatically powered down. only analog input signals within the potential range of v rl to v rh (a/d reference potentials) will result in a non-railed digital output code. 10.4.2 digital sub-block this subsection explains some of the digital features in more detail. see section 10.3.2, ?egister descriptions for all details. 10.4.2.1 external trigger input the external trigger feature allows the user to synchronize atd conversions to the external environment events rather than relying on software to signal the atd module when atd conversions are to take place. the external trigger signal (out of reset atd channel 11, con?urable in atdctl1) is programmable to
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 339 be edge or level sensitive with polarity control. table 10-22 gives a brief description of the different combinations of control bits and their effect on the external trigger function. during a conversion, if additional active edges are detected the overrun error ?g etorf is set. in either level or edge triggered modes, the ?st conversion begins when the trigger is received. once etrige is enabled, conversions cannot be started by a write to atdctl5, but rather must be triggered externally. if the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion sequence, this does not constitute an overrun. therefore, the ?g is not set. if the trigger is left asserted in level mode while a sequence is completing, another sequence will be triggered immediately. 10.4.2.2 general-purpose digital port operation the input channel pins can be multiplexed between analog and digital data. as analog inputs, they are multiplexed and sampled as analog channels to the a/d converter. the analog/digital multiplex operation is performed in the input pads. the input pad is always connected to the analog input channels of the adc12b12c. the input pad signal is buffered to the digital port registers. this buffer can be turned on or off with the atddien register. this is important so that the buffer does not draw excess current when analog potentials are presented at its input. 10.5 resets at reset the adc12b12c is in a power down state. the reset state of each individual bit is listed within the register description section (see section 10.3.2, ?egister descriptions ) which details the registers and their bit-?ld. table 10-22. external trigger control bits etrigle etrigp etrige scan description x x 0 0 ignores external trigger. performs one conversion sequence and stops. x x 0 1 ignores external trigger. performs continuous conversion sequences. 0 0 1 x falling edge triggered. performs one conversion sequence per trigger. 0 1 1 x rising edge triggered. performs one conversion sequence per trigger. 1 0 1 x trigger active low. performs continuous conversions while trigger is active. 1 1 1 x trigger active high. performs continuous conversions while trigger is active.
analog-to-digital converter (adc12b12cv1) block description mc9s12xhy-family reference manual, rev. 1.01 340 freescale semiconductor 10.6 interrupts the interrupts requested by the adc12b12c are listed in table 10-23 . refer to mcu speci?ation for related vector address and priority. see section 10.3.2, ?egister descriptions for further details. table 10-23. atd interrupt vectors interrupt source ccr mask local enable sequence complete interrupt i bit ascie in atdctl2 compare interrupt i bit acmpie in atdctl2
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 341 chapter 11 freescales scalable controller area network (s12mscanv3) 11.1 introduction freescales scalable controller area network (s12mscanv3) de?ition is based on the mscan12 de?ition, which is the speci? implementation of the mscan concept targeted for the m68hc12 microcontroller family. the module is a communication controller implementing the can 2.0a/b protocol as de?ed in the bosch speci?ation dated september 1991. for users to fully understand the mscan speci?ation, it is recommended that the bosch speci?ation be read ?st to familiarize the reader with the terms and concepts contained within this document. though not exclusively intended for automotive applications, can protocol is designed to meet the speci? requirements of a vehicle serial data bus: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness, and required bandwidth. mscan uses an advanced buffer arrangement resulting in predictable real-time behavior and simpli?d application software. table 11-1. revision history revision number revision date sections affected description of changes v03.10 19 aug 2008 11.4.7.4/11-393 11.4.4.5/11-387 11.2/11-344 - corrected wake-up description - relocated initialization section - added note to external pin descriptions for use with integrated physical layer - minor corrections v03.11 31 mar 2009 - orthographic corrections v03.12 09 aug 2010 table 11-37 - added ?osch can 2.0a/b?to bit time settings table
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 342 freescale semiconductor 11.1.1 glossary 11.1.2 block diagram figure 11-1. mscan block diagram table 11-2. terminology ack acknowledge of can message can controller area network crc cyclic redundancy code eof end of frame fifo first-in-first-out memory ifs inter-frame sequence sof start of frame cpu bus cpu related read/write data bus can bus can protocol related serial bus oscillator clock direct clock from external oscillator bus clock cpu bus related clock can clock can protocol related clock rxcan txcan receive/ transmit engine message filtering and buffering control and status wake-up interrupt req. errors interrupt req. receive interrupt req. transmit interrupt req. canclk bus clock con?uration oscillator clock mux presc. tq clk mscan low pass filter wake-up registers
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 343 11.1.3 features the basic features of the mscan are as follows: implementation of the can protocol ?version 2.0a/b standard and extended data frames zero to eight bytes data length programmable bit rate up to 1 mbps 8 support for remote frames five receive buffers with fifo storage scheme three transmit buffers with internal prioritization using a ?ocal priority?concept flexible maskable identi?r ?ter supports two full-size (32-bit) extended identi?r ?ters, or four 16-bit ?ters, or eight 8-bit ?ters programmable wake-up functionality with integrated low-pass ?ter programmable loopback mode supports self-test operation programmable listen-only mode for monitoring of can bus programmable bus-off recovery functionality separate signalling and interrupt capabilities for all can receiver and transmitter error states (warning, error passive, bus-off) programmable mscan clock source either bus clock or oscillator clock internal timer for time-stamping of received and transmitted messages three low-power modes: sleep, power down, and mscan enable global initialization of con?uration registers 11.1.4 modes of operation for a description of the speci? mscan modes and the module operation related to the system operating modes refer to section 11.4.4, ?odes of operation ? 8. depending on the actual bit timing and the clock jitter of the pll.
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 344 freescale semiconductor 11.2 external signal description the mscan uses two external pins. note on mcus with an integrated can physical interface (transceiver) the mscan interface is connected internally to the transceiver interface. in these cases the external availability of signals txcan and rxcan is optional. 11.2.1 rxcan ?can receiver input pin rxcan is the mscan receiver input pin. 11.2.2 txcan ?can transmitter output pin txcan is the mscan transmitter output pin. the txcan output pin represents the logic level on the can bus: 0 = dominant state 1 = recessive state 11.2.3 can system a typical can system with mscan is shown in figure 11-2 . each can station is connected physically to the can bus lines through a transceiver device. the transceiver is capable of driving the large current needed for the can bus and has current protection against defective can or defective stations. figure 11-2. can system can bus can controller (mscan) transceiver can node 1 can node 2 can node n canl canh mcu txcan rxcan
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 345 11.3 memory map and register de?ition this section provides a detailed description of all registers accessible in the mscan. 11.3.1 module memory map figure 11-3 gives an overview on all registers and their individual bits in the mscan memory map. the register address results from the addition of base address and address offset . the base address is determined at the mcu level and can be found in the mcu memory map description. the address offset is de?ed at the module level. the mscan occupies 64 bytes in the memory space. the base address of the mscan module is determined at the mcu level when the mcu is de?ed. the register decode map is ?ed and begins at the ?st address of the module address offset. the detailed register descriptions follow in the order they appear in the register map.
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 346 freescale semiconductor register name bit 7 6 5 4 3 2 1 bit 0 0x0000 canctl0 r rxfrm rxact cswai synch time wupe slprq initrq w 0x0001 canctl1 r cane clksrc loopb listen borm wupm slpak initak w 0x0002 canbtr0 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 w 0x0003 canbtr1 r samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 w 0x0004 canrflg r wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf w 0x0005 canrier r wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie w 0x0006 cantflg r0 0 0 00 txe2 txe1 txe0 w 0x0007 cantier r00000 txeie2 txeie1 txeie0 w 0x0008 cantarq r00000 abtrq2 abtrq1 abtrq0 w 0x0009 cantaak r00000 abtak2 abtak1 abtak0 w 0x000a cantbsel r00000 tx2 tx1 tx0 w 0x000b canidac r0 0 idam1 idam0 0 idhit2 idhit1 idhit0 w 0x000c reserved r00000000 w 0x000d canmisc r0000000 bohold w 0x000e canrxerr r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 w = unimplemented or reserved figure 11-3. mscan register summary
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 347 11.3.2 register descriptions this section describes in detail all the registers and register bits in the mscan module. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. all bits of all registers in this module are completely synchronous to internal clocks during a register read. 11.3.2.1 mscan control register 0 (canctl0) the canctl0 register provides various control bits of the mscan module as described below. 0x000f cantxerr r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 w 0x0010?x0013 canidar0? r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x0014?x0017 canidmrx r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0018?x001b canidar4? r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x001c?x001f canidmr4? r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0020?x002f canrxfg r see section 11.3.3, ?rogrammers model of message storage w 0x0030?x003f cantxfg r see section 11.3.3, ?rogrammers model of message storage w module base + 0x0000 access: user read/write (1) 76543210 r rxfrm rxact cswai synch time wupe slprq initrq w reset: 00000001 = unimplemented figure 11-4. mscan control register 0 (canctl0) register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 11-3. mscan register summary (continued)
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 348 freescale semiconductor note the canctl0 register, except wupe, initrq, and slprq, is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable again as soon as the initialization mode is exited (initrq = 0 and initak = 0). 1. read: anytime write: anytime when out of initialization mode; exceptions are read-only rxact and synch, rxfrm (which is set by the module only), and initrq (which is also writable in initialization mode) table 11-3. canctl0 register field descriptions field description 7 rxfrm (1) received frame flag this bit is read and clear only. it is set when a receiver has received a valid message correctly, independently of the ?ter con?uration. after it is set, it remains set until cleared by software or reset. clearing is done by writing a 1. writing a 0 is ignored. this bit is not valid in loopback mode. 0 no valid message was received since last clearing this ?g 1 a valid message was received since last clearing of this ?g 6 rxact receiver active status ?this read-only ?g indicates the mscan is receiving a message. the ?g is controlled by the receiver front end. this bit is not valid in loopback mode. 0 mscan is transmitting or idle 2 1 mscan is receiving a message (including when arbitration is lost) (2) 5 cswai (3) can stops in wait mode enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the cpu bus interface to the mscan module. 0 the module is not affected during wait mode 1 the module ceases to be clocked during wait mode 4 synch synchronized status this read-only ?g indicates whether the mscan is synchronized to the can bus and able to participate in the communication process. it is set and cleared by the mscan. 0 mscan is not synchronized to the can bus 1 mscan is synchronized to the can bus 3 time timer enable this bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. if the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active tx/rx buffer. right after the eof of a valid message on the can bus, the time stamp is written to the highest bytes (0x000e, 0x000f) in the appropriate buffer (see section 11.3.3, ?rogrammers model of message storage ?. the internal timer is reset (all bits set to 0) when disabled. this bit is held low in initialization mode. 0 disable internal mscan timer 1 enable internal mscan timer 2 wupe (4) wake-up enable ?this con?uration bit allows the mscan to restart from sleep mode or from power down mode (entered from sleep) when traf? on can is detected (see section 11.4.5.5, ?scan sleep mode ?. this bit must be con?ured before sleep mode entry for the selected function to take effect. 0 wake-up disabled ?the mscan ignores traf? on can 1 wake-up enabled ?the mscan is able to restart
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 349 11.3.2.2 mscan control register 1 (canctl1) the canctl1 register provides various control bits and handshake status information of the mscan module as described below. 1 slprq (5) sleep mode request ?this bit requests the mscan to enter sleep mode, which is an internal power saving mode (see section 11.4.5.5, ?scan sleep mode ?. the sleep mode request is serviced when the can bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty. the module indicates entry to sleep mode by setting slpak = 1 (see section 11.3.2.2, ?scan control register 1 (canctl1) ?. slprq cannot be set while the wupif ?g is set (see section 11.3.2.5, ?scan receiver flag register (canrflg) ?. sleep mode will be active until slprq is cleared by the cpu or, depending on the setting of wupe, the mscan detects activity on the can bus and clears slprq itself. 0 running ?the mscan functions normally 1 sleep mode request ?the mscan enters sleep mode when can bus idle 0 initrq (6),(7) initialization mode request ?when this bit is set by the cpu, the mscan skips to initialization mode (see section 11.4.4.5, ?scan initialization mode ?. any ongoing transmission or reception is aborted and synchronization to the can bus is lost. the module indicates entry to initialization mode by setting initak = 1 ( section 11.3.2.2, ?scan control register 1 (canctl1) ?. the following registers enter their hard reset state and restore their default values: canctl0 (8) , canrflg (9) , canrier (10) , cantflg, cantier, cantarq, cantaak, and cantbsel. the registers canctl1, canbtr0, canbtr1, canidac, canidar0-7, and canidmr0-7 can only be written by the cpu when the mscan is in initialization mode (initrq = 1 and initak = 1). the values of the error counters are not affected by initialization mode. when this bit is cleared by the cpu, the mscan restarts and then tries to synchronize to the can bus. if the mscan is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the can bus; if the mscan is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. writing to other bits in canctl0, canrflg, canrier, cantflg, or cantier must be done only after initialization mode is exited, which is initrq = 0 and initak = 0. 0 normal operation 1 mscan in initialization mode 1. the mscan must be in normal mode for this bit to become set. 2. see the bosch can 2.0a/b speci?ation for a detailed de?ition of transmitter and receiver states. 3. in order to protect from accidentally violating the can protocol, txcan is immediately forced to a recessive state when the cpu enters wait (cswai = 1) or stop mode (see section 11.4.5.2, ?peration in wait mode and section 11.4.5.3, ?peration in stop mode ? . 4. the cpu has to make sure that the wupe register and the wupie wake-up interrupt enable register (see section 11.3.2.6, ?scan receiver interrupt enable register (canrier) ) is enabled, if the recovery mechanism from stop or wait is required. 5. the cpu cannot clear slprq before the mscan has entered sleep mode (slprq = 1 and slpak = 1). 6. the cpu cannot clear initrq before the mscan has entered initialization mode (initrq = 1 and initak = 1). 7. in order to protect from accidentally violating the can protocol, txcan is immediately forced to a recessive state when the initialization mode is requested by the cpu. thus, the recommended procedure is to bring the mscan into sleep mode (slprq = 1 and slpak = 1) before requesting initialization mode. 8. not including wupe, initrq, and slprq. 9. tstat1 and tstat0 are not affected by initialization mode. 10. rstat1 and rstat0 are not affected by initialization mode. table 11-3. canctl0 register field descriptions (continued) field description
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 350 freescale semiconductor module base + 0x0001 access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1); cane is write once 76543210 r cane clksrc loopb listen borm wupm slpak initak w reset: 00010001 = unimplemented figure 11-5. mscan control register 1 (canctl1) table 11-4. canctl1 register field descriptions field description 7 cane mscan enable 0 mscan module is disabled 1 mscan module is enabled 6 clksrc mscan clock source this bit de?es the clock source for the mscan module (only for systems with a clock generation module; section 11.4.3.2, ?lock system , and section figure 11-43., ?scan clocking scheme ,?. 0 mscan clock source is the oscillator clock 1 mscan clock source is the bus clock 5 loopb loopback self test mode when this bit is set, the mscan performs an internal loopback which can be used for self test operation. the bit stream output of the transmitter is fed back to the receiver internally. the rxcan input is ignored and the txcan output goes to the recessive state (logic 1). the mscan behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. in this state, the mscan ignores the bit sent during the ack slot in the can frame acknowledge ?ld to ensure proper reception of its own message. both transmit and receive interrupts are generated. 0 loopback self test disabled 1 loopback self test enabled 4 listen listen only mode this bit con?ures the mscan as a can bus monitor. when listen is set, all valid can messages with matching id are received, but no acknowledgement or error frames are sent out (see section 11.4.4.4, ?isten-only mode ?. in addition, the error counters are frozen. listen only mode supports applications which require ?ot plugging?or throughput analysis. the mscan is unable to transmit any messages when listen only mode is active. 0 normal operation 1 listen only mode activated 3 borm bus-off recovery mode ?this bit con?ures the bus-off state recovery mode of the mscan. refer to section 11.5.2, ?us-off recovery , for details. 0 automatic bus-off recovery (see bosch can 2.0a/b protocol speci?ation) 1 bus-off recovery upon user request 2 wupm wake-up mode ?if wupe in canctl0 is enabled, this bit de?es whether the integrated low-pass ?ter is applied to protect the mscan from spurious wake-up (see section 11.4.5.5, ?scan sleep mode ?. 0 mscan wakes up on any dominant level on the can bus 1 mscan wakes up only in case of a dominant pulse on the can bus that has a length of t wup
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 351 11.3.2.3 mscan bus timing register 0 (canbtr0) the canbtr0 register con?ures various can bus timing parameters of the mscan module. 1 slpak sleep mode acknowledge ?this ?g indicates whether the mscan module has entered sleep mode (see section 11.4.5.5, ?scan sleep mode ?. it is used as a handshake ?g for the slprq sleep mode request. sleep mode is active when slprq = 1 and slpak = 1. depending on the setting of wupe, the mscan will clear the ?g if it detects activity on the can bus while in sleep mode. 0 running ?the mscan operates normally 1 sleep mode active ?the mscan has entered sleep mode 0 initak initialization mode acknowledge ?this ?g indicates whether the mscan module is in initialization mode (see section 11.4.4.5, ?scan initialization mode ?. it is used as a handshake ?g for the initrq initialization mode request. initialization mode is active when initrq = 1 and initak = 1. the registers canctl1, canbtr0, canbtr1, canidac, canidar0?anidar7, and canidmr0?anidmr7 can be written only by the cpu when the mscan is in initialization mode. 0 running ?the mscan operates normally 1 initialization mode active ?the mscan has entered initialization mode module base + 0x0002 access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 76543210 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 w reset: 00000000 figure 11-6. mscan bus timing register 0 (canbtr 0 ) table 11-5. canbtr 0 register field descriptions field description 7-6 sjw[1:0] synchronization jump width the synchronization jump width de?es the maximum number of time quanta (tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the can bus (see table 11-6 ). 5-0 brp[5:0] baud rate prescaler these bits determine the time quanta (tq) clock which is used to build up the bit timing (see table 11-7 ). table 11-6. synchronization jump width sjw1 sjw0 synchronization jump width 0 0 1 tq clock cycle 0 1 2 tq clock cycles 1 0 3 tq clock cycles 1 1 4 tq clock cycles table 11-4. canctl1 register field descriptions (continued) field description
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 352 freescale semiconductor 11.3.2.4 mscan bus timing register 1 (canbtr1) the canbtr1 register con?ures various can bus timing parameters of the mscan module. table 11-7. baud rate prescaler brp5 brp4 brp3 brp2 brp1 brp0 prescaler value (p) 000000 1 000001 2 000010 3 000011 4 :::::: : 111111 64 module base + 0x0003 access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 76543210 r samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 w reset: 00000000 figure 11-7. mscan bus timing register 1 (canbtr1) table 11-8. canbtr1 register field descriptions field description 7 samp sampling ?this bit determines the number of can bus samples taken per bit time. 0 one sample per bit. 1 three samples per bit (1) . if samp = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. if samp = 1, the resulting bit value is determined by using majority rule on the three total samples. for higher bit rates, it is recommended that only one sample is taken per bit time (samp = 0). 1. in this case, phase_seg1 must be at least 2 time quanta (tq). 6-4 tseg2[2:0] time segment 2 time segments within the bit time ? the number of clock cycles per bit time and the location of the sample point (see figure 11-44 ). time segment 2 (tseg2) values are programmable as shown in table 11-9 . 3-0 tseg1[3:0] time segment 1 time segments within the bit time ? the number of clock cycles per bit time and the location of the sample point (see figure 11-44 ). time segment 1 (tseg1) values are programmable as shown in table 11-10 .
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 353 the bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (tq) clock cycles per bit (as shown in table 11-9 and table 11-10 ). eqn. 11-1 11.3.2.5 mscan receiver flag register (canrflg) a ?g can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. every ?g has an associated interrupt enable bit in the canrier register. table 11-9. time segment 2 values tseg22 tseg21 tseg20 time segment 2 0 0 0 1 tq clock cycle (1) 1. this setting is not valid. please refer to table 11-37 for valid settings. 0 0 1 2 tq clock cycles ::: : 1 1 0 7 tq clock cycles 1 1 1 8 tq clock cycles table 11-10. time segment 1 values tseg13 tseg12 tseg11 tseg10 time segment 1 0 0 0 0 1 tq clock cycle (1) 1. this setting is not valid. please refer to table 11-37 for valid settings. 0 0 0 1 2 tq clock cycles 1 0 0 1 0 3 tq clock cycles 1 0 0 1 1 4 tq clock cycles :::: : 1 1 1 0 15 tq clock cycles 1 1 1 1 16 tq clock cycles module base + 0x0004 access: user read/write (1) 76543210 r wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf w reset: 00000000 = unimplemented figure 11-8. mscan receiver flag register (canrflg) bit time prescaler value () f canclk ----------------------------------------------------- - 1 timesegment1 timesegment2 ++ () ? =
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 354 freescale semiconductor note the canrflg register is held in the reset state 9 when the initialization mode is active (initrq = 1 and initak = 1). this register is writable again as soon as the initialization mode is exited (initrq = 0 and initak = 0). 1. read: anytime write: anytime when not in initialization mode, except rstat[1:0] and tstat[1:0] ?gs which are read-only; write of 1 clears ?g; write of 0 is ignored 9. the rstat[1:0], tstat[1:0] bits are not affected by initialization mode. table 11-11. canrflg register field descriptions field description 7 wupif wake-up interrupt flag if the mscan detects can bus activity while in sleep mode (see section 11.4.5.5, ?scan sleep mode ,? and wupe = 1 in cantctl0 (see section 11.3.2.1, ?scan control register 0 (canctl0) ?, the module will set wupif. if not masked, a wake-up interrupt is pending while this ?g is set. 0 no wake-up activity observed while in sleep mode 1 mscan detected activity on the can bus and requested wake-up 6 cscif can status change interrupt flag ?this ?g is set when the mscan changes its current can bus status due to the actual value of the transmit error counter (tec) and the receive error counter (rec). an additional 4- bit (rstat[1:0], tstat[1:0]) status register, which is split into separate sections for tec/rec, informs the system on the actual can bus status (see section 11.3.2.6, ?scan receiver interrupt enable register (canrier) ?. if not masked, an error interrupt is pending while this ?g is set. cscif provides a blocking interrupt. that guarantees that the receiver/transmitter status bits (rstat/tstat) are only updated when no can status change interrupt is pending. if the tecs/recs change their current value after the cscif is asserted, which would cause an additional state change in the rstat/tstat bits, these bits keep their status until the current cscif interrupt is cleared again. 0 no change in can bus status occurred since last interrupt 1 mscan changed current can bus status 5-4 rstat[1:0] receiver status bits the values of the error counters control the actual can bus status of the mscan. as soon as the status change interrupt ?g (cscif) is set, these bits indicate the appropriate receiver related can bus status of the mscan. the coding for the bits rstat1, rstat0 is: 00 rxok: 0 receive error counter 96 01 rxwrn: 96 < receive error counter 127 10 rxerr: 127 < receive error counter 11 bus-off (1) : transmit error counter > 255 3-2 tstat[1:0] transmitter status bits the values of the error counters control the actual can bus status of the mscan. as soon as the status change interrupt ?g (cscif) is set, these bits indicate the appropriate transmitter related can bus status of the mscan. the coding for the bits tstat1, tstat0 is: 00 txok: 0 transmit error counter 96 01 txwrn: 96 < transmit error counter 127 10 txerr: 127 < transmit error counter 255 11 bus-off: transmit error counter > 255
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 355 11.3.2.6 mscan receiver interrupt enable register (canrier) this register contains the interrupt enable bits for the interrupt ?gs described in the canrflg register. note the canrier register is held in the reset state when the initialization mode is active (initrq=1 and initak=1). this register is writable when not in initialization mode (initrq=0 and initak=0). the rstate[1:0], tstate[1:0] bits are not affected by initialization mode. 1 ovrif overrun interrupt flag this ?g is set when a data overrun condition occurs. if not masked, an error interrupt is pending while this ?g is set. 0 no data overrun condition 1 a data overrun detected 0 rxf (2) receive buffer full flag ?rxf is set by the mscan when a new message is shifted in the receiver fifo. this ?g indicates whether the shifted buffer is loaded with a correctly received message (matching identi?r, matching cyclic redundancy code (crc) and no other errors detected). after the cpu has read that message from the rxfg buffer in the receiver fifo, the rxf ?g must be cleared to release the buffer. a set rxf ?g prohibits the shifting of the next fifo entry into the foreground buffer (rxfg). if not masked, a receive interrupt is pending while this ?g is set. 0 no new message available within the rxfg 1 the receiver fifo is not empty. a new message is available in the rxfg 1. redundant information for the most critical can bus status which is ?us-off? this only occurs if the tx error counter exceeds a number of 255 errors. bus-off affects the receiver state. as soon as the transmitter leaves its bus-off state the receiver state skips to rxok too. refer also to tstat[1:0] coding in this register. 2. to ensure data integrity, do not read the receive buffer registers while the rxf ?g is cleared. for mcus with dual cpus, reading the receive buffer registers while the rxf ?g is cleared may result in a cpu fault condition. module base + 0x0005 access: user read/write (1) 1. read: anytime write: anytime when not in initialization mode 76543210 r wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie w reset: 00000000 figure 11-9. mscan receiver interrupt enable register (canrier) table 11-11. canrflg register field descriptions (continued) field description
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 356 freescale semiconductor 11.3.2.7 mscan transmitter flag register (cantflg) the transmit buffer empty ?gs each have an associated interrupt enable bit in the cantier register. table 11-12. canrier register field descriptions field description 7 wupie (1) 1. wupie and wupe (see section 11.3.2.1, ?scan control register 0 (canctl0) ? must both be enabled if the recovery mechanism from stop or wait is required. wake-up interrupt enable 0 no interrupt request is generated from this event. 1 a wake-up event causes a wake-up interrupt request. 6 cscie can status change interrupt enable 0 no interrupt request is generated from this event. 1 a can status change event causes an error interrupt request. 5-4 rstate[1:0] receiver status change enable these rstat enable bits control the sensitivity level in which receiver state changes are causing cscif interrupts. independent of the chosen sensitivity level the rstat ?gs continue to indicate the actual receiver state and are only updated if no cscif interrupt is pending. 00 do not generate any cscif interrupt caused by receiver state changes. 01 generate cscif interrupt only if the receiver enters or leaves ?us-off?state. discard other receiver state changes for generating cscif interrupt. 10 generate cscif interrupt only if the receiver enters or leaves ?xerr?or ?us-off (2) state. discard other receiver state changes for generating cscif interrupt. 11 generate cscif interrupt on all state changes. 2. bus-off state is only de?ed for transmitters by the can standard (see bosch can 2.0a/b protocol speci?ation). because the only possible state change for the transmitter from bus-off to txok also forces the receiver to skip its current state to rxok, the coding of the rxstat[1:0] ?gs de?e an additional bus-off state for the receiver (see section 11.3.2.5, ?scan receiver flag register (canrflg) ?. 3-2 tstate[1:0] transmitter status change enable these tstat enable bits control the sensitivity level in which transmitter state changes are causing cscif interrupts. independent of the chosen sensitivity level, the tstat ?gs continue to indicate the actual transmitter state and are only updated if no cscif interrupt is pending. 00 do not generate any cscif interrupt caused by transmitter state changes. 01 generate cscif interrupt only if the transmitter enters or leaves ?us-off?state. discard other transmitter state changes for generating cscif interrupt. 10 generate cscif interrupt only if the transmitter enters or leaves ?xerr?or ?us-off?state. discard other transmitter state changes for generating cscif interrupt. 11 generate cscif interrupt on all state changes. 1 ovrie overrun interrupt enable 0 no interrupt request is generated from this event. 1 an overrun event causes an error interrupt request. 0 rxfie receiver full interrupt enable 0 no interrupt request is generated from this event. 1 a receive buffer full (successful message reception) event causes a receiver interrupt request.
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 357 note the cantflg register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). 11.3.2.8 mscan transmitter interrupt enable register (cantier) this register contains the interrupt enable bits for the transmit buffer empty interrupt ?gs. module base + 0x0006 access: user read/write (1) 1. read: anytime write: anytime when not in initialization mode; write of 1 clears ?g, write of 0 is ignored 76543210 r0 0 0 00 txe2 txe1 txe0 w reset: 00000111 = unimplemented figure 11-10. mscan transmitter flag register (cantflg) table 11-13. cantflg register field descriptions field description 2-0 txe[2:0] transmitter buffer empty this ?g indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. the cpu must clear the ?g after a message is set up in the transmit buffer and is due for transmission. the mscan sets the ?g after the message is sent successfully. the ?g is also set by the mscan when the transmission request is successfully aborted due to a pending abort request (see section 11.3.2.9, ?scan transmitter message abort request register (cantarq) ?. if not masked, a transmit interrupt is pending while this ?g is set. clearing a txex ?g also clears the corresponding abtakx (see section 11.3.2.10, ?scan transmitter message abort acknowledge register (cantaak) ?. when a txex ?g is set, the corresponding abtrqx bit is cleared (see section 11.3.2.9, ?scan transmitter message abort request register (cantarq) ?. when listen-mode is active (see section 11.3.2.2, ?scan control register 1 (canctl1) ? the txex ?gs cannot be cleared and no transmission is started. read and write accesses to the transmit buffer will be blocked, if the corresponding txex bit is cleared (txex = 0) and the buffer is scheduled for transmission. 0 the associated message buffer is full (loaded with a message due for transmission) 1 the associated message buffer is empty (not scheduled) module base + 0x0007 access: user read/write (1) 76543210 r00000 txeie2 txeie1 txeie0 w reset: 00000000 = unimplemented figure 11-11. mscan transmitter interrupt enable register (cantier)
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 358 freescale semiconductor note the cantier register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). 11.3.2.9 mscan transmitter message abort request register (cantarq) the cantarq register allows abort request of queued messages as described below. note the cantarq register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). 1. read: anytime write: anytime when not in initialization mode table 11-14. cantier register field descriptions field description 2-0 txeie[2:0] transmitter empty interrupt enable 0 no interrupt request is generated from this event. 1 a transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request. module base + 0x0008 access: user read/write (1) 1. read: anytime write: anytime when not in initialization mode 76543210 r00000 abtrq2 abtrq1 abtrq0 w reset: 00000000 = unimplemented figure 11-12. mscan transmitter message abort request register (cantarq) table 11-15. cantarq register field descriptions field description 2-0 abtrq[2:0] abort request ?the cpu sets the abtrqx bit to request that a scheduled message buffer (txex = 0) be aborted. the mscan grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). when a message is aborted, the associated txe (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and abort acknowledge ?gs (abtak, see section 11.3.2.10, ?scan transmitter message abort acknowledge register (cantaak) ? are set and a transmit interrupt occurs if enabled. the cpu cannot reset abtrqx. abtrqx is reset whenever the associated txe ?g is set. 0 no abort request 1 abort request pending
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 359 11.3.2.10 mscan transmitter message abort acknowledge register (cantaak) the cantaak register indicates the successful abort of a queued message, if requested by the appropriate bits in the cantarq register. note the cantaak register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). 11.3.2.11 mscan transmit buffer selection register (cantbsel) the cantbsel register allows the selection of the actual transmit message buffer, which then will be accessible in the cantxfg register space. module base + 0x0009 access: user read/write (1) 1. read: anytime write: unimplemented 76543210 r00000 abtak2 abtak1 abtak0 w reset: 00000000 = unimplemented figure 11-13. mscan transmitter message abort acknowledge register (cantaak) table 11-16. cantaak register field descriptions field description 2-0 abtak[2:0] abort acknowledge ?this ?g acknowledges that a message was aborted due to a pending abort request from the cpu. after a particular message buffer is ?gged empty, this ?g can be used by the application software to identify whether the message was aborted successfully or was sent anyway. the abtakx ?g is cleared whenever the corresponding txe ?g is cleared. 0 the message was not aborted. 1 the message was aborted. module base + 0x000a access: user read/write (1) 1. read: find the lowest ordered bit set to 1, all other bits will be read as 0 write: anytime when not in initialization mode 76543210 r00000 tx2 tx1 tx0 w reset: 00000000 = unimplemented figure 11-14. mscan transmit buffer selection register (cantbsel)
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 360 freescale semiconductor note the cantbsel register is held in the reset state when the initialization mode is active (initrq = 1 and initak=1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). the following gives a short programming example of the usage of the cantbsel register: to get the next available transmit buffer, application software must read the cantflg register and write this value back into the cantbsel register. in this example tx buffers tx1 and tx2 are available. the value read from cantflg is therefore 0b0000_0110. when writing this value back to cantbsel, the tx buffer tx1 is selected in the cantxfg because the lowest numbered bit set to 1 is at bit position 1. reading back this value out of cantbsel results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. this mechanism eases the application softwares selection of the next available tx buffer. ldaa cantflg; value read is 0b0000_0110 staa cantbsel; value written is 0b0000_0110 ldaa cantbsel; value read is 0b0000_0010 if all transmit message buffers are deselected, no accesses are allowed to the cantxfg registers. 11.3.2.12 mscan identi?r acceptance control register (canidac) the canidac register is used for identi?r acceptance control as described below. table 11-17. cantbsel register field descriptions field description 2-0 tx[2:0] transmit buffer select ?the lowest numbered bit places the respective transmit buffer in the cantxfg register space (e.g., tx1 = 1 and tx0 = 1 selects transmit buffer tx0; tx1 = 1 and tx0 = 0 selects transmit buffer tx1). read and write accesses to the selected transmit buffer will be blocked, if the corresponding txex bit is cleared and the buffer is scheduled for transmission (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ?. 0 the associated message buffer is deselected 1 the associated message buffer is selected, if lowest numbered bit module base + 0x000b access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1), except bits idhitx, which are read-only 76543210 r0 0 idam1 idam0 0 idhit2 idhit1 idhit0 w reset: 00000000 = unimplemented figure 11-15. mscan identi?r acceptance control register (canidac)
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 361 the idhitx indicators are always related to the message in the foreground buffer (rxfg). when a message gets shifted into the foreground buffer of the receiver fifo the indicators are updated as well. 11.3.2.13 mscan reserved register this register is reserved for factory testing of the mscan module and is not available in normal system operating modes. table 11-18. canidac register field descriptions field description 5-4 idam[1:0] identi?r acceptance mode the cpu sets these ?gs to de?e the identi?r acceptance ?ter organization (see section 11.4.3, ?denti?r acceptance filter ?. table 11-19 summarizes the different settings. in ?ter closed mode, no message is accepted such that the foreground buffer is never reloaded. 2-0 idhit[2:0] identi?r acceptance hit indicator ?the mscan sets these ?gs to indicate an identi?r acceptance hit (see section 11.4.3, ?denti?r acceptance filter ?. table 11-20 summarizes the different settings. table 11-19. identi?r acceptance mode settings idam1 idam0 identi?r acceptance mode 0 0 two 32-bit acceptance ?ters 0 1 four 16-bit acceptance ?ters 1 0 eight 8-bit acceptance ?ters 1 1 filter closed table 11-20. identi?r acceptance hit indication idhit2 idhit1 idhit0 identi?r acceptance hit 0 0 0 filter 0 hit 0 0 1 filter 1 hit 0 1 0 filter 2 hit 0 1 1 filter 3 hit 1 0 0 filter 4 hit 1 0 1 filter 5 hit 1 1 0 filter 6 hit 1 1 1 filter 7 hit
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 362 freescale semiconductor note writing to this register when in special system operating modes can alter the mscan functionality. 11.3.2.14 mscan miscellaneous register (canmisc) this register provides additional features. 11.3.2.15 mscan receive error counter (canrxerr) this register re?cts the status of the mscan receive error counter. module base + 0x000c to module base + 0x000d access: user read/write (1) 1. read: always reads zero in normal system operation modes write: unimplemented in normal system operation modes 76543210 r00000000 w reset: 00000000 = unimplemented figure 11-16. mscan reserved register module base + 0x000d access: user read/write (1) 1. read: anytime write: anytime; write of ??clears ?g; write of ??ignored 76543210 r0000000 bohold w reset: 00000000 = unimplemented figure 11-17. mscan miscellaneous register (canmisc) table 11-21. canmisc register field descriptions field description 0 bohold bus-off state hold until user request ?if borm is set in mscan control register 1 (canctl1) , this bit indicates whether the module has entered the bus-off state. clearing this bit requests the recovery from bus-off. refer to section 11.5.2, ?us-off recovery , for details. 0 module is not bus-off or recovery has been requested by user in bus-off state 1 module is bus-off and holds this state until user request
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 363 note reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. for mcus with dual cpus, this may result in a cpu fault condition. writing to this register when in special modes can alter the mscan functionality. 11.3.2.16 mscan transmit error counter (cantxerr) this register re?cts the status of the mscan transmit error counter. note reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. for mcus with dual cpus, this may result in a cpu fault condition. writing to this register when in special modes can alter the mscan functionality. module base + 0x000e access: user read/write (1) 1. read: only when in sleep mode (slprq = 1 and slpak = 1) or initialization mode (initrq = 1 and initak = 1) write: unimplemented 76543210 r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 w reset: 00000000 = unimplemented figure 11-18. mscan receive error counter (canrxerr) module base + 0x000f access: user read/write (1) 1. read: only when in sleep mode (slprq = 1 and slpak = 1) or initialization mode (initrq = 1 and initak = 1) write: unimplemented 76543210 r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 w reset: 00000000 = unimplemented figure 11-19. mscan transmit error counter (cantxerr)
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 364 freescale semiconductor 11.3.2.17 mscan identi?r acceptance registers (canidar0-7) on reception, each message is written into the background receive buffer. the cpu is only signalled to read the message if it passes the criteria in the identi?r acceptance and identi?r mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). the acceptance registers of the mscan are applied on the idr0?dr3 registers (see section 11.3.3.1, ?denti?r registers (idr0?dr3) ? of incoming messages in a bit by bit manner (see section 11.4.3, ?denti?r acceptance filter ?. for extended identi?rs, all four acceptance and mask registers are applied. for standard identi?rs, only the ?st two (canidar0/1, canidmr0/1) are applied. module base + 0x0010 to module base + 0x0013 access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 76543210 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w reset 00000000 figure 11-20. mscan identi?r acceptance registers (first bank) ?canidar0?anidar3 table 11-22. canidar0?anidar3 register field descriptions field description 7-0 ac[7:0] acceptance code bits ac[7:0] comprise a user-de?ed sequence of bits with which the corresponding bits of the related identi?r register (idrn) of the receive message buffer are compared. the result of this comparison is then masked with the corresponding identi?r mask register. module base + 0x0018 to module base + 0x001b access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 76543210 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w reset 00000000 figure 11-21. mscan identi?r acceptance registers (second bank) ?canidar4?anidar7
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 365 11.3.2.18 mscan identi?r mask registers (canidmr0?anidmr7) the identi?r mask register speci?s which of the corresponding bits in the identi?r acceptance register are relevant for acceptance ?tering. to receive standard identi?rs in 32 bit ?ter mode, it is required to program the last three bits (am[2:0]) in the mask registers canidmr1 and canidmr5 to ?ont care. to receive standard identi?rs in 16 bit ?ter mode, it is required to program the last three bits (am[2:0]) in the mask registers canidmr1, canidmr3, canidmr5, and canidmr7 to ?ont care. table 11-23. canidar4?anidar7 register field descriptions field description 7-0 ac[7:0] acceptance code bits ac[7:0] comprise a user-de?ed sequence of bits with which the corresponding bits of the related identi?r register (idrn) of the receive message buffer are compared. the result of this comparison is then masked with the corresponding identi?r mask register. module base + 0x0014 to module base + 0x0017 access: user read/write (1) 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 00000000 figure 11-22. mscan identi?r mask registers (first bank) ?canidmr0?anidmr3 table 11-24. canidmr0?anidmr3 register field descriptions field description 7-0 am[7:0] acceptance mask bits if a particular bit in this register is cleared, this indicates that the corresponding bit in the identi?r acceptance register must be the same as its identi?r bit before a match is detected. the message is accepted if all such bits match. if a bit is set, it indicates that the state of the corresponding bit in the identi?r acceptance register does not affect whether or not the message is accepted. 0 match corresponding acceptance code register and identi?r bits 1 ignore corresponding acceptance code register bit module base + 0x001c to module base + 0x001f access: user read/write (1) 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 00000000 figure 11-23. mscan identi?r mask registers (second bank) ?canidmr4?anidmr7
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 366 freescale semiconductor 11.3.3 programmers model of message storage the following section details the organization of the receive and transmit message buffers and the associated control registers. to simplify the programmer interface, the receive and transmit message buffers have the same outline. each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure. an additional transmit buffer priority register (tbpr) is de?ed for the transmit buffers. within the last two bytes of this memory map, the mscan stores a special 16-bit time stamp, which is sampled from an internal timer after successful transmission or reception of a message. this feature is only available for transmit and receiver buffers, if the time bit is set (see section 11.3.2.1, ?scan control register 0 (canctl0) ?. the time stamp register is written by the mscan. the cpu can only read these registers. 1. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) table 11-25. canidmr4?anidmr7 register field descriptions field description 7-0 am[7:0] acceptance mask bits if a particular bit in this register is cleared, this indicates that the corresponding bit in the identi?r acceptance register must be the same as its identi?r bit before a match is detected. the message is accepted if all such bits match. if a bit is set, it indicates that the state of the corresponding bit in the identi?r acceptance register does not affect whether or not the message is accepted. 0 match corresponding acceptance code register and identi?r bits 1 ignore corresponding acceptance code register bit
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 367 figure 11-24 shows the common 13-byte data structure of receive and transmit buffers for extended identi?rs. the mapping of standard identi?rs into the idr registers is shown in figure 11-25 . all bits of the receive and transmit buffers are ??out of reset because of ram-based implementation 10 . all reserved or unused bits of the receive and transmit buffers always read ?? table 11-26. message buffer organization offset address register access 0x00x0 identi?r register 0 r/w 0x00x1 identi?r register 1 r/w 0x00x2 identi?r register 2 r/w 0x00x3 identi?r register 3 r/w 0x00x4 data segment register 0 r/w 0x00x5 data segment register 1 r/w 0x00x6 data segment register 2 r/w 0x00x7 data segment register 3 r/w 0x00x8 data segment register 4 r/w 0x00x9 data segment register 5 r/w 0x00xa data segment register 6 r/w 0x00xb data segment register 7 r/w 0x00xc data length register r/w 0x00xd transmit buffer priority register (1) 1. not applicable for receive buffers r/w 0x00xe time stamp register (high byte) r 0x00xf time stamp register (low byte) r 10. exception: the transmit buffer priority registers are 0 out of reset.
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 368 freescale semiconductor figure 11-24. receive/transmit message buffer ?extended identi?r mapping register name bit 7 654321 bit0 0x00x0 idr0 r id28 id27 id26 id25 id24 id23 id22 id21 w 0x00x1 idr1 r id20 id19 id18 srr (=1) ide (=1) id17 id16 id15 w 0x00x2 idr2 r id14 id13 id12 id11 id10 id9 id8 id7 w 0x00x3 idr3 r id6 id5 id4 id3 id2 id1 id0 rtr w 0x00x4 dsr0 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x5 dsr1 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x6 dsr2 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x7 dsr3 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x8 dsr4 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00x9 dsr5 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00xa dsr6 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00xb dsr7 r db7 db6 db5 db4 db3 db2 db1 db0 w 0x00xc dlr r dlc3 dlc2 dlc1 dlc0 w
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 369 read: for transmit buffers, anytime when txex ?g is set (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ?. for receive buffers, only when rxf ?g is set (see section 11.3.2.5, ?scan receiver flag register (canrflg) ?. write: for transmit buffers, anytime when txex ?g is set (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ?. unimplemented for receive buffers. reset: unde?ed because of ram-based implementation 11.3.3.1 identi?r registers (idr0?dr3) the identi?r registers for an extended format identi?r consist of a total of 32 bits: id[28:0], srr, ide, and rtr. the identi?r registers for a standard format identi?r consist of a total of 13 bits: id[10:0], rtr, and ide. = unused, always read ? figure 11-25. receive/transmit message buffer ?standard identi?r mapping register name bit 7 654321 bit 0 idr0 0x00x0 r id10 id9 id8 id7 id6 id5 id4 id3 w idr1 0x00x1 r id2 id1 id0 rtr ide (=0) w idr2 0x00x2 r w idr3 0x00x3 r w = unused, always read ? figure 11-24. receive/transmit message buffer ?extended identi?r mapping (continued) register name bit 7 654321 bit0
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 370 freescale semiconductor 11.3.3.1.1 idr0?dr3 for extended identi?r mapping module base + 0x00x0 76543210 r id28 id27 id26 id25 id24 id23 id22 id21 w reset: xxxxxxxx figure 11-26. identi?r register 0 (idr0) ?extended identi?r mapping table 11-27. idr0 register field descriptions ?extended field description 7-0 id[28:21] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. module base + 0x00x1 76543210 r id20 id19 id18 srr (=1) ide (=1) id17 id16 id15 w reset: xxxxxxxx figure 11-27. identi?r register 1 (idr1) ?extended identi?r mapping table 11-28. idr1 register field descriptions ?extended field description 7-5 id[20:18] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. 4 srr substitute remote request ?this ?ed recessive bit is used only in extended format. it must be set to 1 by the user for transmission buffers and is stored as received on the can bus for receive buffers. 3 ide id extended this ?g indicates whether the extended or standard identi?r format is applied in this buffer. in the case of a receive buffer, the ?g is set as received and indicates to the cpu how to process the buffer identi?r registers. in the case of a transmit buffer, the ?g indicates to the mscan what type of identi?r to send. 0 standard format (11 bit) 1 extended format (29 bit) 2-0 id[17:15] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number.
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 371 module base + 0x00x2 76543210 r id14 id13 id12 id11 id10 id9 id8 id7 w reset: xxxxxxxx figure 11-28. identi?r register 2 (idr2) ?extended identi?r mapping table 11-29. idr2 register field descriptions ?extended field description 7-0 id[14:7] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. module base + 0x00x3 76543210 r id6 id5 id4 id3 id2 id1 id0 rtr w reset: xxxxxxxx figure 11-29. identi?r register 3 (idr3) ?extended identi?r mapping table 11-30. idr3 register field descriptions ?extended field description 7-1 id[6:0] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. 0 rtr remote transmission request ?this ?g re?cts the status of the remote transmission request bit in the can frame. in the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. in the case of a transmit buffer, this ?g de?es the setting of the rtr bit to be sent. 0 data frame 1 remote frame
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 372 freescale semiconductor 11.3.3.1.2 idr0?dr3 for standard identi?r mapping module base + 0x00x0 76543210 r id10 id9 id8 id7 id6 id5 id4 id3 w reset: xxxxxxxx figure 11-30. identi?r register 0 ?standard mapping table 11-31. idr0 register field descriptions ?standard field description 7-0 id[10:3] standard format identi?r the identi?rs consist of 11 bits (id[10:0]) for the standard format. id10 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. see also id bits in table 11-32 . module base + 0x00x1 76543210 r id2 id1 id0 rtr ide (=0) w reset: xxxxxxxx = unused; always read ? figure 11-31. identi?r register 1 ?standard mapping table 11-32. idr1 register field descriptions field description 7-5 id[2:0] standard format identi?r the identi?rs consist of 11 bits (id[10:0]) for the standard format. id10 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. see also id bits in table 11-31 . 4 rtr remote transmission request this ?g re?cts the status of the remote transmission request bit in the can frame. in the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. in the case of a transmit buffer, this ?g de?es the setting of the rtr bit to be sent. 0 data frame 1 remote frame 3 ide id extended this ?g indicates whether the extended or standard identi?r format is applied in this buffer. in the case of a receive buffer, the ?g is set as received and indicates to the cpu how to process the buffer identi?r registers. in the case of a transmit buffer, the ?g indicates to the mscan what type of identi?r to send. 0 standard format (11 bit) 1 extended format (29 bit)
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 373 11.3.3.2 data segment registers (dsr0-7) the eight data segment registers, each with bits db[7:0], contain the data to be transmitted or received. the number of bytes to be transmitted or received is determined by the data length code in the corresponding dlr register. module base + 0x00x2 76543210 r w reset: xxxxxxxx = unused; always read ? figure 11-32. identi?r register 2 ?standard mapping module base + 0x00x3 76543210 r w reset: xxxxxxxx = unused; always read ? figure 11-33. identi?r register 3 ?standard mapping module base + 0x00x4 to module base + 0x00xb 76543210 r db7 db6 db5 db4 db3 db2 db1 db0 w reset: xxxxxxxx figure 11-34. data segment registers (dsr0?sr7) ?extended identi?r mapping table 11-33. dsr0?sr7 register field descriptions field description 7-0 db[7:0] data bits 7-0
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 374 freescale semiconductor 11.3.3.3 data length register (dlr) this register keeps the data length ?ld of the can frame. 11.3.3.4 transmit buffer priority register (tbpr) this register de?es the local priority of the associated message buffer. the local priority is used for the internal prioritization process of the mscan and is de?ed to be highest for the smallest binary number. the mscan implements the following internal prioritization mechanisms: all transmission buffers with a cleared txex ?g participate in the prioritization immediately before the sof (start of frame) is sent. module base + 0x00xc 76543210 r dlc3 dlc2 dlc1 dlc0 w reset: xxxxxxxx = unused; always read ? figure 11-35. data length register (dlr) ?extended identi?r mapping table 11-34. dlr register field descriptions field description 3-0 dlc[3:0] data length code bits the data length code contains the number of bytes (data byte count) of the respective message. during the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. the data byte count ranges from 0 to 8 for a data frame. table 11-35 shows the effect of setting the dlc bits. table 11-35. data length codes data length code data byte count dlc3 dlc2 dlc1 dlc0 00000 00011 00102 00113 01004 01015 01106 01117 10008
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 375 the transmission buffer with the lowest local priority ?ld wins the prioritization. in cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins. 11.3.3.5 time stamp register (tsrh?srl) if the time bit is enabled, the mscan will write a time stamp to the respective registers in the active transmit or receive buffer right after the eof of a valid message on the can bus (see section 11.3.2.1, ?scan control register 0 (canctl0) ?. in case of a transmission, the cpu can only read the time stamp after the respective transmit buffer has been ?gged empty. the timer value, which is used for stamping, is taken from a free running internal can bit clock. a timer overrun is not indicated by the mscan. the timer is reset (all bits set to 0) during initialization mode. the cpu can only read the time stamp registers. module base + 0x00xd access: user read/write (1) 1. read: anytime when txex ?g is set (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ? write: anytime when txex ?g is set (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ? 76543210 r prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 w reset: 00000000 figure 11-36. transmit buffer priority register (tbpr) module base + 0x00xe access: user read/write (1) 1. read: anytime when txex ?g is set (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ? write: unimplemented 76543210 r tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 w reset: xxxxxxxx figure 11-37. time stamp register ?high byte (tsrh)
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 376 freescale semiconductor module base + 0x00xf access: user read/write (1) 1. read: anytime when txex ?g is set (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ? write: unimplemented 76543210 r tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 w reset: xxxxxxxx figure 11-38. time stamp register ?low byte (tsrl)
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 377 11.4 functional description 11.4.1 general this section provides a complete functional description of the mscan. 11.4.2 message storage figure 11-39. user model for message buffer organization mscan rx0 rx1 can receive / transmit engine memory mapped i/o cpu bus mscan tx2 txe2 prio receiver transmitter rxbg txbg tx0 txe0 prio txbg tx1 prio txe1 txfg cpu bus rx2 rx3 rx4 rxf rxfg
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 378 freescale semiconductor the mscan facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 11.4.2.1 message transmit background modern application layer software is built upon two fundamental assumptions: any can node is able to send out a stream of scheduled messages without releasing the can bus between the two messages. such nodes arbitrate for the can bus immediately after sending the previous message and only release the can bus in case of lost arbitration. the internal message queue within any can node is organized such that the highest priority message is sent out ?st, if more than one message is ready to be sent. the behavior described in the bullets above cannot be achieved with a single transmit buffer. that buffer must be reloaded immediately after the previous message is sent. this loading process lasts a ?ite amount of time and must be completed within the inter-frame sequence (ifs) to be able to send an uninterrupted stream of messages. even if this is feasible for limited can bus speeds, it requires that the cpu reacts with short latencies to the transmit interrupt. a double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the cpu. problems can arise if the sending of a message is ?ished while the cpu re-loads the second buffer. no buffer would then be ready for transmission, and the can bus would be released. at least three transmit buffers are required to meet the ?st of the above requirements under all circumstances. the mscan has three transmit buffers. the second requirement calls for some sort of internal prioritization which the mscan implements with the ?ocal priority?concept described in section 11.4.2.2, ?ransmit structures . 11.4.2.2 transmit structures the mscan triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. the three buffers are arranged as shown in figure 11-39 . all three buffers have a 13-byte data structure similar to the outline of the receive buffers (see section 11.3.3, ?rogrammers model of message storage ?. an additional transmit buffer priority register (tbpr) contains an 8-bit local priority ?ld (prio) (see section 11.3.3.4, ?ransmit buffer priority register (tbpr) ?. the remaining two bytes are used for time stamping of a message, if required (see section 11.3.3.5, ?ime stamp register (tsrh?srl) ?. to transmit a message, the cpu must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (txex) ?g (see section 11.3.2.7, ?scan transmitter flag register (cantflg) ?. if a transmit buffer is available, the cpu must set a pointer to this buffer by writing to the cantbsel register (see section 11.3.2.11, ?scan transmit buffer selection register (cantbsel) ?. this makes the respective buffer accessible within the cantxfg address space (see section 11.3.3, ?rogrammers model of message storage ?. the algorithmic feature associated with the cantbsel register simpli?s the transmit buffer selection. in addition, this scheme makes the handler
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 379 software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. the cpu then stores the identi?r, the control bits, and the data content into one of the transmit buffers. finally, the buffer is ?gged as ready for transmission by clearing the associated txe ?g. the mscan then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated txe ?g. a transmit interrupt (see section 11.4.7.2, ?ransmit interrupt ? is generated 11 when txex is set and can be used to drive the application software to re-load the buffer. if more than one buffer is scheduled for transmission when the can bus becomes available for arbitration, the mscan uses the local priority setting of the three buffers to determine the prioritization. for this purpose, every transmit buffer has an 8-bit local priority ?ld (prio). the application software programs this ?ld when the message is set up. the local priority re?cts the priority of this particular message relative to the set of messages being transmitted from this node. the lowest binary value of the prio ?ld is de?ed to be the highest priority. the internal scheduling process takes place whenever the mscan arbitrates for the can bus. this is also the case after the occurrence of a transmission error. when a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers. because messages that are already in transmission cannot be aborted, the user must request the abort by setting the corresponding abort request bit (abtrq) (see section 11.3.2.9, ?scan transmitter message abort request register (cantarq) ?) the mscan then grants the request, if possible, by: 1. setting the corresponding abort acknowledge ?g (abtak) in the cantaak register. 2. setting the associated txe ?g to release the buffer. 3. generating a transmit interrupt. the transmit interrupt handler software can determine from the setting of the abtak ?g whether the message was aborted (abtak = 1) or sent (abtak = 0). 11.4.2.3 receive structures the received messages are stored in a ve stage input fifo. the ve message buffers are alternately mapped into a single memory area (see figure 11-39 ). the background receive buffer (rxbg) is exclusively associated with the mscan, but the foreground receive buffer (rxfg) is addressable by the cpu (see figure 11-39 ). this scheme simpli?s the handler software because only one address area is applicable for the receive process. all receive buffers have a size of 15 bytes to store the can control bits, the identi?r (standard or extended), the data contents, and a time stamp, if enabled (see section 11.3.3, ?rogrammers model of message storage ?. the receiver full ?g (rxf) (see section 11.3.2.5, ?scan receiver flag register (canrflg) ? signals the status of the foreground receive buffer. when the buffer contains a correctly received message with a matching identi?r, this ?g is set. on reception, each message is checked to see whether it passes the ?ter (see section 11.4.3, ?denti?r acceptance filter ? and simultaneously is written into the active rxbg. after successful reception of a valid message, the mscan shifts the content of rxbg into the receiver fifo, sets the rxf ?g, and 11. the transmit interrupt occurs only if not masked. a polling scheme can be applied on txex also.
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 380 freescale semiconductor generates a receive interrupt 12 (see section 11.4.7.3, ?eceive interrupt ? to the cpu. the users receive handler must read the received message from the rxfg and then reset the rxf ?g to acknowledge the interrupt and to release the foreground buffer. a new message, which can follow immediately after the ifs ?ld of the can frame, is received into the next available rxbg. if the mscan receives an invalid message in its rxbg (wrong identi?r, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. the buffer will then not be shifted into the fifo. when the mscan module is transmitting, the mscan receives its own transmitted messages into the background receive buffer, rxbg, but does not shift it into the receiver fifo, generate a receive interrupt, or acknowledge its own messages on the can bus. the exception to this rule is in loopback mode (see section 11.3.2.2, ?scan control register 1 (canctl1) ? where the mscan treats its own messages exactly like all other incoming messages. the mscan receives its own transmitted messages in the event that it loses arbitration. if arbitration is lost, the mscan must be prepared to become a receiver. an overrun condition occurs when all receive message buffers in the fifo are ?led with correctly received messages with accepted identi?rs and another message is correctly received from the can bus with an accepted identi?r. the latter message is discarded and an error interrupt with overrun indication is generated if enabled (see section 11.4.7.5, ?rror interrupt ?. the mscan remains able to transmit messages while the receiver fifo is being ?led, but all incoming messages are discarded. as soon as a receive buffer in the fifo is available again, new valid messages will be accepted. 11.4.3 identi?r acceptance filter the mscan identi?r acceptance registers (see section 11.3.2.12, ?scan identi?r acceptance control register (canidac) ? de?e the acceptable patterns of the standard or extended identi?r (id[10:0] or id[28:0]). any of these bits can be marked ?ont care?in the mscan identi?r mask registers (see section 11.3.2.18, ?scan identi?r mask registers (canidmr0?anidmr7) ?. a ?ter hit is indicated to the application software by a set receive buffer full ?g (rxf = 1) and three bits in the canidac register (see section 11.3.2.12, ?scan identi?r acceptance control register (canidac) ?. these identi?r hit ?gs (idhit[2:0]) clearly identify the ?ter section that caused the acceptance. they simplify the application softwares task to identify the cause of the receiver interrupt. if more than one hit occurs (two or more ?ters match), the lower hit has priority. a very ?xible programmable generic identi?r acceptance ?ter has been introduced to reduce the cpu interrupt loading. the ?ter is programmable to operate in four different modes: two identi?r acceptance ?ters, each to be applied to: the full 29 bits of the extended identi?r and to the following bits of the can 2.0b frame: remote transmission request (rtr) identi?r extension (ide) substitute remote request (srr) the 11 bits of the standard identi?r plus the rtr and ide bits of the can 2.0a/b messages. this mode implements two ?ters for a full length can 2.0b compliant extended identi?r. although this mode can be used for standard identi?rs, it is recommended to use the four or eight identi?r acceptance ?ters. 12. the receive interrupt occurs only if not masked. a polling scheme can be applied on rxf also.
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 381 figure 11-40 shows how the ?st 32-bit ?ter bank (canidar0?anidar3, canidmr0?anidmr3) produces a ?ter 0 hit. similarly, the second ?ter bank (canidar4?anidar7, canidmr4?anidmr7) produces a ?ter 1 hit. four identi?r acceptance ?ters, each to be applied to: the 14 most signi?ant bits of the extended identi?r plus the srr and ide bits of can 2.0b messages. the 11 bits of the standard identi?r, the rtr and ide bits of can 2.0a/b messages. figure 11-41 shows how the ?st 32-bit ?ter bank (canidar0?anidar3, canidmr0?anidmr3) produces ?ter 0 and 1 hits. similarly, the second ?ter bank (canidar4?anidar7, canidmr4?anidmr7) produces ?ter 2 and 3 hits. eight identi?r acceptance ?ters, each to be applied to the ?st 8 bits of the identi?r. this mode implements eight independent ?ters for the ?st 8 bits of a can 2.0a/b compliant standard identi?r or a can 2.0b compliant extended identi?r. figure 11-42 shows how the ?st 32-bit ?ter bank (canidar0?anidar3, canidmr0?anidmr3) produces ?ter 0 to 3 hits. similarly, the second ?ter bank (canidar4?anidar7, canidmr4?anidmr7) produces ?ter 4 to 7 hits. closed ?ter. no can message is copied into the foreground buffer rxfg, and the rxf ?g is never set. figure 11-40. 32-bit maskable identi?r acceptance filter id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 canidar0 am7 am0 canidmr0 ac7 ac0 canidar1 am7 am0 canidmr1 ac7 ac0 canidar2 am7 am0 canidmr2 ac7 ac0 canidar3 am7 am0 canidmr3 id accepted (filter 0 hit) can 2.0b extended identi?r can 2.0a/b standard identi?r
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 382 freescale semiconductor figure 11-41. 16-bit maskable identi?r acceptance filters id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 canidar0 am7 am0 canidmr0 ac7 ac0 canidar1 am7 am0 canidmr1 id accepted (filter 0 hit) ac7 ac0 canidar2 am7 am0 canidmr2 ac7 ac0 canidar3 am7 am0 canidmr3 id accepted (filter 1 hit) can 2.0b extended identi?r can 2.0a/b standard identi?r
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 383 figure 11-42. 8-bit maskable identi?r acceptance filters can 2.0b extended identi?r can 2.0a/b standard identi?r ac7 ac0 cidar3 am7 am0 cidmr3 id accepted (filter 3 hit) ac7 ac0 cidar2 am7 am0 cidmr2 id accepted (filter 2 hit) ac7 ac0 cidar1 am7 am0 cidmr1 id accepted (filter 1 hit) id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 cidar0 am7 am0 cidmr0 id accepted (filter 0 hit)
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 384 freescale semiconductor 11.4.3.1 protocol violation protection the mscan protects the user from accidentally violating the can protocol through programming errors. the protection logic implements the following features: the receive and transmit error counters cannot be written or otherwise manipulated. all registers which control the con?uration of the mscan cannot be modi?d while the mscan is on-line. the mscan has to be in initialization mode. the corresponding initrq/initak handshake bits in the canctl0/canctl1 registers (see section 11.3.2.1, ?scan control register 0 (canctl0) ? serve as a lock to protect the following registers: mscan control 1 register (canctl1) mscan bus timing registers 0 and 1 (canbtr0, canbtr1) mscan identi?r acceptance control register (canidac) mscan identi?r acceptance registers (canidar0?anidar7) mscan identi?r mask registers (canidmr0?anidmr7) the txcan is immediately forced to a recessive state when the mscan goes into the power down mode or initialization mode (see section 11.4.5.6, ?scan power down mode , and section 11.4.4.5, ?scan initialization mode ?. the mscan enable bit (cane) is writable only once in normal system operation modes, which provides further protection against inadvertently disabling the mscan. 11.4.3.2 clock system figure 11-43 shows the structure of the mscan clock generation circuitry. figure 11-43. mscan clocking scheme the clock source bit (clksrc) in the canctl1 register ( 11.3.2.2/11-349 ) de?es whether the internal canclk is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock. the clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the can protocol are met. additionally, for high can bus rates (1 mbps), a 45% to 55% duty cycle of the clock is required. if the bus clock is generated from a pll, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster can bus rates. bus clock oscillator clock mscan canclk clksrc clksrc prescaler (1 .. 64) time quanta clock (tq)
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 385 for microcontrollers without a clock and reset generator (crg), canclk is driven from the crystal oscillator (oscillator clock). a programmable prescaler generates the time quanta (tq) clock from canclk. a time quantum is the atomic unit of time handled by the mscan. eqn. 11-2 a bit time is subdivided into three segments as described in the bosch can 2.0a/b speci?ation. (see figure 11-44 ): sync_seg: this segment has a ?ed length of one time quantum. signal edges are expected to happen within this section. time segment 1: this segment includes the prop_seg and the phase_seg1 of the can standard. it can be programmed by setting the parameter tseg1 to consist of 4 to 16 time quanta. time segment 2: this segment represents the phase_seg2 of the can standard. it can be programmed by setting the tseg2 parameter to be 2 to 8 time quanta long. eqn. 11-3 figure 11-44. segments within the bit time tq f canclk prescaler value ( ) ---------------------------------------------------- -- = bit rate f tq number of time quanta () -------------------------------------------------------------------------------- - = sync_seg time segment 1 time segment 2 1 4 ... 16 2 ... 8 8 ... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + phase_seg1) (phase_seg2) transmit point
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 386 freescale semiconductor the synchronization jump width (see the bosch can 2.0a/b speci?ation for details) can be programmed in a range of 1 to 4 time quanta by setting the sjw parameter. the sync_seg, tseg1, tseg2, and sjw parameters are set by programming the mscan bus timing registers (canbtr0, canbtr1) (see section 11.3.2.3, ?scan bus timing register 0 (canbtr0) and section 11.3.2.4, ?scan bus timing register 1 (canbtr1) ?. table 11-37 gives an overview of the bosch can 2.0a/b speci?ation compliant segment settings and the related parameter values. note it is the users responsibility to ensure the bit time settings are in compliance with the can standard. 11.4.4 modes of operation 11.4.4.1 normal system operating modes the mscan module behaves as described within this speci?ation in all normal system operating modes. write restrictions exist for some registers. table 11-36. time segment syntax syntax description sync_seg system expects transitions to occur on the can bus during this period. transmit point a node in transmit mode transfers a new value to the can bus at this point. sample point a node in receive mode samples the can bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. table 11-37. bosch can 2.0a/b compliant bit time segment settings time segment 1 tseg1 time segment 2 tseg2 synchronization jump width sjw 5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1 4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2 5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3 6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3 7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3 8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3 9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 387 11.4.4.2 special system operating modes the mscan module behaves as described within this speci?ation in all special system operating modes. write restrictions which exist on speci? registers in normal modes are lifted for test purposes in special modes. 11.4.4.3 emulation modes in all emulation modes, the mscan module behaves just like in normal system operating modes as described within this speci?ation. 11.4.4.4 listen-only mode in an optional can bus monitoring mode (listen-only), the can node is able to receive valid data frames and valid remote frames, but it sends only ?ecessive?bits on the can bus. in addition, it cannot start a transmission. if the mac sub-layer is required to send a ?ominant bit (ack bit, overload ?g, or active error ?g), the bit is rerouted internally so that the mac sub-layer monitors this ?ominant?bit, although the can bus may remain in recessive state externally. 11.4.4.5 mscan initialization mode the mscan enters initialization mode when it is enabled (cane=1). when entering initialization mode during operation, any on-going transmission or reception is immediately aborted and synchronization to the can bus is lost, potentially causing can protocol violations. to protect the can bus system from fatal consequences of violations, the mscan immediately drives txcan into a recessive state. note the user is responsible for ensuring that the mscan is not active when initialization mode is entered. the recommended procedure is to bring the mscan into sleep mode (slprq = 1 and slpak = 1) before setting the initrq bit in the canctl0 register. otherwise, the abort of an on-going message can cause an error condition and can impact other can bus devices. in initialization mode, the mscan is stopped. however, interface registers remain accessible. this mode is used to reset the canctl0, canrflg, canrier, cantflg, cantier, cantarq, cantaak, and cantbsel registers to their default values. in addition, the mscan enables the con?uration of the canbtr0, canbtr1 bit timing registers; canidac; and the canidar, canidmr message ?ters. see section 11.3.2.1, ?scan control register 0 (canctl0) , for a detailed description of the initialization mode.
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 388 freescale semiconductor figure 11-45. initialization request/acknowledge cycle due to independent clock domains within the mscan, initrq must be synchronized to all domains by using a special handshake mechanism. this handshake causes additional synchronization delay (see figure 11-45 ). if there is no message transfer ongoing on the can bus, the minimum delay will be two additional bus clocks and three additional can clocks. when all parts of the mscan are in initialization mode, the initak ?g is set. the application software must use initak as a handshake indication for the request (initrq) to go into initialization mode. note the cpu cannot clear initrq before initialization mode (initrq = 1 and initak = 1) is active. 11.4.5 low-power options if the mscan is disabled (cane = 0), the mscan clocks are stopped for power saving. if the mscan is enabled (cane = 1), the mscan has two additional modes with reduced power consumption, compared to normal mode: sleep and power down mode. in sleep mode, power consumption is reduced by stopping all clocks except those to access the registers from the cpu side. in power down mode, all clocks are stopped and no power is consumed. table 11-38 summarizes the combinations of mscan and cpu modes. a particular combination of modes is entered by the given settings on the cswai and slprq/slpak bits. sync sync bus cloc k domain can cloc k domain cpu init request init flag initak flag initrq sync. initak sync. initrq initak
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 389 11.4.5.1 operation in run mode as shown in table 11-38 , only mscan sleep mode is available as low power option when the cpu is in run mode. 11.4.5.2 operation in wait mode the wai instruction puts the mcu in a low power consumption stand-by mode. if the cswai bit is set, additional power can be saved in power down mode because the cpu clocks are stopped. after leaving this power down mode, the mscan restarts and enters normal mode again. while the cpu is in wait mode, the mscan can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode). 11.4.5.3 operation in stop mode the stop instruction puts the mcu in a low power consumption stand-by mode. in stop mode, the mscan is set in power down mode regardless of the value of the slprq/slpak and cswai bits ( table 11-38 ). 11.4.5.4 mscan normal mode this is a non-power-saving mode. enabling the mscan puts the module from disabled mode into normal mode. in this mode the module can either be in initialization mode or out of initialization mode. see section 11.4.4.5, ?scan initialization mode ? table 11-38. cpu vs. mscan operating modes cpu mode mscan mode normal reduced power consumption sleep power down disabled (cane=0) run cswai = x (1) slprq = 0 slpak = 0 1. ??means don? care. cswai = x slprq = 1 slpak = 1 cswai = x slprq = x slpak = x wait cswai = 0 slprq = 0 slpak = 0 cswai = 0 slprq = 1 slpak = 1 cswai = 1 slprq = x slpak = x cswai = x slprq = x slpak = x stop cswai = x slprq = x slpak = x cswai = x slprq = x slpak = x
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 390 freescale semiconductor 11.4.5.5 mscan sleep mode the cpu can request the mscan to enter this low power mode by asserting the slprq bit in the canctl0 register. the time when the mscan enters sleep mode depends on a ?ed synchronization delay and its current activity: if there are one or more message buffers scheduled for transmission (txex = 0), the mscan will continue to transmit until all transmit message buffers are empty (txex = 1, transmitted successfully or aborted) and then goes into sleep mode. if the mscan is receiving, it continues to receive and goes into sleep mode as soon as the can bus next becomes idle. if the mscan is neither transmitting nor receiving, it immediately goes into sleep mode. figure 11-46. sleep request / acknowledge cycle note the application software must avoid setting up a transmission (by clearing one or more txex ?g(s)) and immediately request sleep mode (by setting slprq). whether the mscan starts transmitting or goes into sleep mode directly depends on the exact sequence of operations. if sleep mode is active, the slprq and slpak bits are set ( figure 11-46 ). the application software must use slpak as a handshake indication for the request (slprq) to go into sleep mode. when in sleep mode (slprq = 1 and slpak = 1), the mscan stops its internal clocks. however, clocks that allow register accesses from the cpu side continue to run. if the mscan is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. txcan remains in a recessive state. if rxf = 1, the message can be read and rxf can be cleared. shifting a new message into the foreground buffer of the receiver fifo (rxfg) does not take place while in sleep mode. it is possible to access the transmit buffers and to clear the associated txe ?gs. no message abort takes place while in sleep mode. sync sync bus cloc k domain can cloc k domain mscan in sleep mode cpu sleep request slprq flag slpak flag slprq sync. slpak sync. slprq slpak
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 391 if the wupe bit in canctl0 is not asserted, the mscan will mask any activity it detects on can. rxcan is therefore held internally in a recessive state. this locks the mscan in sleep mode. wupe must be set before entering sleep mode to take effect. the mscan is able to leave sleep mode (wake up) only when: can bus activity occurs and wupe = 1 or the cpu clears the slprq bit note the cpu cannot clear the slprq bit before sleep mode (slprq = 1 and slpak = 1) is active. after wake-up, the mscan waits for 11 consecutive recessive bits to synchronize to the can bus. as a consequence, if the mscan is woken-up by a can frame, this frame is not received. the receive message buffers (rxfg and rxbg) contain messages if they were received before sleep mode was entered. all pending actions will be executed upon wake-up; copying of rxbg into rxfg, message aborts and message transmissions. if the mscan remains in bus-off state after sleep mode was exited, it continues counting the 128 occurrences of 11 consecutive recessive bits. 11.4.5.6 mscan power down mode the mscan is in power down mode ( table 11-38 ) when cpu is in stop mode or cpu is in wait mode and the cswai bit is set when entering the power down mode, the mscan immediately stops all ongoing transmissions and receptions, potentially causing can protocol violations. to protect the can bus system from fatal consequences of violations to the above rule, the mscan immediately drives txcan into a recessive state. note the user is responsible for ensuring that the mscan is not active when power down mode is entered. the recommended procedure is to bring the mscan into sleep mode before the stop or wai instruction (if cswai is set) is executed. otherwise, the abort of an ongoing message can cause an error condition and impact other can bus devices. in power down mode, all clocks are stopped and no registers can be accessed. if the mscan was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. this causes some ?ed delay before the module enters normal mode again.
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 392 freescale semiconductor 11.4.5.7 disabled mode the mscan is in disabled mode out of reset (cane=0). all module clocks are stopped for power saving, however the register map can still be accessed as speci?d. 11.4.5.8 programmable wake-up function the mscan can be programmed to wake up from sleep or power down mode as soon as can bus activity is detected (see control bit wupe in mscan control register 0 (canctl0). the sensitivity to existing can bus action can be modi?d by applying a low-pass ?ter function to the rxcan input line (see control bit wupm in section 11.3.2.2, ?scan control register 1 (canctl1) ?. this feature can be used to protect the mscan from wake-up due to short glitches on the can bus lines. such glitches can result from?or example?lectromagnetic interference within noisy environments. 11.4.6 reset initialization the reset state of each individual bit is listed in section 11.3.2, ?egister descriptions , which details all the registers and their bit-?lds. 11.4.7 interrupts this section describes all interrupts originated by the mscan. it documents the enable bits and generated ?gs. each interrupt is listed and described separately. 11.4.7.1 description of interrupt operation the mscan supports four interrupt vectors (see table 11-39 ), any of which can be individually masked (for details see section 11.3.2.6, ?scan receiver interrupt enable register (canrier) ?to section 11.3.2.8, ?scan transmitter interrupt enable register (cantier) ?. refer to the device overview section to determine the dedicated interrupt vector addresses. 11.4.7.2 transmit interrupt at least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. the txex ?g of the empty message buffer is set. table 11-39. interrupt vectors interrupt source ccr mask local enable wake-up interrupt (wupif) i bit canrier (wupie) error interrupts interrupt (cscif, ovrif) i bit canrier (cscie, ovrie) receive interrupt (rxf) i bit canrier (rxfie) transmit interrupts (txe[2:0]) i bit cantier (txeie[2:0])
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 393 11.4.7.3 receive interrupt a message is successfully received and shifted into the foreground buffer (rxfg) of the receiver fifo. this interrupt is generated immediately after receiving the eof symbol. the rxf ?g is set. if there are multiple messages in the receiver fifo, the rxf ?g is set as soon as the next message is shifted to the foreground buffer. 11.4.7.4 wake-up interrupt a wake-up interrupt is generated if activity on the can bus occurs during mscan sleep or power-down mode. note this interrupt can only occur if the mscan was in sleep mode (slprq = 1 and slpak = 1) before entering power down mode, the wake-up option is enabled (wupe = 1), and the wake-up interrupt is enabled (wupie = 1). 11.4.7.5 error interrupt an error interrupt is generated if an overrun of the receiver fifo, error, warning, or bus-off condition occurrs. mscan receiver flag register (canrflg) indicates one of the following conditions: overrun an overrun condition of the receiver fifo as described in section 11.4.2.3, ?eceive structures , occurred. can status change ?the actual value of the transmit and receive error counters control the can bus state of the mscan. as soon as the error counters skip into a critical range (tx/rx- warning, tx/rx-error, bus-off) the mscan ?gs an error condition. the status change, which caused the error condition, is indicated by the tstat and rstat ?gs (see section 11.3.2.5, ?scan receiver flag register (canrflg) ?and section 11.3.2.6, ?scan receiver interrupt enable register (canrier) ?. 11.4.7.6 interrupt acknowledge interrupts are directly associated with one or more status ?gs in either the mscan receiver flag register (canrflg) or the mscan transmitter flag register (cantflg). interrupts are pending as long as one of the corresponding ?gs is set. the ?gs in canrflg and cantflg must be reset within the interrupt handler to handshake the interrupt. the ?gs are reset by writing a 1 to the corresponding bit position. a ?g cannot be cleared if the respective condition prevails. note it must be guaranteed that the cpu clears only the bit causing the current interrupt. for this reason, bit manipulation instructions (bset) must not be used to clear interrupt ?gs. these instructions may cause accidental clearing of interrupt ?gs which are set after entering the current interrupt service routine.
freescales scalable controller area network (s12mscanv3) mc9s12xhy-family reference manual, rev. 1.01 394 freescale semiconductor 11.5 initialization/application information 11.5.1 mscan initialization the procedure to initially start up the mscan module out of reset is as follows: 1. assert cane 2. write to the con?uration registers in initialization mode 3. clear initrq to leave initialization mode if the con?uration of registers which are only writable in initialization mode shall be changed: 1. bring the module into sleep mode by setting slprq and awaiting slpak to assert after the can bus becomes idle. 2. enter initialization mode: assert initrq and await initak 3. write to the con?uration registers in initialization mode 4. clear initrq to leave initialization mode and continue 11.5.2 bus-off recovery the bus-off recovery is user con?urable. the bus-off state can either be left automatically or on user request. for reasons of backwards compatibility, the mscan defaults to automatic recovery after reset. in this case, the mscan will become error active again after counting 128 occurrences of 11 consecutive recessive bits on the can bus (see the bosch can 2.0 a/b speci?ation for details). if the mscan is con?ured for user request (borm set in mscan control register 1 (canctl1)), the recovery from bus-off starts after both independent events have become true: 128 occurrences of 11 consecutive recessive bits on the can bus have been monitored bohold in mscan miscellaneous register (canmisc) has been cleared by the user these two events may occur in any order.
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 395 chapter 12 inter-integrated circuit (iicv3) block description table 12-1. revision history 12.1 introduction the inter-ic bus (iic) is a two-wire, bidirectional serial bus that provides a simple, ef?ient method of data exchange between devices. being a two-wire device, the iic bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. this bus is suitable for applications requiring occasional communications over a short distance between a number of devices. it also provides ?xibility, allowing additional devices to be connected to the bus for further expansion and system development. the interface is designed to operate up to 100 kbps with maximum bus loading and timing. the device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pf. 12.1.1 features the iic module has the following key features: compatible with i2c bus standard multi-master operation software programmable for one of 256 different serial clock frequencies software selectable acknowledge bit interrupt driven byte-by-byte data transfer arbitration lost interrupt with automatic mode switching from master to slave calling address identi?ation interrupt start and stop signal generation/detection repeated start signal generation revision number revision date sections affected description of changes v01.03 28 jul 2006 12.7.1.7/12-419 - update ?w-chart of interrupt routine for 10-bit address v01.04 17 nov 2006 12.3.1.2/12-399 - revise table1-5 rev. 1.01 14 aug 2007 12.3.1.1/12-399 - backward compatible for ibad bit name
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 396 freescale semiconductor acknowledge bit generation/detection bus busy detection general call address detection compliant to ten-bit address
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 397 12.1.2 modes of operation the iic functions the same in normal, special, and emulation modes. it has two low power modes: wait and stop modes. 12.1.3 block diagram the block diagram of the iic module is shown in figure 12-1 . figure 12-1. iic block diagram in/out data shift register address compare sda interrupt clock control start stop arbitration control scl bus_clock iic registers
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 398 freescale semiconductor 12.2 external signal description the iicv3 module has two external pins. 12.2.1 iic_scl ?serial clock line pin this is the bidirectional serial clock line (scl) of the module, compatible to the iic bus speci?ation. 12.2.2 iic_sda ?serial data line pin this is the bidirectional serial data line (sda) of the module, compatible to the iic bus speci?ation. 12.3 memory map and register de?ition this section provides a detailed description of all memory and registers for the iic module. 12.3.1 register descriptions this section consists of register descriptions in address order. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. register name bit 7 654321 bit 0 0x0000 ibad r adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 w 0x0001 ibfd r ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 w 0x0002 ibcr r iben ibie ms/ sl tx/ rx txak 00 ibswai w rsta 0x0003 ibsr r tcf iaas ibb ibal 0srw ibif rxak w 0x0004 ibdr r d7 d6 d5 d4 d3 d2 d1 d0 w 0x0005 ibcr2 r gcen adtype 000 adr10 adr9 adr8 w = unimplemented or reserved figure 12-2. iic register summary
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 399 12.3.1.1 iic address register (ibad) read and write anytime this register contains the address the iic bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer. 12.3.1.2 iic frequency divider register (ibfd) read and write anytime module base +0x0000 76543210 r adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 w reset 0 0 0 00000 = unimplemented or reserved figure 12-3. iic bus address register (ibad) table 12-2. ibad field descriptions field description 7:1 adr[7:1] slave address bit 1 to bit 7 contain the speci? slave address to be used by the iic bus module.the default mode of iic bus is slave mode for an address match on the bus. 0 reserved reserved ?bit 0 of the ibad is reserved for future compatibility. this bit will always read 0. module base + 0x0001 76543210 r ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 w reset 0 0 0 00000 = unimplemented or reserved figure 12-4. iic bus frequency divider register (ibfd) table 12-3. ibfd field descriptions field description 7:0 ibc[7:0] i bus clock rate 7:0 ?this ?ld is used to prescale the clock for bit rate selection. the bit clock generator is implemented as a prescale divider ibc7:6, prescaled shift register ibc5:3 select the prescaler divider and ibc2-0 select the shift register tap point. the ibc bits are decoded to give the tap and prescale values as shown in table 12-4 .
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 400 freescale semiconductor table 12-5. prescale divider encoding the number of clocks from the falling edge of scl to the ?st tap (tap[1]) is de?ed by the values shown in the scl2tap column of table 12-4 , all subsequent tap points are separated by 2 ibc5-3 as shown in the tap2tap column in table 12-5 . the scl tap is used to generated the scl period and the sda tap is used to determine the delay from the falling edge of scl to sda changing, the sda hold time. ibc7? de?es the multiplier factor mul. the values of mul are shown in the table 12-6 . table 12-4. i-bus tap and prescale values ibc2-0 (bin) scl tap (clocks) sda tap (clocks) 000 5 1 001 6 1 010 7 2 011 8 2 100 9 3 101 10 3 110 12 4 111 15 4 ibc5-3 (bin) scl2start (clocks) scl2stop (clocks) scl2tap (clocks) tap2tap (clocks) 0002741 0012742 0102964 0116968 100 14 17 14 16 101 30 33 30 32 110 62 65 62 64 111 126 129 126 128 table 12-6. multiplier factor ibc7-6 mul 00 01 01 02 10 04 11 reserved
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 401 figure 12-5. scl divider and sda hold the equation used to generate the divider values from the ibfd bits is: scl divider = mul x {2 x (scl2tap + [(scl_tap -1) x tap2tap] + 2)} the sda hold delay is equal to the cpu clock period multiplied by the sda hold value shown in table 12-7 . the equation used to generate the sda hold value from the ibfd bits is: sda hold = mul x {scl2tap + [(sda_tap - 1) x tap2tap] + 3} the equation for scl hold values to generate the start and stop conditions from the ibfd bits is: scl hold(start) = mul x [scl2start + (scl_tap - 1) x tap2tap] scl hold(stop) = mul x [scl2stop + (scl_tap - 1) x tap2tap] table 12-7. iic divider and hold values (sheet 1 of 6) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) mul=1 scl divider sda hold scl sda sda scl start condition stop condition scl hold(start) scl hold(stop)
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 402 freescale semiconductor 00 20/22 7 6 11 01 22/24 7 7 12 02 24/26 8 8 13 03 26/28 8 9 14 04 28/30 9 10 15 05 30/32 9 11 16 06 34/36 10 13 18 07 40/42 10 16 21 08 28/32 7 10 15 09 32/36 7 12 17 0a 36/40 9 14 19 0b 40/44 9 16 21 0c 44/48 11 18 23 0d 48/52 11 20 25 0e 56/60 13 24 29 0f 68/72 13 30 35 10 48 9 18 25 11 56 9 22 29 12 64 13 26 33 13 72 13 30 37 14 80 17 34 41 15 88 17 38 45 16 104 21 46 53 17 128 21 58 65 18 80 9 38 41 19 96 9 46 49 1a 112 17 54 57 1b 128 17 62 65 1c 144 25 70 73 1d 160 25 78 81 1e 192 33 94 97 1f 240 33 118 121 20 160 17 78 81 21 192 17 94 97 22 224 33 110 113 23 256 33 126 129 24 288 49 142 145 25 320 49 158 161 26 384 65 190 193 27 480 65 238 241 28 320 33 158 161 29 384 33 190 193 2a 448 65 222 225 2b 512 65 254 257 2c 576 97 286 289 table 12-7. iic divider and hold values (sheet 2 of 6) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 403 2d 640 97 318 321 2e 768 129 382 385 2f 960 129 478 481 30 640 65 318 321 31 768 65 382 385 32 896 129 446 449 33 1024 129 510 513 34 1152 193 574 577 35 1280 193 638 641 36 1536 257 766 769 37 1920 257 958 961 38 1280 129 638 641 39 1536 129 766 769 3a 1792 257 894 897 3b 2048 257 1022 1025 3c 2304 385 1150 1153 3d 2560 385 1278 1281 3e 3072 513 1534 1537 3f 3840 513 1918 1921 mul=2 40 40 14 12 22 41 44 14 14 24 42 48 16 16 26 43 52 16 18 28 44 56 18 20 30 45 60 18 22 32 46 68 20 26 36 47 80 20 32 42 48 56 14 20 30 49 64 14 24 34 4a 72 18 28 38 4b 80 18 32 42 4c 88 22 36 46 4d 96 22 40 50 4e 112 26 48 58 4f 136 26 60 70 50 96 18 36 50 51 112 18 44 58 52 128 26 52 66 53 144 26 60 74 54 160 34 68 82 55 176 34 76 90 56 208 42 92 106 57 256 42 116 130 58 160 18 76 82 table 12-7. iic divider and hold values (sheet 3 of 6) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 404 freescale semiconductor 59 192 18 92 98 5a 224 34 108 114 5b 256 34 124 130 5c 288 50 140 146 5d 320 50 156 162 5e 384 66 188 194 5f 480 66 236 242 60 320 34 156 162 61 384 34 188 194 62 448 66 220 226 63 512 66 252 258 64 576 98 284 290 65 640 98 316 322 66 768 130 380 386 67 960 130 476 482 68 640 66 316 322 69 768 66 380 386 6a 896 130 444 450 6b 1024 130 508 514 6c 1152 194 572 578 6d 1280 194 636 642 6e 1536 258 764 770 6f 1920 258 956 962 70 1280 130 636 642 71 1536 130 764 770 72 1792 258 892 898 73 2048 258 1020 1026 74 2304 386 1148 1154 75 2560 386 1276 1282 76 3072 514 1532 1538 77 3840 514 1916 1922 78 2560 258 1276 1282 79 3072 258 1532 1538 7a 3584 514 1788 1794 7b 4096 514 2044 2050 7c 4608 770 2300 2306 7d 5120 770 2556 2562 7e 6144 1026 3068 3074 7f 7680 1026 3836 3842 mul=4 80 72 28 24 44 81 80 28 28 48 82 88 32 32 52 83 96 32 36 56 84 104 36 40 60 table 12-7. iic divider and hold values (sheet 4 of 6) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 405 85 112 36 44 64 86 128 40 52 72 87 152 40 64 84 88 112 28 40 60 89 128 28 48 68 8a 144 36 56 76 8b 160 36 64 84 8c 176 44 72 92 8d 192 44 80 100 8e 224 52 96 116 8f 272 52 120 140 90 192 36 72 100 91 224 36 88 116 92 256 52 104 132 93 288 52 120 148 94 320 68 136 164 95 352 68 152 180 96 416 84 184 212 97 512 84 232 260 98 320 36 152 164 99 384 36 184 196 9a 448 68 216 228 9b 512 68 248 260 9c 576 100 280 292 9d 640 100 312 324 9e 768 132 376 388 9f 960 132 472 484 a0 640 68 312 324 a1 768 68 376 388 a2 896 132 440 452 a3 1024 132 504 516 a4 1152 196 568 580 a5 1280 196 632 644 a6 1536 260 760 772 a7 1920 260 952 964 a8 1280 132 632 644 a9 1536 132 760 772 aa 1792 260 888 900 ab 2048 260 1016 1028 ac 2304 388 1144 1156 ad 2560 388 1272 1284 ae 3072 516 1528 1540 af 3840 516 1912 1924 b0 2560 260 1272 1284 b1 3072 260 1528 1540 table 12-7. iic divider and hold values (sheet 5 of 6) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 406 freescale semiconductor note:since the bus frequency is speeding up,the scl divider could be expanded by it.therefore,in the table,when ibc[7:0] is from $00 to $0f,the scl divider is revised by the format value1/value2.value1 is the divider under the low frequency.value2 is the divider under the high frequency.how to select the divider depends on the bus frequency.when ibc[7:0] is from $10 to $bf,the divider is not changed. 12.3.1.3 iic control register (ibcr) read and write anytime b2 3584 516 1784 1796 b3 4096 516 2040 2052 b4 4608 772 2296 2308 b5 5120 772 2552 2564 b6 6144 1028 3064 3076 b7 7680 1028 3832 3844 b8 5120 516 2552 2564 b9 6144 516 3064 3076 ba 7168 1028 3576 3588 bb 8192 1028 4088 4100 bc 9216 1540 4600 4612 bd 10240 1540 5112 5124 be 12288 2052 6136 6148 bf 15360 2052 7672 7684 module base + 0x0002 76543210 r iben ibie ms/sl tx/rx txak 00 ibswai w rsta reset 0 0 0 00000 = unimplemented or reserved figure 12-6. iic bus control register (ibcr) table 12-7. iic divider and hold values (sheet 6 of 6) ibc[7:0] (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 407 wait mode is entered via execution of a cpu wai instruction. in the event that the ibswai bit is set, all clocks internal to the iic will be stopped and any transmission currently in progress will halt.if the cpu were woken up by a source other than the iic module, then clocks would restart and the iic would resume table 12-8. ibcr field descriptions field description 7 iben i-bus enable ?this bit controls the software reset of the entire iic bus module. 0 the module is reset and disabled. this is the power-on reset situation. when low the interface is held in reset but registers can be accessed 1 the iic bus module is enabled.this bit must be set before any other ibcr bits have any effect if the iic bus module is enabled in the middle of a byte transfer the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected. master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle may become corrupt. this would ultimately result in either the current bus master or the iic bus module losing arbitration, after which bus operation would return to normal. 6 ibie i-bus interrupt enable 0 interrupts from the iic bus module are disabled. note that this does not clear any currently pending interrupt condition 1 interrupts from the iic bus module are enabled. an iic bus interrupt occurs provided the ibif bit in the status register is also set. 5 ms/sl master/slave mode select bit upon reset, this bit is cleared. when this bit is changed from 0 to 1, a start signal is generated on the bus, and the master mode is selected. when this bit is changed from 1 to 0, a stop signal is generated and the operation mode changes from master to slave.a stop signal should only be generated if the ibif ?g is set. ms/ sl is cleared without generating a stop signal when the master loses arbitration. 0 slave mode 1 master mode 4 tx/rx transmit/receive mode select bit ?this bit selects the direction of master and slave transfers. when addressed as a slave this bit should be set by software according to the srw bit in the status register. in master mode this bit should be set according to the type of transfer required. therefore, for address cycles, this bit will always be high. 0 receive 1 transmit 3 txak transmit acknowledge enable this bit speci?s the value driven onto sda during data acknowledge cycles for both master and slave receivers. the iic module will always acknowledge address matches, provided it is enabled, regardless of the value of txak. note that values written to this bit are only used when the iic bus is a receiver, not a transmitter. 0 an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data 1 no acknowledge signal response is sent (i.e., acknowledge bit = 1) 2 rsta repeat start ?writing a 1 to this bit will generate a repeated start condition on the bus, provided it is the current bus master. this bit will always be read as a low. attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 generate repeat start cycle 1 reserved reserved ?bit 1 of the ibcr is reserved for future compatibility. this bit will always read 0. 0 ibswai i bus interface stop in wait mode 0 iic bus module clock operates normally 1 halt iic bus module clock generation in wait mode
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 408 freescale semiconductor from where was during the previous transmission. it is not possible for the iic to wake up the cpu when its internal clocks are stopped. if it were the case that the ibswai bit was cleared when the wai instruction was executed, the iic internal clocks and interface would remain alive, continuing the operation which was currently underway. it is also possible to con?ure the iic such that it will wake up the cpu via an interrupt at the conclusion of the current operation. see the discussion on the ibif and ibie bits in the ibsr and ibcr, respectively. 12.3.1.4 iic status register (ibsr) this status register is read-only with exception of bit 1 (ibif) and bit 4 (ibal), which are software clearable. module base + 0x0003 76543210 r tcf iaas ibb ibal 0srw ibif rxak w reset 1 0 0 00000 = unimplemented or reserved figure 12-7. iic bus status register (ibsr) table 12-9. ibsr field descriptions field description 7 tcf data transferring bit ?while one byte of data is being transferred, this bit is cleared. it is set by the falling edge of the 9th clock of a byte transfer. note that this bit is only valid during or immediately following a transfer to the iic module or from the iic module. 0 transfer in progress 1 transfer complete 6 iaas addressed as a slave bit when its own speci? address (i-bus address register) is matched with the calling address or it receives the general call address with gcen== 1,this bit is set.the cpu is interrupted provided the ibie is set.then the cpu needs to check the srw bit and set its tx/ rx mode accordingly.writing to the i-bus control register clears this bit. 0 not addressed 1 addressed as a slave 5 ibb bus busy bit 0 this bit indicates the status of the bus. when a start signal is detected, the ibb is set. if a stop signal is detected, ibb is cleared and the bus enters idle state. 1 bus is busy 4 ibal arbitration lost ?the arbitration lost bit (ibal) is set by hardware when the arbitration procedure is lost. arbitration is lost in the following circumstances: 1. sda sampled low when the master drives a high during an address or data transmit cycle. 2. sda sampled low when the master drives a high during the acknowledge bit of a data receive cycle. 3. a start cycle is attempted when the bus is busy. 4. a repeated start cycle is requested in slave mode. 5. a stop condition is detected when the master did not request it. this bit must be cleared by software, by writing a one to it. a write of 0 has no effect on this bit.
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 409 12.3.1.5 iic data i/o register (ibdr) in master transmit mode, when data is written to the ibdr a data transfer is initiated. the most signi?ant bit is sent ?st. in master receive mode, reading this register initiates next byte data receiving. in slave mode, the same functions are available after an address match has occurred.note that the tx/rx bit in the ibcr must correctly re?ct the desired direction of transfer in master and slave modes for the transmission to begin. for instance, if the iic is con?ured for master transmit but a master receive is desired, then reading the ibdr will not initiate the receive. reading the ibdr will return the last byte received while the iic is con?ured in either master receive or slave receive modes. the ibdr does not re?ct every byte that is transmitted on the iic bus, nor can software verify that a byte has been written to the ibdr correctly by reading it back. in master transmit mode, the ?st byte of data written to ibdr following assertion of ms/ sl is used for the address transfer and should com.prise of the calling address (in position d7:d1) concatenated with the required r/ w bit (in position d0). 3 reserved reserved ?bit 3 of ibsr is reserved for future use. a read operation on this bit will return 0. 2 srw slave read/write when iaas is set this bit indicates the value of the r/w command bit of the calling address sent from the master this bit is only valid when the i-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated. checking this bit, the cpu can select slave transmit/receive mode according to the command of the master. 0 slave receive, master writing to slave 1 slave transmit, master reading from slave 1 ibif i-bus interrupt ?the ibif bit is set when one of the following conditions occurs: ?arbitration lost (ibal bit set) ?data transfer complete (tcf bit set) ?addressed as slave (iaas bit set) it will cause a processor interrupt request if the ibie bit is set. this bit must be cleared by software, writing a one to it. a write of 0 has no effect on this bit. 0 rxak received acknowledge ?the value of sda during the acknowledge bit of a bus cycle. if the received acknowledge bit (rxak) is low, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. if rxak is high, it means no acknowledge signal is detected at the 9th clock. 0 acknowledge received 1 no acknowledge received module base + 0x0004 76543210 r d7 d6 d5 d4 d3 d2 d1 d0 w reset 0 0 0 00000 figure 12-8. iic bus data i/o register (ibdr) table 12-9. ibsr field descriptions (continued) field description
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 410 freescale semiconductor 12.3.1.6 iic control register 2(ibcr2) figure 12-9. iic bus control register 2(ibcr2) this register contains the variables used in general call and in ten-bit address. read and write anytime 12.4 functional description this section provides a complete functional description of the iicv3. 12.4.1 i-bus protocol the iic bus system uses a serial data line (sda) and a serial clock line (scl) for data transfer. all devices connected to it must have open drain or open collector outputs. logic and function is exercised on both lines with external pull-up resistors. the value of these resistors is system dependent. normally, a standard communication is composed of four parts: start signal, slave address transmission, data transfer and stop signal. they are described brie? in the following sections and illustrated in figure 12-10 . module base + 0x0005 76543210 r gcen adtype 000 adr10 adr9 adr8 w reset 0 0 0 00000 table 12-10. ibcr2 field descriptions field description 7 gcen general call enable . 0 general call is disabled. the module dont receive any general call data and address. 1 enable general call. it indicates that the module can receive address and any data. 6 adtype address type this bit selects the address length. the variable must be con?ured correctly before iic enters slave mode. 0 7-bit address 1 10-bit address 5,4,3 reserved reserved ?bit 5,4 and 3 of the ibcr2 are reserved for future compatibility. these bits will always read 0. 2:0 adr[10:8] slave address [10:8] ?hese 3 bits represent the msb of the 10-bit address when address type is asserted (adtype = 1).
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 411 figure 12-10. iic-bus transmission signals 12.4.1.1 start signal when the bus is free, i.e. no master device is engaging the bus (both scl and sda lines are at logical high), a master may initiate communication by sending a start signal.as shown in figure 12-10 , a start signal is de?ed as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. figure 12-11. start and stop conditions c l d a start signal ack bit 12345678 msb lsb 1 2 34 5 6 78 msb lsb no c l d a 1234567 8 msb lsb 12 5 678 msb lsb repeated 34 99 adr7 adr6 adr5 adr4adr3 adr2 adr1r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte adr7 adr6 adr5 adr4 adr3 adr2 adr1r/w adr7 adr6 adr5 adr4 adr3 adr2 adr1r/w new calling address 99 xx ack bit write start signal start signal ack bit calling address read/ write no ack bit read/ write sda scl start condition stop condition
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 412 freescale semiconductor 12.4.1.2 slave address transmission the ?st byte of data transfer immediately after the start signal is the slave address transmitted by the master. this is a seven-bit calling address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer. 1 = read transfer, the slave transmits data to the master. 0 = write transfer, the master transmits data to the slave. if the calling address is 10-bit, another byte is followed by the ?st byte.only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. this is done by pulling the sda low at the 9th clock (see figure 12-10 ). no two slaves in the system may have the same address. if the iic bus is master, it must not transmit an address that is equal to its own slave address. the iic bus cannot be master and slave at the same time.however, if arbitration is lost during an address cycle the iic bus will revert to slave mode and operate correctly even if it is being addressed by another master. 12.4.1.3 data transfer as soon as successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction speci?d by the r/w bit sent by the calling master all transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device. each data byte is 8 bits long. data may be changed only while scl is low and must be held stable while scl is high as shown in figure 12-10 . there is one clock pulse on scl for each data bit, the msb being transferred ?st. each data byte has to be followed by an acknowledge bit, which is signalled from the receiving device by pulling the sda low at the ninth clock. so one complete data byte transfer needs nine clock pulses. if the slave receiver does not acknowledge the master, the sda line must be left high by the slave. the master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. if the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the sda line for the master to generate stop or start signal.note in order to release the bus correctly,after no-acknowledge to the master,the slave must be immediately switched to receiver and a following dummy reading of the ibdr is necessary. 12.4.1.4 stop signal the master can terminate the communication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a calling command without generating a stop signal ?st. this is called repeated start. a stop signal is de?ed as a low-to-high transition of sda while scl at logical 1 (see figure 12-10 ). the master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus.
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 413 12.4.1.5 repeated start signal as shown in figure 12-10 , a repeated start signal is a start signal generated without ?st generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 12.4.1.6 arbitration procedure the inter-ic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. the relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. the losing masters immediately switch over to slave receive mode and stop driving sda output. in this case the transition from master to slave mode does not generate a stop condition. meanwhile, a status bit is set by hardware to indicate loss of arbitration. 12.4.1.7 clock synchronization because wire-and logic is performed on scl line, a high-to-low transition on scl line affects all the devices connected on the bus. the devices start counting their low period and as soon as a device's clock has gone low, it holds the scl line low until the clock high state is reached.however, the change of low to high in this device clock may not change the state of the scl line if another device clock is within its low period. therefore, synchronized clock scl is held low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 12-11 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no difference between the device clocks and the state of the scl line and all the devices start counting their high periods.the ?st device to complete its high period pulls the scl line low again. figure 12-12. iic-bus clock synchronization scl1 scl2 scl internal counter reset wait start counting high period
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 414 freescale semiconductor 12.4.1.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave devices may hold the scl low after completion of one byte transfer (9 bits). in such case, it halts the bus clock and forces the master clock into wait states until the slave releases the scl line. 12.4.1.9 clock stretching the clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low the slave can drive scl low for the required period and then release it.if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 12.4.1.10 ten-bit address a ten-bit address is indicated if the ?st 5 bits of the ?st address byte are 0x11110. the following rules apply to the ?st address byte. figure 12-13. de?ition of bits in the ?st byte . the address type is identi?d by adtype. when adtype is 0, 7-bit address is applied. reversely, the address is 10-bit address.generally, there are two cases of 10-bit address.see the figure 12-14 and figure 12-15 . figure 12-14. a master-transmitter addresses a slave-receiver with a 10-bit address figure 12-15. a master-receiver addresses a slave-transmitter with a 10-bit address. in the figure 12-15 , the ?st two bytes are the similar to figure 12-14 . after the repeated start(sr),the ?st slave address is transmitted again, but the r/w is 1, meaning that the slave is acted as a transmitter. slave address r/w bit description 0000000 0 general call address 0000010 x reserved for different bus format 0000011 x reserved for future purposes 11111xx x reserved for future purposes 11110xx x 10-bit slave addressing s slave add1st 7bits 11110+adr10+adr9 r/w 0 a1 slave add 2nd byte adr[8:1] a2 data a3 s slave add1st 7bits 11110+adr10+adr9 r/w 0 a1 slave add 2nd byte adr[8:1] a2 sr slave add 1st 7bits 11110+adr10+adr9 r/w 1 a3 data a4
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 415 12.4.1.11 general call address to broadcast using a general call, a device must ?st generate the general call address($00), then after receiving acknowledge, it must transmit data. in communication, as a slave device, provided the gcen is asserted, a device acknowledges the broadcast and receives data until the gcen is disabled or the master device releases the bus or generates a new transfer. in the broadcast, slaves always act as receivers. in general call, iaas is also used to indicate the address match. in order to distinguish whether the address match is the normal address match or the general call address match, ibdr should be read after the address byte has been received. if the data is $00, the match is general call address match. the meaning of the general call address is always speci?d in the ?st data byte and must be dealt with by s/w, the iic hardware does not decode and process the ?st data byte. when one byte transfer is done, the received data can be read from ibdr. the user can control the procedure by enabling or disabling gcen. 12.4.2 operation in run mode this is the basic mode of operation. 12.4.3 operation in wait mode iic operation in wait mode can be con?ured. depending on the state of internal bits, the iic can operate normally when the cpu is in wait mode or the iic clock generation can be turned off and the iic module enters a power conservation state during wait mode. in the later case, any transmission or reception in progress stops at wait mode entry. 12.4.4 operation in stop mode the iic is inactive in stop mode for reduced power consumption. the stop instruction does not affect iic register states. 12.5 resets the reset state of each individual bit is listed in section 12.3, ?emory map and register de?ition , which details the registers and their bit-?lds. 12.6 interrupts iicv3 uses only one interrupt vector. table 12-11. interrupt summary interrupt offset vector priority source description
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 416 freescale semiconductor internally there are three types of interrupts in iic. the interrupt service routine can determine the interrupt type by reading the status register. iic interrupt can be generated on 1. arbitration lost condition (ibal bit set) 2. byte transfer condition (tcf bit set) 3. address detect condition (iaas bit set) the iic interrupt is enabled by the ibie bit in the iic control register. it must be cleared by writing 0 to the ibf bit in the interrupt service routine. 12.7 application information 12.7.1 iic programming examples 12.7.1.1 initialization sequence reset will put the iic bus control register to its default status. before the interface can be used to transfer serial data, an initialization procedure must be carried out, as follows: 1. update the frequency divider register (ibfd) and select the required division ratio to obtain scl frequency from system clock. 2. update the adtype of ibcr2 to de?e the address length, 7 bits or 10 bits. 3. update the iic bus address register (ibad) to de?e its slave address. if 10-bit address is applied ibcr2 should be updated to de?e the rest bits of address. 4. set the iben bit of the iic bus control register (ibcr) to enable the iic interface system. 5. modify the bits of the iic bus control register (ibcr) to select master/slave mode, transmit/receive mode and interrupt enable or not. 6. if supported general call, the gcen in ibcr2 should be asserted. 12.7.1.2 generation of start after completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. if the device is connected to a multi-master bus system, the state of the iic bus busy bit (ibb) must be tested to check whether the serial bus is free. if the bus is free (ibb=0), the start condition and the ?st byte (the slave address) can be sent. the data written to the data register comprises the slave calling address and the lsb set to indicate the direction of transfer required from the slave. the bus free time (i.e., the time between a stop condition and the following start condition) is built into the hardware that generates the start cycle. depending on the relative frequencies of the system iic interrupt ibal, tcf, iaas bits in ibsr register when either of ibal, tcf or iaas bits is set may cause an interrupt based on arbitration lost, transfer complete or address detect conditions
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 417 clock and the scl period it may be necessary to wait until the iic is busy after writing the calling address to the ibdr before proceeding with the following instructions. this is illustrated in the following example. an example of a program which generates the start signal and transmits the ?st byte of data (slave address) is shown below: 12.7.1.3 post-transfer software response transmission or reception of a byte will set the data transferring bit (tcf) to 1, which indicates one byte communication is ?ished. the iic bus interrupt bit (ibif) is set also; an interrupt will be generated if the interrupt function is enabled during initialization by setting the ibie bit. software must clear the ibif bit in the interrupt routine ?st. the tcf bit will be cleared by reading from the iic bus data i/o register (ibdr) in receive mode or writing to ibdr in transmit mode. software may service the iic i/o in the main program by monitoring the ibif bit if the interrupt function is disabled. note that polling should monitor the ibif bit rather than the tcf bit because their operation is different when arbitration is lost. note that when an interrupt occurs at the end of the address cycle the master will always be in transmit mode, i.e. the address is transmitted. if master receive mode is required, indicated by r/w bit in ibdr, then the tx/rx bit should be toggled at this stage. during slave mode address cycles (iaas=1), the srw bit in the status register is read to determine the direction of the subsequent transfer and the tx/rx bit is programmed accordingly.for slave mode data cycles (iaas=0) the srw bit is not valid, the tx/rx bit in the control register should be read to determine the direction of the current transfer. the following is an example of a software response by a 'master transmitter' in the interrupt routine. 12.7.1.4 generation of stop a data transfer ends with a stop signal generated by the 'master' device. a master transmitter can simply generate a stop signal after all the data has been transmitted. the following is an example showing how a stop condition is generated by a master transmitter. chflag brset ibsr,#$20,* ;wait for ibb flag to clear txstart bset ibcr,#$30 ;set transmit and master mode;i.e. generate start condition movb calling,ibdr ;transmit the calling address, d0=r/w ibfree brclr ibsr,#$20,* ;wait for ibb flag to set isr bclr ibsr,#$02 ;clear the ibif flag brclr ibcr,#$20,slave ;branch if in slave mode brclr ibcr,#$10,receive ;branch if in receive mode brset ibsr,#$01,end ;if no ack, end of transmission transmit movb databuf,ibdr ;transmit next byte of data
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 418 freescale semiconductor if a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (txak) before reading the 2nd last byte of data. before reading the last byte of data, a stop signal must be generated ?st. the following is an example showing how a stop signal is generated by a master receiver. 12.7.1.5 generation of repeated start at the end of data transfer, if the master continues to want to communicate on the bus, it can generate another start signal followed by another slave address without ?st generating a stop signal. a program example is as shown. 12.7.1.6 slave mode in the slave interrupt service routine, the module addressed as slave bit (iaas) should be tested to check if a calling of its own address has just been received. if iaas is set, software should set the transmit/receive mode select bit (tx/rx bit of ibcr) according to the r/w command bit (srw). writing to the ibcr clears the iaas automatically. note that the only time iaas is read as set is from the interrupt at the end of the address cycle where an address match occurred, interrupts resulting from subsequent data transfers will have iaas cleared. a data transfer may now be initiated by writing information to ibdr, for slave transmits, or dummy reading from ibdr, in slave receive mode. the slave will drive scl low in-between byte transfers, scl is released when the ibdr is accessed in the required mode. in slave transmitter routine, the received acknowledge bit (rxak) must be tested before transmitting the next byte of data. setting rxak means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. a dummy read then releases the scl line so that the master can generate a stop signal. mastx tst txcnt ;get value from the transmiting counter beq end ;end if no more data brset ibsr,#$01,end ;end if no ack movb databuf,ibdr ;transmit next byte of data dec txcnt ;decrease the txcnt bra emastx ;exit end bclr ibcr,#$20 ;generate a stop condition emastx rti ;return from interrupt masr dec rxcnt ;decrease the rxcnt beq enmasr ;last byte to be read movb rxcnt,d1 ;check second last byte dec d1 ;to be read bne nxmar ;not last or second last lamar bset ibcr,#$08 ;second last, disable ack ;transmitting bra nxmar enmasr bclr ibcr,#$20 ;last one, generate ?top?signal nxmar movb ibdr,rxbuf ;read data and store rti restart bset ibcr,#$04 ;another start (restart) movb calling,ibdr ;transmit the calling address;d0=r/w
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 419 12.7.1.7 arbitration lost if several masters try to engage the bus simultaneously, only one master wins and the others lose arbitration. the devices which lost arbitration are immediately switched to slave receive mode by the hardware. their data output to the sda line is stopped, but scl continues to be generated until the end of the byte during which arbitration was lost. an interrupt occurs at the falling edge of the ninth clock of this transfer with ibal=1 and ms/sl=0. if one master attempts to start transmission while the bus is being engaged by another master, the hardware will inhibit the transmission; switch the ms/sl bit from 1 to 0 without generating stop condition; generate an interrupt to cpu and set the ibal to indicate that the attempt to engage the bus is failed. when considering these cases, the slave service routine should test the ibal ?st and the software should clear the ibal bit if it is set.
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 420 freescale semiconductor figure 12-16. flow-chart of typical iic interrupt routine clear master mode ? tx/rx ? last byte transmitted ? rxak=0 ? end of addr cycle (master rx) ? write next byte to ibdr switch to rx mode dummy read from ibdr generate stop signal read data from ibdr and store set txak =1 generate stop signal 2nd last byte to be read ? last byte to be read ? arbitration lost ? clear ibal iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to ibdr set rx mode dummy read from ibdr ack from receiver ? tx next byte read data from ibdr and store switch to rx mode dummy read from ibdr rti yn y y y y y y y n n n n n n n n y tx rx rx tx (write) (read) n ibif data transfer y y 10-bit address? n n 7-bit address transfer y 10-bit address transfer mode set rx dummy read from ibdr n set tx mode write data to ibdr y ibdr== 11110xx1?
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 421 caution:when iic is con?ured as 10-bit address,the point of the data array in interrupt routine must be reset after its addressed.
inter-integrated circuit (iicv3) block description mc9s12xhy-family reference manual, rev. 1.01 422 freescale semiconductor
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 423 chapter 13 pulse-width modulator (s12pwm8b8cv1) 13.1 introduction the pwm de?ition is based on the hc12 pwm de?itions. it contains the basic features from the hc11 with some of the enhancements incorporated on the hc12: center aligned output mode and four available clock sources.the pwm module has eight channels with independent control of left and center aligned outputs on each channel. each of the eight channels has a programmable period and duty cycle as well as a dedicated counter. a ?xible clock select scheme allows a total of four different clock sources to be used with the counters. each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. the pwm outputs can be programmed as left aligned outputs or center aligned outputs. 13.1.1 features the pwm block includes these distinctive features: eight independent pwm channels with programmable period and duty cycle dedicated counter for each pwm channel programmable pwm enable/disable for each channel software selection of pwm duty pulse polarity for each channel period and duty cycle are double buffered. change takes effect when the end of the effective period is reached (pwm counter reaches zero) or when the channel is disabled. programmable center or left aligned outputs on individual channels eight 8-bit channel or four 16-bit channel pwm resolution four clock sources (a, b, sa, and sb) provide for a wide range of frequencies programmable clock select logic emergency shutdown 13.1.2 modes of operation there is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. in freeze mode there is a software programmable option to disable the input clock to the prescaler. this is useful for emulation.
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 424 freescale semiconductor 13.1.3 block diagram figure 13-1 shows the block diagram for the 8-bit 8-channel pwm block. figure 13-1. pwm block diagram 13.2 external signal description the pwm module has a total of 8 external pins. 13.2.1 pwm7 ?pwm channel 7 this pin serves as waveform output of pwm channel 7 and as an input for the emergency shutdown feature. 13.2.2 pwm6 ?pwm channel 6 this pin serves as waveform output of pwm channel 6. period and duty counter channel 6 clock select pwm clock period and duty counter channel 5 period and duty counter channel 4 period and duty counter channel 3 period and duty counter channel 2 period and duty counter channel 1 alignment polarity control pwm8b8c pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 enable pwm channels period and duty counter channel 7 period and duty counter channel 0 pwm0 pwm7 bus clock
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 425 13.2.3 pwm5 ?pwm channel 5 this pin serves as waveform output of pwm channel 5. 13.2.4 pwm4 ?pwm channel 4 this pin serves as waveform output of pwm channel 4. 13.2.5 pwm3 ?pwm channel 3 this pin serves as waveform output of pwm channel 3. 13.2.6 pwm3 ?pwm channel 2 this pin serves as waveform output of pwm channel 2. 13.2.7 pwm3 ?pwm channel 1 this pin serves as waveform output of pwm channel 1. 13.2.8 pwm3 ?pwm channel 0 this pin serves as waveform output of pwm channel 0. 13.3 memory map and register de?ition this section describes in detail all the registers and register bits in the pwm module. the special-purpose registers and register bit functions that are not normally available to device end users, such as factory test control registers and reserved registers, are clearly identi?d by means of shading the appropriate portions of address maps and register diagrams. notes explaining the reasons for restricting access to the registers and functions are also explained in the individual register descriptions. 13.3.1 module memory map this section describes the content of the registers in the pwm module. the base address of the pwm module is determined at the mcu level when the mcu is de?ed. the register decode map is ?ed and begins at the ?st address of the module address offset. the ?ure below shows the registers associated with the pwm and their relative offset from the base address. the register detail description follows the order they appear in the register map. reserved bits within a register will always read as 0 and the write will be unimplemented. unimplemented functions are indicated by shading the bit. .
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 426 freescale semiconductor note register address = base address + address offset, where the base address is de?ed at the mcu level and the address offset is de?ed at the module level. 13.3.2 register descriptions this section describes in detail all the registers and register bits in the pwm module. register name bit 7 6 5 4 3 2 1 bit 0 0x0000 pwme r pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w 0x0001 pwmpol r ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w 0x0002 pwmclk r pclk7 pclkl6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 w 0x0003 pwmprclk r0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w 0x0004 pwmcae r cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 w 0x0005 pwmctl r con67 con45 con23 con01 pswai pfrz 00 w 0x0006 pwmtst 1 r00 0 00000 w 0x0007 pwmprsc 1 r00 0 00000 w 0x0008 pwmscla r bit 7 6 5 4 3 2 1 bit 0 w 0x0009 pwmsclb r bit 7 6 5 4 3 2 1 bit 0 w 0x000a pwmscnta 1 r00 0 00000 w = unimplemented or reserved figure 13-2. pwm register summary (sheet 1 of 3)
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 427 0x000b pwmscntb 1 r00 0 00000 w 0x000c pwmcnt0 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x000d pwmcnt1 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x000e pwmcnt2 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x000f pwmcnt3 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x0010 pwmcnt4 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x0011 pwmcnt5 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x0012 pwmcnt6 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x0013 pwmcnt7 r bit 7 6 5 4 3 2 1 bit 0 w00 0 00000 0x0014 pwmper0 r bit 7 6 5 4 3 2 1 bit 0 w 0x0015 pwmper1 r bit 7 6 5 4 3 2 1 bit 0 w 0x0016 pwmper2 r bit 7 6 5 4 3 2 1 bit 0 w 0x0017 pwmper3 r bit 7 6 5 4 3 2 1 bit 0 w 0x0018 pwmper4 r bit 7 6 5 4 3 2 1 bit 0 w 0x0019 pwmper5 r bit 7 6 5 4 3 2 1 bit 0 w register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 13-2. pwm register summary (sheet 2 of 3)
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 428 freescale semiconductor 13.3.2.1 pwm enable register (pwme) each pwm channel has an enable bit (pwmex) to start its waveform output. when any of the pwmex bits are set (pwmex = 1), the associated pwm output is enabled immediately. however, the actual pwm waveform is not available on the associated pwm output until its clock source begins its next cycle due to the synchronization of pwmex and the clock source. note the ?st pwm cycle after enabling the channel can be irregular. 0x001a pwmper6 r bit 7 6 5 4 3 2 1 bit 0 w 0x001b pwmper7 r bit 7 6 5 4 3 2 1 bit 0 w 0x001c pwmdty0 r bit 7 6 5 4 3 2 1 bit 0 w 0x001d pwmdty1 r bit 7 6 5 4 3 2 1 bit 0 w 0x001e pwmdty2 r bit 7 6 5 4 3 2 1 bit 0 w 0x001f pwmdty3 r bit 7 6 5 4 3 2 1 bit 0 w 0x0010 pwmdty4 r bit 7 6 5 4 3 2 1 bit 0 w 0x0021 pwmdty5 r bit 7 6 5 4 3 2 1 bit 0 w 0x0022 pwmdty6 r bit 7 6 5 4 3 2 1 bit 0 w 0x0023 pwmdty7 r bit 7 6 5 4 3 2 1 bit 0 w 0x0024 pwmsdn r pwmif pwmie 0 pwmlvl 0 pwm7in pwm7inl pwm7ena w pwmrstrt 1 intended for factory test purposes only. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented or reserved figure 13-2. pwm register summary (sheet 3 of 3)
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 429 an exception to this is when channels are concatenated. once concatenated mode is enabled (conxx bits set in pwmctl register), enabling/disabling the corresponding 16-bit pwm channel is controlled by the low order pwmex bit.in this case, the high order bytes pwmex bits have no effect and their corresponding pwm output lines are disabled. while in run mode, if all eight pwm channels are disabled (pwme7? = 0), the prescaler counter shuts off for power savings. read: anytime write: anytime module base + 0x0000 76543210 r pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w reset 0 0 0 00000 figure 13-3. pwm enable register (pwme) table 13-1. pwme field descriptions field description 7 pwme7 pulse width channel 7 enable 0 pulse width channel 7 is disabled. 1 pulse width channel 7 is enabled. the pulse modulated signal becomes available at pwm output bit 7 when its clock source begins its next cycle. 6 pwme6 pulse width channel 6 enable 0 pulse width channel 6 is disabled. 1 pulse width channel 6 is enabled. the pulse modulated signal becomes available at pwm output bit6 when its clock source begins its next cycle. if con67=1, then bit has no effect and pwm output line 6 is disabled. 5 pwme5 pulse width channel 5 enable 0 pulse width channel 5 is disabled. 1 pulse width channel 5 is enabled. the pulse modulated signal becomes available at pwm output bit 5 when its clock source begins its next cycle. 4 pwme4 pulse width channel 4 enable 0 pulse width channel 4 is disabled. 1 pulse width channel 4 is enabled. the pulse modulated signal becomes available at pwm, output bit 4 when its clock source begins its next cycle. if con45 = 1, then bit has no effect and pwm output bit4 is disabled. 3 pwme3 pulse width channel 3 enable 0 pulse width channel 3 is disabled. 1 pulse width channel 3 is enabled. the pulse modulated signal becomes available at pwm, output bit 3 when its clock source begins its next cycle. 2 pwme2 pulse width channel 2 enable 0 pulse width channel 2 is disabled. 1 pulse width channel 2 is enabled. the pulse modulated signal becomes available at pwm, output bit 2 when its clock source begins its next cycle. if con23 = 1, then bit has no effect and pwm output bit2 is disabled.
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 430 freescale semiconductor 13.3.2.2 pwm polarity register (pwmpol) the starting polarity of each pwm channel waveform is determined by the associated ppolx bit in the pwmpol register. if the polarity bit is one, the pwm channel output is high at the beginning of the cycle and then goes low when the duty count is reached. conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. read: anytime write: anytime note ppolx register bits can be written anytime. if the polarity is changed while a pwm signal is being generated, a truncated or stretched pulse can occur during the transition 13.3.2.3 pwm clock select register (pwmclk) each pwm channel has a choice of two clocks to use as the clock source for that channel as described below. 1 pwme1 pulse width channel 1 enable 0 pulse width channel 1 is disabled. 1 pulse width channel 1 is enabled. the pulse modulated signal becomes available at pwm, output bit 1 when its clock source begins its next cycle. 0 pwme0 pulse width channel 0 enable 0 pulse width channel 0 is disabled. 1 pulse width channel 0 is enabled. the pulse modulated signal becomes available at pwm, output bit 0 when its clock source begins its next cycle. if con01 = 1, then bit has no effect and pwm output line0 is disabled. module base + 0x0001 76543210 r ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w reset 0 0 0 00000 figure 13-4. pwm polarity register (pwmpol) table 13-2. pwmpol field descriptions field description 7? ppol[7:0] p ulse width channel 7? polarity bits 0 pwm channel 7? outputs are low at the beginning of the period, then go high when the duty count is reached. 1 pwm channel 7? outputs are high at the beginning of the period, then go low when the duty count is reached. table 13-1. pwme field descriptions (continued) field description
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 431 read: anytime write: anytime note register bits pclk0 to pclk7 can be written anytime. if a clock select is changed while a pwm signal is being generated, a truncated or stretched pulse can occur during the transition. 13.3.2.4 pwm prescale clock select register (pwmprclk) this register selects the prescale clock source for clocks a and b independently. module base + 0x0002 76543210 r pclk7 pclkl6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 w reset 0 0 0 00000 figure 13-5. pwm clock select register (pwmclk) table 13-3. pwmclk field descriptions field description 7 pclk7 pulse width channel 7 clock select 0 clock b is the clock source for pwm channel 7. 1 clock sb is the clock source for pwm channel 7. 6 pclk6 pulse width channel 6 clock select 0 clock b is the clock source for pwm channel 6. 1 clock sb is the clock source for pwm channel 6. 5 pclk5 pulse width channel 5 clock select 0 clock a is the clock source for pwm channel 5. 1 clock sa is the clock source for pwm channel 5. 4 pclk4 pulse width channel 4 clock select 0 clock a is the clock source for pwm channel 4. 1 clock sa is the clock source for pwm channel 4. 3 pclk3 pulse width channel 3 clock select 0 clock b is the clock source for pwm channel 3. 1 clock sb is the clock source for pwm channel 3. 2 pclk2 pulse width channel 2 clock select 0 clock b is the clock source for pwm channel 2. 1 clock sb is the clock source for pwm channel 2. 1 pclk1 pulse width channel 1 clock select 0 clock a is the clock source for pwm channel 1. 1 clock sa is the clock source for pwm channel 1. 0 pclk0 pulse width channel 0 clock select 0 clock a is the clock source for pwm channel 0. 1 clock sa is the clock source for pwm channel 0.
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 432 freescale semiconductor read: anytime write: anytime note pckb2? and pcka2? register bits can be written anytime. if the clock pre-scale is changed while a pwm signal is being generated, a truncated or stretched pulse can occur during the transition. s module base + 0x0003 76543210 r0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w reset 0 0 0 00000 = unimplemented or reserved figure 13-6. pwm prescale clock select register (pwmprclk) table 13-4. pwmprclk field descriptions field description 6? pckb[2:0] prescaler select for clock b clock b is one of two clock sources which can be used for channels 2, 3, 6, or 7. these three bits determine the rate of clock b, as shown in table 13-5 . 2? pcka[2:0] prescaler select for clock a clock a is one of two clock sources which can be used for channels 0, 1, 4 or 5. these three bits determine the rate of clock a, as shown in table 13-6 . table 13-5. clock b prescaler selects pckb2 pckb1 pckb0 value of clock b 0 0 0 bus clock 0 0 1 bus clock / 2 0 1 0 bus clock / 4 0 1 1 bus clock / 8 1 0 0 bus clock / 16 1 0 1 bus clock / 32 1 1 0 bus clock / 64 1 1 1 bus clock / 128 table 13-6. clock a prescaler selects pcka2 pcka1 pcka0 value of clock a 0 0 0 bus clock 0 0 1 bus clock / 2 0 1 0 bus clock / 4 0 1 1 bus clock / 8 1 0 0 bus clock / 16 1 0 1 bus clock / 32 1 1 0 bus clock / 64 1 1 1 bus clock / 128
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 433 13.3.2.5 pwm center align enable register (pwmcae) the pwmcae register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each pwm channel. if the caex bit is set to a one, the corresponding pwm output will be center aligned. if the caex bit is cleared, the corresponding pwm output will be left aligned. see section 13.4.2.5, ?eft aligned outputs and section 13.4.2.6, ?enter aligned outputs for a more detailed description of the pwm output modes. read: anytime write: anytime note write these bits only when the corresponding channel is disabled. 13.3.2.6 pwm control register (pwmctl) the pwmctl register provides for various control of the pwm module. read: anytime write: anytime there are three control bits for concatenation, each of which is used to concatenate a pair of pwm channels into one 16-bit channel. when channels 6 and 7are concatenated, channel 6 registers become the high order bytes of the double byte channel. when channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. when channels 2 and 3 are concatenated, channel module base + 0x0004 76543210 r cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 w reset 0 0 0 00000 figure 13-7. pwm center align enable register (pwmcae) table 13-7. pwmcae field descriptions field description 7? cae[7:0] center aligned output modes on channels 7? 0 channels 7? operate in left aligned output mode. 1 channels 7? operate in center aligned output mode. module base + 0x0005 76543210 r con67 con45 con23 con01 pswai pfrz 00 w reset 0 0 0 00000 = unimplemented or reserved figure 13-8. pwm control register (pwmctl)
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 434 freescale semiconductor 2 registers become the high order bytes of the double byte channel. when channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. see section 13.4.2.7, ?wm 16-bit functions for a more detailed description of the concatenation pwm function. note change these bits only when both corresponding channels are disabled. table 13-8. pwmctl field descriptions field description 7 con67 concatenate channels 6 and 7 0 channels 6 and 7 are separate 8-bit pwms. 1 channels 6 and 7 are concatenated to create one 16-bit pwm channel. channel 6 becomes the high order byte and channel 7 becomes the low order byte. channel 7 output pin is used as the output for this 16-bit pwm (bit 7 of port pwmp). channel 7 clock select control-bit determines the clock source, channel 7 polarity bit determines the polarity, channel 7 enable bit enables the output and channel 7 center aligned enable bit determines the output mode. 6 con45 concatenate channels 4 and 5 0 channels 4 and 5 are separate 8-bit pwms. 1 channels 4 and 5 are concatenated to create one 16-bit pwm channel. channel 4 becomes the high order byte and channel 5 becomes the low order byte. channel 5 output pin is used as the output for this 16-bit pwm (bit 5 of port pwmp). channel 5 clock select control-bit determines the clock source, channel 5 polarity bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit determines the output mode. 5 con23 concatenate channels 2 and 3 0 channels 2 and 3 are separate 8-bit pwms. 1 channels 2 and 3 are concatenated to create one 16-bit pwm channel. channel 2 becomes the high order byte and channel 3 becomes the low order byte. channel 3 output pin is used as the output for this 16-bit pwm (bit 3 of port pwmp). channel 3 clock select control-bit determines the clock source, channel 3 polarity bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit determines the output mode. 4 con01 concatenate channels 0 and 1 0 channels 0 and 1 are separate 8-bit pwms. 1 channels 0 and 1 are concatenated to create one 16-bit pwm channel. channel 0 becomes the high order byte and channel 1 becomes the low order byte. channel 1 output pin is used as the output for this 16-bit pwm (bit 1 of port pwmp). channel 1 clock select control-bit determines the clock source, channel 1 polarity bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit determines the output mode. 3 pswai pwm stops in wait mode enabling this bit allows for lower power consumption in wait mode by disabling the input clock to the prescaler. 0 allow the clock to the prescaler to continue while in wait mode. 1 stop the input clock to the prescaler whenever the mcu is in wait mode. 2 pfrez pwm counters stop in freeze mode ?in freeze mode, there is an option to disable the input clock to the prescaler by setting the pfrz bit in the pwmctl register. if this bit is set, whenever the mcu is in freeze mode, the input clock to the prescaler is disabled. this feature is useful during emulation as it allows the pwm function to be suspended. in this way, the counters of the pwm can be stopped while in freeze mode so that once normal program ow is continued, the counters are re-enabled to simulate real-time operations. since the registers can still be accessed in this mode, to re-enable the prescaler clock, either disable the pfrz bit or exit freeze mode. 0 allow pwm to continue while in freeze mode. 1 disable pwm input clock to the prescaler whenever the part is in freeze mode. this is useful for emulation.
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 435 13.3.2.7 reserved register (pwmtst) this register is reserved for factory testing of the pwm module and is not available in normal modes. read: always read $00 in normal modes write: unimplemented in normal modes note writing to this register when in special modes can alter the pwm functionality. 13.3.2.8 reserved register (pwmprsc) this register is reserved for factory testing of the pwm module and is not available in normal modes. read: always read $00 in normal modes write: unimplemented in normal modes note writing to this register when in special modes can alter the pwm functionality. 13.3.2.9 pwm scale a register (pwmscla) pwmscla is the programmable scale value used in scaling clock a to generate clock sa. clock sa is generated by taking clock a, dividing it by the value in the pwmscla register and dividing that by two. clock sa = clock a / (2 * pwmscla) module base + 0x0006 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 13-9. reserved register (pwmtst) module base + 0x0007 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 13-10. reserved register (pwmprsc)
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 436 freescale semiconductor note when pwmscla = $00, pwmscla value is considered a full scale value of 256. clock a is thus divided by 512. any value written to this register will cause the scale counter to load the new scale value (pwmscla). read: anytime write: anytime (causes the scale counter to load the pwmscla value) 13.3.2.10 pwm scale b register (pwmsclb) pwmsclb is the programmable scale value used in scaling clock b to generate clock sb. clock sb is generated by taking clock b, dividing it by the value in the pwmsclb register and dividing that by two. clock sb = clock b / (2 * pwmsclb) note when pwmsclb = $00, pwmsclb value is considered a full scale value of 256. clock b is thus divided by 512. any value written to this register will cause the scale counter to load the new scale value (pwmsclb). read: anytime write: anytime (causes the scale counter to load the pwmsclb value). 13.3.2.11 reserved registers (pwmscntx) the registers pwmscnta and pwmscntb are reserved for factory testing of the pwm module and are not available in normal modes. module base + 0x0008 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset 0 0 0 00000 figure 13-11. pwm scale a register (pwmscla) module base + 0x0009 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset 0 0 0 00000 figure 13-12. pwm scale b register (pwmsclb)
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 437 read: always read $00 in normal modes write: unimplemented in normal modes note writing to these registers when in special modes can alter the pwm functionality. 13.3.2.12 pwm channel counter registers (pwmcntx) each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. the counter can be read at any time without affecting the count or the operation of the pwm channel. in left aligned output mode, the counter counts from 0 to the value in the period register - 1. in center aligned output mode, the counter counts from 0 up to the value in the period register and then back down to 0. any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. the counter is also cleared at the end of the effective period (see section 13.4.2.5, ?eft aligned outputs and section 13.4.2.6, ?enter aligned outputs for more details). when the channel is disabled (pwmex = 0), the pwmcntx register does not count. when a channel becomes enabled (pwmex = 1), the associated pwm counter starts at the count in the pwmcntx register. for more detailed information on the operation of the counters, see section 13.4.2.4, ?wm timer counters . in concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. note writing to the counter while the channel is enabled can cause an irregular pwm cycle to occur. read: anytime module base + 0x000a, 0x000b 76543210 r00000000 w reset 0 0 0 00000 = unimplemented or reserved figure 13-13. reserved registers (pwmscntx) module base + 0x000c = pwmcnt0, 0x000d = pwmcnt1, 0x000e = pwmcnt2, 0x000f = pwmcnt3 module base + 0x0010 = pwmcnt4, 0x0011 = pwmcnt5, 0x0012 = pwmcnt6, 0x0013 = pwmcnt7 76543210 r bit 7 6 5 4 3 2 1 bit 0 w00000000 reset 0 0 0 00000 figure 13-14. pwm channel counter registers (pwmcntx)
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 438 freescale semiconductor write: anytime (any value written causes pwm counter to be reset to $00). 13.3.2.13 pwm channel period registers (pwmperx) there is a dedicated period register for each channel. the value in this register determines the period of the associated pwm channel. the period registers for each channel are double buffered so that if they change while the channel is enabled, the change will not take effect until one of the following occurs: the effective period ends the counter is written (counter resets to $00) the channel is disabled in this way, the output of the pwm will always be either the old waveform or the new waveform, not some variation in between. if the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. note reads of this register return the most recent value written. reads do not necessarily return the value of the currently active period due to the double buffering scheme. see section 13.4.2.3, ?wm period and duty for more information. to calculate the output period, take the selected clock source period for the channel of interest (a, b, sa, or sb) and multiply it by the value in the period register for that channel: left aligned output (caex = 0) pwmx period = channel clock period * pwmperx center aligned output (caex = 1) pwmx period = channel clock period * (2 * pwmperx) for boundary case programming values, please refer to section 13.4.2.8, ?wm boundary cases . read: anytime write: anytime module base + 0x0014 = pwmper0, 0x0015 = pwmper1, 0x0016 = pwmper2, 0x0017 = pwmper3 module base + 0x0018 = pwmper4, 0x0019 = pwmper5, 0x001a = pwmper6, 0x001b = pwmper7 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset 1 1 1 11111 figure 13-15. pwm channel period registers (pwmperx)
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 439 13.3.2.14 pwm channel duty registers (pwmdtyx) there is a dedicated duty register for each channel. the value in this register determines the duty of the associated pwm channel. the duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state. the duty registers for each channel are double buffered so that if they change while the channel is enabled, the change will not take effect until one of the following occurs: the effective period ends the counter is written (counter resets to $00) the channel is disabled in this way, the output of the pwm will always be either the old duty waveform or the new duty waveform, not some variation in between. if the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. note reads of this register return the most recent value written. reads do not necessarily return the value of the currently active duty due to the double buffering scheme. see section 13.4.2.3, ?wm period and duty for more information. note depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. if the polarity bit is one, the output starts high and then goes low when the duty count is reached, so the duty registers contain a count of the high time. if the polarity bit is zero, the output starts low and then goes high when the duty count is reached, so the duty registers contain a count of the low time. to calculate the output duty cycle (high time as a% of period) for a particular channel: polarity = 0 (ppol x =0) duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100% for boundary case programming values, please refer to section 13.4.2.8, ?wm boundary cases . read: anytime module base + 0x001c = pwmdty0, 0x001d = pwmdty1, 0x001e = pwmdty2, 0x001f = pwmdty3 module base + 0x0020 = pwmdty4, 0x0021 = pwmdty5, 0x0022 = pwmdty6, 0x0023 = pwmdty7 76543210 r bit 7 6 5 4 3 2 1 bit 0 w reset 1 1 1 11111 figure 13-16. pwm channel duty registers (pwmdtyx)
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 440 freescale semiconductor write: anytime 13.3.2.15 pwm shutdown register (pwmsdn) the pwmsdn register provides for the shutdown functionality of the pwm module in the emergency cases. for proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks. read: anytime write: anytime module base + 0x0024 76543210 r pwmif pwmie 0 pwmlvl 0 pwm7in pwm7inl pwm7ena w pwmrstrt reset 0 0 0 00000 = unimplemented or reserved figure 13-17. pwm shutdown register (pwmsdn) table 13-9. pwmsdn field descriptions field description 7 pwmif pwm interrupt flag ?any change from passive to asserted (active) state or from active to passive state will be ?gged by setting the pwmif ?g = 1. the ?g is cleared by writing a logic 1 to it. writing a 0 has no effect. 0 no change on pwm7in input. 1 change on pwm7in input 6 pwmie pwm interrupt enable ?if interrupt is enabled an interrupt to the cpu is asserted. 0 pwm interrupt is disabled. 1 pwm interrupt is enabled. 5 pwmrstrt pwm restart the pwm can only be restarted if the pwm channel input 7 is de-asserted. after writing a logic 1 to the pwmrstrt bit (trigger event) the pwm channels start running after the corresponding counter passes next ?ounter == 0?phase. also, if the pwm7ena bit is reset to 0, the pwm do not start before the counter passes $00. the bit is always read as ?? 4 pwmlvl pwm shutdown output level if active level as de?ed by the pwm7in input, gets asserted all enabled pwm channels are immediately driven to the level de?ed by pwmlvl. 0 pwm outputs are forced to 0 1 outputs are forced to 1. 2 pwm7in pwm channel 7 input status ?this re?cts the current status of the pwm7 pin. 1 pwm7inl pwm shutdown active input level for channel 7 ?if the emergency shutdown feature is enabled (pwm7ena = 1), this bit determines the active level of the pwm7channel. 0 active level is low 1 active level is high 0 pwm7ena pwm emergency shutdown enable if this bit is logic 1, the pin associated with channel 7 is forced to input and the emergency shutdown feature is enabled. all the other bits in this register are meaningful only if pwm7ena = 1. 0 pwm emergency feature disabled. 1 pwm emergency feature is enabled.
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 441 13.4 functional description 13.4.1 pwm clock select there are four available clocks: clock a, clock b, clock sa (scaled a), and clock sb (scaled b). these four clocks are based on the bus clock. clock a and b can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. clock sa uses clock a as an input and divides it further with a reloadable counter. similarly, clock sb uses clock b as an input and divides it further with a reloadable counter. the rates available for clock sa are software selectable to be clock a divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. similar rates are available for clock sb. each pwm channel has the capability of selecting one of two clocks, either the pre-scaled clock (clock a or b) or the scaled clock (clock sa or sb). the block diagram in figure 13-18 shows the four different clocks and how the scaled clocks are created. 13.4.1.1 prescale the input clock to the pwm prescaler is the bus clock. it can be disabled whenever the part is in freeze mode by setting the pfrz bit in the pwmctl register. if this bit is set, whenever the mcu is in freeze mode (freeze mode signal active) the input clock to the prescaler is disabled. this is useful for emulation in order to freeze the pwm. the input clock can also be disabled when all eight pwm channels are disabled (pwme7-0 = 0). this is useful for reducing power by disabling the prescale counter. clock a and clock b are scaled values of the input clock. the value is software selectable for both clock a and clock b and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. the value selected for clock a is determined by the pcka2, pcka1, pcka0 bits in the pwmprclk register. the value selected for clock b is determined by the pckb2, pckb1, pckb0 bits also in the pwmprclk register. 13.4.1.2 clock scale the scaled a clock uses clock a as an input and divides it further with a user programmable value and then divides this by 2. the scaled b clock uses clock b as an input and divides it further with a user programmable value and then divides this by 2. the rates available for clock sa are software selectable to be clock a divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. similar rates are available for clock sb.
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 442 freescale semiconductor figure 13-18. pwm clock select block diagram 128 2 4 8 16 32 64 pckb2 pckb1 pckb0 m u x clock a clock b clock sa clock a/2, a/4, a/6,....a/512 prescale scale divide by pfrz freeze mode signal bus clock clock select m u x pclk0 clock to pwm ch 0 m u x pclk2 clock to pwm ch 2 m u x pclk1 clock to pwm ch 1 m u x pclk4 clock to pwm ch 4 m u x pclk5 clock to pwm ch 5 m u x pclk6 clock to pwm ch 6 m u x pclk7 clock to pwm ch 7 m u x pclk3 clock to pwm ch 3 load div 2 pwmsclb clock sb clock b/2, b/4, b/6,....b/512 m u x pcka2 pcka1 pcka0 pwme7-0 count = 1 load div 2 pwmscla count = 1 8-bit down counter 8-bit down counter prescaler taps:
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 443 clock a is used as an input to an 8-bit down counter. this down counter loads a user programmable scale value from the scale register (pwmscla). when the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. the output signal from this circuit is further divided by two. this gives a greater range with only a slight reduction in granularity. clock sa equals clock a divided by two times the value in the pwmscla register. note clock sa = clock a / (2 * pwmscla) when pwmscla = $00, pwmscla value is considered a full scale value of 256. clock a is thus divided by 512. similarly, clock b is used as an input to an 8-bit down counter followed by a divide by two producing clock sb. thus, clock sb equals clock b divided by two times the value in the pwmsclb register. note clock sb = clock b / (2 * pwmsclb) when pwmsclb = $00, pwmsclb value is considered a full scale value of 256. clock b is thus divided by 512. as an example, consider the case in which the user writes $ff into the pwmscla register. clock a for this case will be e divided by 4. a pulse will occur at a rate of once every 255x4 e cycles. passing this through the divide by two circuit produces a clock signal at an e divided by 2040 rate. similarly, a value of $01 in the pwmscla register when clock a is e divided by 4 will produce a clock at an e divided by 8 rate. writing to pwmscla or pwmsclb causes the associated 8-bit down counter to be re-loaded. otherwise, when changing rates the counter would have to count down to $01 before counting at the proper rate. forcing the associated counter to re-load the scale register value every time pwmscla or pwmsclb is written prevents this. note writing to the scale registers while channels are operating can cause irregularities in the pwm outputs. 13.4.1.3 clock select each pwm channel has the capability of selecting one of two clocks. for channels 0, 1, 4, and 5 the clock choices are clock a or clock sa. for channels 2, 3, 6, and 7 the choices are clock b or clock sb. the clock selection is done with the pclkx control bits in the pwmclk register. note changing clock control bits while channels are operating can cause irregularities in the pwm outputs.
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 444 freescale semiconductor 13.4.2 pwm channel timers the main part of the pwm module are the actual timers. each of the timer channels has a counter, a period register and a duty register (each are 8-bit). the waveform output period is controlled by a match between the period register and the value in the counter. the duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period. the starting polarity of the output is also selectable on a per channel basis. shown below in figure 13-19 is the block diagram for the pwm timer. figure 13-19. pwm timer channel block diagram 13.4.2.1 pwm enable each pwm channel has an enable bit (pwmex) to start its waveform output. when any of the pwmex bits are set (pwmex = 1), the associated pwm output signal is enabled immediately. however, the actual pwm waveform is not available on the associated pwm output until its clock source begins its next cycle due to the synchronization of pwmex and the clock source. an exception to this is when channels are concatenated. refer to section 13.4.2.7, ?wm 16-bit functions for more detail. note the ?st pwm cycle after enabling the channel can be irregular. clock source t r q q ppolx from port pwmp data register pwmex to pin driver gate 8-bit compare = pwmdtyx 8-bit compare = pwmperx caex t r q q 8-bit counter pwmcntx m u x m u x (clock edge sync) up/down reset
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 445 on the front end of the pwm timer, the clock is enabled to the pwm circuit by the pwmex bit being high. there is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. when the channel is disabled (pwmex = 0), the counter for the channel does not count. 13.4.2.2 pwm polarity each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. this is shown on the block diagram as a mux select of either the q output or the q output of the pwm output ?p ?p. when one of the bits in the pwmpol register is set, the associated pwm channel output is high at the beginning of the waveform, then goes low when the duty count is reached. conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. 13.4.2.3 pwm period and duty dedicated period and duty registers exist for each channel and are double buffered so that if they change while the channel is enabled, the change will not take effect until one of the following occurs: the effective period ends the counter is written (counter resets to $00) the channel is disabled in this way, the output of the pwm will always be either the old waveform or the new waveform, not some variation in between. if the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer. a change in duty or period can be forced into effect ?mmediately?by writing the new value to the duty and/or period registers and then writing to the counter. this forces the counter to reset and the new duty and/or period values to be latched. in addition, since the counter is readable, it is possible to know where the count is with respect to the duty value and software can be used to make adjustments note when forcing a new period or duty into effect immediately, an irregular pwm cycle can occur. depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. 13.4.2.4 pwm timer counters each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see section 13.4.1, ?wm clock select for the available clock sources and rates). the counter compares to two registers, a duty register and a period register as shown in figure 13-19 . when the pwm counter matches the duty register, the output ?p-?p changes state, causing the pwm waveform to also change state. a match between the pwm counter and the period register behaves differently depending on what output mode is selected as shown in figure 13-19 and described in section 13.4.2.5, ?eft aligned outputs and section 13.4.2.6, ?enter aligned outputs .
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 446 freescale semiconductor each channel counter can be read at anytime without affecting the count or the operation of the pwm channel. any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. when the channel is disabled (pwmex = 0), the counter stops. when a channel becomes enabled (pwmex = 1), the associated pwm counter continues from the count in the pwmcntx register. this allows the waveform to continue where it left off when the channel is re-enabled. when the channel is disabled, writing ? to the period register will cause the counter to reset on the next selected clock. note if the user wants to start a new ?lean?pwm waveform without any ?istory?from the old waveform, the user must write to channel counter (pwmcntx) prior to enabling the pwm channel (pwmex = 1). generally, writes to the counter are done prior to enabling a channel in order to start from a known state. however, writing a counter can also be done while the pwm channel is enabled (counting). the effect is similar to writing the counter when the channel is disabled, except that the new period is started immediately with the output set according to the polarity bit. note writing to the counter while the channel is enabled can cause an irregular pwm cycle to occur. the counter is cleared at the end of the effective period (see section 13.4.2.5, ?eft aligned outputs and section 13.4.2.6, ?enter aligned outputs for more details). 13.4.2.5 left aligned outputs the pwm timer provides the choice of two types of outputs, left aligned or center aligned. they are selected with the caex bits in the pwmcae register. if the caex bit is cleared (caex = 0), the corresponding pwm output will be left aligned. in left aligned output mode, the 8-bit counter is con?ured as an up counter only. it compares to two registers, a duty register and a period register as shown in the block diagram in figure 13-19 . when the pwm counter matches the duty register the output ?p-?p changes state causing the pwm waveform to also change state. a match between the pwm counter and the period register resets the counter and the output ?p-?p, as shown in figure 13-19 , as well as performing a load from the double buffer period and duty register to the associated registers, as described in section 13.4.2.3, ?wm period and duty . the counter counts from 0 to the value in the period register ?1. table 13-10. pwm timer counter conditions counter clears ($00) counter counts counter stops when pwmcntx register written to any value when pwm channel is enabled (pwmex = 1). counts from last value in pwmcntx. when pwm channel is disabled (pwmex = 0) effective period ends
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 447 note changing the pwm output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the pwm output. it is recommended to program the output mode before enabling the pwm channel. figure 13-20. pwm left aligned output waveform to calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency for the channel (a, b, sa, or sb) and divide it by the value in the period register for that channel. pwmx frequency = clock (a, b, sa, or sb) / pwmperx pwmx duty cycle (high time as a% of period): polarity = 0 (ppolx = 0) duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100% as an example of a left aligned output, consider the following case: clock source = e, where e = 10 mhz (100 ns period) ppolx = 0 pwmperx = 4 pwmdtyx = 1 pwmx frequency = 10 mhz/4 = 2.5 mhz pwmx period = 400 ns pwmx duty cycle = 3/4 *100% = 75% the output waveform generated is shown in figure 13-21 . pwmdtyx period = pwmperx ppolx = 0 ppolx = 1
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 448 freescale semiconductor figure 13-21. pwm left aligned output example waveform 13.4.2.6 center aligned outputs for center aligned output mode selection, set the caex bit (caex = 1) in the pwmcae register and the corresponding pwm output will be center aligned. the 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00. the counter compares to two registers, a duty register and a period register as shown in the block diagram in figure 13-19 . when the pwm counter matches the duty register, the output ?p-?p changes state, causing the pwm waveform to also change state. a match between the pwm counter and the period register changes the counter direction from an up-count to a down-count. when the pwm counter decrements and matches the duty register again, the output ?p-?p changes state causing the pwm output to also change state. when the pwm counter decrements and reaches zero, the counter direction changes from a down-count back to an up-count and a load from the double buffer period and duty registers to the associated registers is performed, as described in section 13.4.2.3, ?wm period and duty . the counter counts from 0 up to the value in the period register and then back down to 0. thus the effective period is pwmperx*2. note changing the pwm output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the pwm output. it is recommended to program the output mode before enabling the pwm channel. figure 13-22. pwm center aligned output waveform period = 400 ns e = 100 ns duty cycle = 75% ppolx = 0 ppolx = 1 pwmdtyx pwmdtyx period = pwmperx*2 pwmperx pwmperx
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 449 to calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (a, b, sa, or sb) and divide it by twice the value in the period register for that channel. pwmx frequency = clock (a, b, sa, or sb) / (2*pwmperx) pwmx duty cycle (high time as a% of period): polarity = 0 (ppolx = 0) duty cycle = [(pwmperx-pwmdtyx)/pwmperx] * 100% polarity = 1 (ppolx = 1) duty cycle = [pwmdtyx / pwmperx] * 100%
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 450 freescale semiconductor as an example of a center aligned output, consider the following case: clock source = e, where e = 10 mhz (100 ns period) ppolx = 0 pwmperx = 4 pwmdtyx = 1 pwmx frequency = 10 mhz/8 = 1.25 mhz pwmx period = 800 ns pwmx duty cycle = 3/4 *100% = 75% shown in figure 13-23 is the output waveform generated. figure 13-23. pwm center aligned output example waveform 13.4.2.7 pwm 16-bit functions the pwm timer also has the option of generating 8-channels of 8-bits or 4-channels of 16-bits for greater pwm resolution. this 16-bit channel option is achieved through the concatenation of two 8-bit channels. the pwmctl register contains four control bits, each of which is used to concatenate a pair of pwm channels into one 16-bit channel. channels 6 and 7 are concatenated with the con67 bit, channels 4 and 5 are concatenated with the con45 bit, channels 2 and 3 are concatenated with the con23 bit, and channels 0 and 1 are concatenated with the con01 bit. note change these bits only when both corresponding channels are disabled. when channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double byte channel, as shown in figure 13-24 . similarly, when channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. when channels 2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel. when channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. when using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel clock select control bits. that is channel 7 when channels 6 and 7 are concatenated, channel 5 when channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when channels 0 and 1 are concatenated. the resulting pwm is output to the pins of the corresponding low order 8-bit channel as also shown in figure 13-24 . the polarity of the resulting pwm output is controlled by the ppolx bit of the corresponding low order 8-bit channel as well. e = 100 ns duty cycle = 75% e = 100 ns period = 800 ns
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 451 figure 13-24. pwm 16-bit mode once concatenated mode is enabled (conxx bits set in pwmctl register), enabling/disabling the corresponding 16-bit pwm channel is controlled by the low order pwmex bit. in this case, the high order bytes pwmex bits have no effect and their corresponding pwm output is disabled. in concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. pwmcnt6 pwcnt7 pwm7 clock source 7 high low period/duty compare pwmcnt4 pwcnt5 pwm5 clock source 5 high low period/duty compare pwmcnt2 pwcnt3 pwm3 clock source 3 high low period/duty compare pwmcnt0 pwcnt1 pwm1 clock source 1 high low period/duty compare
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 452 freescale semiconductor either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order caex bit. the high order caex bit has no effect. table 13-11 is used to summarize which channels are used to set the various control bits when in 16-bit mode. 13.4.2.8 pwm boundary cases table 13-12 summarizes the boundary conditions for the pwm regardless of the output mode (left aligned or center aligned) and 8-bit (normal) or 16-bit (concatenation). 13.5 resets the reset state of each individual bit is listed within the section 13.3.2, ?egister descriptions which details the registers and their bit-?lds. all special functions or modes which are initialized during or just following reset are described within this section. the 8-bit up/down counter is con?ured as an up counter out of reset. all the channels are disabled and all the counters do not count. table 13-11. 16-bit concatenation mode summary conxx pwmex ppolx pclkx caex pwmx output con67 pwme7 ppol7 pclk7 cae7 pwm7 con45 pwme5 ppol5 pclk5 cae5 pwm5 con23 pwme3 ppol3 pclk3 cae3 pwm3 con01 pwme1 ppol1 pclk1 cae1 pwm1 table 13-12. pwm boundary cases pwmdtyx pwmperx ppolx pwmx output $00 (indicates no duty) >$00 1 always low $00 (indicates no duty) >$00 0 always high xx $00 1 (indicates no period) 1 counter = $00 and does not count. 1 always high xx $00 1 (indicates no period) 0 always low >= pwmperx xx 1 always high >= pwmperx xx 0 always low
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 453 13.6 interrupts the pwm module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (pwmie) is set. this bit is the enable for the interrupt. the interrupt ?g pwmif is set whenever the input level of the pwm7 channel changes while pwm7ena = 1 or when pwmena is being asserted while the level at pwm7 is active. in stop mode or wait mode (with the pswai bit set), the emergency shutdown feature will drive the pwm outputs to their shutdown output levels but the pwmif ?g will not be set. a description of the registers involved and affected due to this interrupt is explained in section 13.3.2.15, ?wm shutdown register (pwmsdn) . the pwm block only generates the interrupt and does not service it. the interrupt signal name is pwm interrupt signal.
pulse-width modulator (s12pwm8b8cv1) mc9s12xhy-family reference manual, rev. 1.01 454 freescale semiconductor
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 455 chapter 14 serial communication interface (s12sciv5) 14.1 introduction this block guide provides an overview of the serial communication interface (sci) module. the sci allows asynchronous serial communications with peripheral devices and other cpus. 14.1.1 glossary ir: infrared irda: infrared design associate irq: interrupt request lin: local interconnect network lsb: least signi?ant bit msb: most signi?ant bit nrz: non-return-to-zero rzi: return-to-zero-inverted rxd: receive pin sci : serial communication interface txd: transmit pin table 14-1. revision history version number revision date effective date author description of changes 05.03 12/25/2008 remove redundancy comments in figure1-2 05.04 08/05/2009 fix typo, scibdl reset value be 0x04, not 0x00 05.05 06/03/2010 fix typo, table 14-4 ,scicr1 even parity should be pt=0 fix typo, on page 14-477 ,should be bkdif,not bldif
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 456 freescale semiconductor 14.1.2 features the sci includes these distinctive features: full-duplex or single-wire operation standard mark/space non-return-to-zero (nrz) format selectable irda 1.4 return-to-zero-inverted (rzi) format with programmable pulse widths 13-bit baud rate selection programmable 8-bit or 9-bit data format separately enabled transmitter and receiver programmable polarity for transmitter and receiver programmable transmitter output parity two receiver wakeup methods: idle line wakeup address mark wakeup interrupt-driven operation with eight flags: transmitter empty transmission complete receiver full idle receiver input receiver overrun noise error framing error parity error receive wakeup on active edge transmit collision detect supporting lin break detect supporting lin receiver framing error detection hardware parity checking 1/16 bit-time noise detection 14.1.3 modes of operation the sci functions the same in normal, special, and emulation modes. it has two low power modes, wait and stop modes. run mode wait mode stop mode
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 457 14.1.4 block diagram figure 14-1 is a high level block diagram of the sci module, showing the interaction of various function blocks. figure 14-1. sci block diagram sci data register rxd data in data out txd receive shift register infrared decoder receive & wakeup control data format control transmit control baud rate generator bus clock 1/16 transmit shift register sci data register receive interrupt generation transmit interrupt generation infrared encoder idle rdrf/or tc tdre brkd berr rxedg sci interrupt request
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 458 freescale semiconductor 14.2 external signal description the sci module has a total of two external pins. 14.2.1 txd ?transmit pin the txd pin transmits sci (standard or infrared) data. it will idle high in either mode and is high impedance anytime the transmitter is disabled. 14.2.2 rxd ?receive pin the rxd pin receives sci (standard or infrared) data. an idle line is detected as a line high. this input is ignored when the receiver is disabled and should be terminated to a known voltage. 14.3 memory map and register de?ition this section provides a detailed description of all the sci registers. 14.3.1 module memory map and register de?ition the memory map for the sci module is given below in figure 14-2 . the address listed for each register is the address offset. the total address for each register is the sum of the base address for the sci module and the address offset for each register.
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 459 14.3.2 register descriptions this section consists of register descriptions in address order. each description includes a standard register diagram with an associated ?ure number. writes to a reserved register locations do not have any effect and reads of these locations return a zero. details of register bit and ?ld function follow the register diagrams, in bit order. register name bit 7 6 5 4 3 2 1 bit 0 0x0000 scibdh 1 r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w 0x0001 scibdl 1 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w 0x0002 scicr1 1 r loops sciswai rsrc m wake ilt pe pt w 0x0000 sciasr1 2 r rxedgif 0000 berrv berrif bkdif w 0x0001 sciacr1 2 r rxedgie 00000 berrie bkdie w 0x0002 sciacr2 2 r00000 berrm1 berrm0 bkdfe w 0x0003 scicr2 r tie tcie rie ilie te re rwu sbk w 0x0004 scisr1 r tdre tc rdrf idle or nf fe pf w 0x0005 scisr2 r amap 00 txpol rxpol brk13 txdir raf w 0x0006 scidrh rr8 t8 000000 w 0x0007 scidrl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 1.these registers are accessible if the amap bit in the scisr2 register is set to zero. 2,these registers are accessible if the amap bit in the scisr2 register is set to one. = unimplemented or reserved figure 14-2. sci register summary
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 460 freescale semiconductor 14.3.2.1 sci baud rate registers (scibdh, scibdl) read: anytime, if amap = 0. if only scibdh is written to, a read will not return the correct data until scibdl is written to as well, following a write to scibdh. write: anytime, if amap = 0. note those two registers are only visible in the memory map if amap = 0 (reset condition). the sci baud rate register is used by to determine the baud rate of the sci, and to control the infrared modulation/demodulation submodule. module base + 0x0000 76543210 r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w reset 0 0 0 00000 figure 14-3. sci baud rate register (scibdh) module base + 0x0001 76543210 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w reset 0 0 0 00100 figure 14-4. sci baud rate register (scibdl) table 14-2. scibdh and scibdl field descriptions field description 7 iren infrared enable bit ?this bit enables/disables the infrared modulation/demodulation submodule. 0 ir disabled 1 ir enabled 6:5 tnp[1:0] transmitter narrow pulse bits these bits enable whether the sci transmits a 1/16, 3/16, 1/32 or 1/4 narrow pulse. see table 14-3 . 4:0 7:0 sbr[12:0] sci baud rate bits ?the baud rate for the sci is determined by the bits in this register. the baud rate is calculated two different ways depending on the state of the iren bit. the formulas for calculating the baud rate are: when iren = 0 then, sci baud rate = sci bus clock / (16 x sbr[12:0]) when iren = 1 then, sci baud rate = sci bus clock / (32 x sbr[12:1]) note: the baud rate generator is disabled after reset and not started until the te bit or the re bit is set for the ?st time. the baud rate generator is disabled when (sbr[12:0] = 0 and iren = 0) or (sbr[12:1] = 0 and iren = 1). note: writing to scibdh has no effect without writing to scibdl, because writing to scibdh puts the data in a temporary location until scibdl is written to.
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 461 14.3.2.2 sci control register 1 (scicr1) read: anytime, if amap = 0. write: anytime, if amap = 0. note this register is only visible in the memory map if amap = 0 (reset condition). table 14-3. irsci transmit pulse width tnp[1:0] narrow pulse width 11 1/4 10 1/32 01 1/16 00 3/16 module base + 0x0002 76543210 r loops sciswai rsrc m wake ilt pe pt w reset 0 0 0 00000 figure 14-5. sci control register 1 (scicr1) table 14-4. scicr1 field descriptions field description 7 loops loop select bit loops enables loop operation. in loop operation, the rxd pin is disconnected from the sci and the transmitter output is internally connected to the receiver input. both the transmitter and the receiver must be enabled to use the loop function. 0 normal operation enabled 1 loop operation enabled the receiver input is determined by the rsrc bit. 6 sciswai sci stop in wait mode bit ?sciswai disables the sci in wait mode. 0 sci enabled in wait mode 1 sci disabled in wait mode 5 rsrc receiver source bit ?when loops = 1, the rsrc bit determines the source for the receiver shift register input. see table 14-5 . 0 receiver input internally connected to transmitter output 1 receiver input connected externally to transmitter 4 m data format mode bit ?mode determines whether data characters are eight or nine bits long. 0 one start bit, eight data bits, one stop bit 1 one start bit, nine data bits, one stop bit 3 wake wakeup condition bit wake determines which condition wakes up the sci: a logic 1 (address mark) in the most signi?ant bit position of a received data character or an idle condition on the rxd pin. 0 idle line wakeup 1 address mark wakeup
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 462 freescale semiconductor 2 ilt idle line type bit ?ilt determines when the receiver starts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 idle character bit count begins after start bit 1 idle character bit count begins after stop bit 1 pe parity enable bit pe enables the parity function. when enabled, the parity function inserts a parity bit in the most signi?ant bit position. 0 parity function disabled 1 parity function enabled 0 pt parity type bit pt determines whether the sci generates and checks for even parity or odd parity. with even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. with odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 0 even parity 1 odd parity table 14-5. loop functions loops rsrc function 0 x normal operation 1 0 loop mode with transmitter output internally connected to receiver input 1 1 single-wire mode with txd pin connected to receiver input table 14-4. scicr1 field descriptions (continued) field description
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 463 14.3.2.3 sci alternative status register 1 (sciasr1) read: anytime, if amap = 1 write: anytime, if amap = 1 module base + 0x0000 76543210 r rxedgif 0 0 0 0 berrv berrif bkdif w reset 0 0 0 00000 = unimplemented or reserved figure 14-6. sci alternative status register 1 (sciasr1) table 14-6. sciasr1 field descriptions field description 7 rxedgif receive input active edge interrupt flag ?rxedgif is asserted, if an active edge (falling if rxpol = 0, rising if rxpol = 1) on the rxd input occurs. rxedgif bit is cleared by writing a ??to it. 0 no active receive on the receive input has occurred 1 an active edge on the receive input has occurred 2 berrv bit error value berrv re?cts the state of the rxd input when the bit error detect circuitry is enabled and a mismatch to the expected value happened. the value is only meaningful, if berrif = 1. 0 a low input was sampled, when a high was expected 1 a high input reassembled, when a low was expected 1 berrif bit error interrupt flag ?berrif is asserted, when the bit error detect circuitry is enabled and if the value sampled at the rxd input does not match the transmitted value. if the berrie interrupt enable bit is set an interrupt will be generated. the berrif bit is cleared by writing a ??to it. 0 no mismatch detected 1 a mismatch has occurred 0 bkdif break detect interrupt flag bkdif is asserted, if the break detect circuitry is enabled and a break signal is received. if the bkdie interrupt enable bit is set an interrupt will be generated. the bkdif bit is cleared by writing a ??to it. 0 no break signal was received 1 a break signal was received
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 464 freescale semiconductor 14.3.2.4 sci alternative control register 1 (sciacr1) read: anytime, if amap = 1 write: anytime, if amap = 1 module base + 0x0001 76543210 r rxedgie 00000 berrie bkdie w reset 0 0 0 00000 = unimplemented or reserved figure 14-7. sci alternative control register 1 (sciacr1) table 14-7. sciacr1 field descriptions field description 7 rsedgie receive input active edge interrupt enable rxedgie enables the receive input active edge interrupt ?g, rxedgif, to generate interrupt requests. 0 rxedgif interrupt requests disabled 1 rxedgif interrupt requests enabled 1 berrie bit error interrupt enable ?berrie enables the bit error interrupt ?g, berrif, to generate interrupt requests. 0 berrif interrupt requests disabled 1 berrif interrupt requests enabled 0 bkdie break detect interrupt enable ?bkdie enables the break detect interrupt ?g, bkdif, to generate interrupt requests. 0 bkdif interrupt requests disabled 1 bkdif interrupt requests enabled
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 465 14.3.2.5 sci alternative control register 2 (sciacr2) read: anytime, if amap = 1 write: anytime, if amap = 1 module base + 0x0002 76543210 r00000 berrm1 berrm0 bkdfe w reset 0 0 0 00000 = unimplemented or reserved figure 14-8. sci alternative control register 2 (sciacr2) table 14-8. sciacr2 field descriptions field description 2:1 berrm[1:0] bit error mode ?those two bits determines the functionality of the bit error detect feature. see table 14-9 . 0 bkdfe break detect feature enable ?bkdfe enables the break detect circuitry. 0 break detect circuit disabled 1 break detect circuit enabled table 14-9. bit error mode coding berrm1 berrm0 function 0 0 bit error detect circuit is disabled 0 1 receive input sampling occurs during the 9th time tick of a transmitted bit (refer to figure 14-19 ) 1 0 receive input sampling occurs during the 13th time tick of a transmitted bit (refer to figure 14-19 ) 1 1 reserved
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 466 freescale semiconductor 14.3.2.6 sci control register 2 (scicr2) read: anytime write: anytime module base + 0x0003 76543210 r tie tcie rie ilie te re rwu sbk w reset 0 0 0 00000 figure 14-9. sci control register 2 (scicr2) table 14-10. scicr2 field descriptions field description 7 tie transmitter interrupt enable bit ?tie enables the transmit data register empty ?g, tdre, to generate interrupt requests. 0 tdre interrupt requests disabled 1 tdre interrupt requests enabled 6 tcie transmission complete interrupt enable bit tcie enables the transmission complete ?g, tc, to generate interrupt requests. 0 tc interrupt requests disabled 1 tc interrupt requests enabled 5 rie receiver full interrupt enable bit rie enables the receive data register full ?g, rdrf, or the overrun ?g, or, to generate interrupt requests. 0 rdrf and or interrupt requests disabled 1 rdrf and or interrupt requests enabled 4 ilie idle line interrupt enable bit ?ilie enables the idle line ?g, idle, to generate interrupt requests. 0 idle interrupt requests disabled 1 idle interrupt requests enabled 3 te transmitter enable bit ?te enables the sci transmitter and con?ures the txd pin as being controlled by the sci. the te bit can be used to queue an idle preamble. 0 transmitter disabled 1 transmitter enabled 2 re receiver enable bit ?re enables the sci receiver. 0 receiver disabled 1 receiver enabled 1 rwu receiver wakeup bit ?standby state 0 normal operation. 1 rwu enables the wakeup function and inhibits further receiver interrupt requests. normally, hardware wakes the receiver by automatically clearing rwu. 0 sbk send break bit ?toggling sbk sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if brk13 is set). toggling implies clearing the sbk bit before the break character has ?ished transmitting. as long as sbk is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 no break characters 1 transmit break characters
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 467 14.3.2.7 sci status register 1 (scisr1) the scisr1 and scisr2 registers provides inputs to the mcu for generation of sci interrupts. also, these registers can be polled by the mcu to check the status of these bits. the ?g-clearing procedures require that the status register be read followed by a read or write to the sci data register.it is permissible to execute other instructions between the two steps as long as it does not compromise the handling of i/o, but the order of operations is important for ?g clearing. read: anytime write: has no meaning or effect module base + 0x0004 76543210 r tdre tc rdrf idle or nf fe pf w reset 1 1 0 00000 = unimplemented or reserved figure 14-10. sci status register 1 (scisr1) table 14-11. scisr1 field descriptions field description 7 tdre transmit data register empty flag ?tdre is set when the transmit shift register receives a byte from the sci data register. when tdre is 1, the transmit data register (scidrh/l) is empty and can receive a new value to transmit.clear tdre by reading sci status register 1 (scisr1), with tdre set and then writing to sci data register low (scidrl). 0 no byte transferred to transmit shift register 1 byte transferred to transmit shift register; transmit data register empty 6 tc transmit complete flag tc is set low when there is a transmission in progress or when a preamble or break character is loaded. tc is set high when the tdre ?g is set and no data, preamble, or break character is being transmitted.when tc is set, the txd pin becomes idle (logic 1). clear tc by reading sci status register 1 (scisr1) with tc set and then writing to sci data register low (scidrl). tc is cleared automatically when data, preamble, or break is queued and ready to be sent. tc is cleared in the event of a simultaneous set and clear of the tc ?g (transmission not complete). 0 transmission in progress 1 no transmission in progress 5 rdrf receive data register full flag rdrf is set when the data in the receive shift register transfers to the sci data register. clear rdrf by reading sci status register 1 (scisr1) with rdrf set and then reading sci data register low (scidrl). 0 data not available in sci data register 1 received data available in sci data register 4 idle idle line flag idle is set when 10 consecutive logic 1s (if m = 0) or 11 consecutive logic 1s (if m =1) appear on the receiver input. once the idle ?g is cleared, a valid frame must again set the rdrf ?g before an idle condition can set the idle ?g.clear idle by reading sci status register 1 (scisr1) with idle set and then reading sci data register low (scidrl). 0 receiver input is either active now or has never become active since the idle ?g was last cleared 1 receiver input has become idle note: when the receiver wakeup bit (rwu) is set, an idle line condition does not set the idle ?g.
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 468 freescale semiconductor 3 or overrun flag ?or is set when software fails to read the sci data register before the receive shift register receives the next frame. the or bit is set immediately after the stop bit has been completely received for the second frame. the data in the shift register is lost, but the data already in the sci data registers is not affected. clear or by reading sci status register 1 (scisr1) with or set and then reading sci data register low (scidrl). 0 no overrun 1 overrun note: or ?g may read back as set when rdrf ?g is clear. this may happen if the following sequence of events occurs: 1. after the ?st frame is received, read status register scisr1 (returns rdrf set and or ?g clear); 2. receive second frame without reading the ?st frame in the data register (the second frame is not received and or ?g is set); 3. read data register scidrl (returns ?st frame and clears rdrf ?g in the status register); 4. read status register scisr1 (returns rdrf clear and or set). event 3 may be at exactly the same time as event 2 or any time after. when this happens, a dummy scidrl read following event 4 will be required to clear the or ?g if further frames are to be received. 2 nf noise flag nf is set when the sci detects noise on the receiver input. nf bit is set during the same cycle as the rdrf ?g but does not get set in the case of an overrun. clear nf by reading sci status register 1(scisr1), and then reading sci data register low (scidrl). 0 no noise 1 noise 1 fe framing error flag fe is set when a logic 0 is accepted as the stop bit. fe bit is set during the same cycle as the rdrf ?g but does not get set in the case of an overrun. fe inhibits further data reception until it is cleared. clear fe by reading sci status register 1 (scisr1) with fe set and then reading the sci data register low (scidrl). 0 no framing error 1 framing error 0 pf parity error flag pf is set when the parity enable bit (pe) is set and the parity of the received data does not match the parity type bit (pt). pf bit is set during the same cycle as the rdrf ?g but does not get set in the case of an overrun. clear pf by reading sci status register 1 (scisr1), and then reading sci data register low (scidrl). 0 no parity error 1 parity error table 14-11. scisr1 field descriptions (continued) field description
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 469 14.3.2.8 sci status register 2 (scisr2) read: anytime write: anytime module base + 0x0005 76543210 r amap 00 txpol rxpol brk13 txdir raf w reset 0 0 0 00000 = unimplemented or reserved figure 14-11. sci status register 2 (scisr2) table 14-12. scisr2 field descriptions field description 7 amap alternative map this bit controls which registers sharing the same address space are accessible. in the reset condition the sci behaves as previous versions. setting amap=1 allows the access to another set of control and status registers and hides the baud rate and sci control register 1. 0 the registers labelled scibdh (0x0000),scibdl (0x0001), scicr1 (0x0002) are accessible 1 the registers labelled sciasr1 (0x0000),sciacr1 (0x0001), sciacr2 (0x00002) are accessible 4 txpol transmit polarity this bit control the polarity of the transmitted data. in nrz format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. in irda format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. 0 normal polarity 1 inverted polarity 3 rxpol receive polarity ?this bit control the polarity of the received data. in nrz format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. in irda format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. 0 normal polarity 1 inverted polarity 2 brk13 break transmit character length this bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. the detection of a framing error is not affected by this bit. 0 break character is 10 or 11 bit long 1 break character is 13 or 14 bit long 1 txdir transmitter pin data direction in single-wire mode ?this bit determines whether the txd pin is going to be used as an input or output, in the single-wire mode of operation. this bit is only relevant in the single-wire mode of operation. 0 txd pin to be used as an input in single-wire mode 1 txd pin to be used as an output in single-wire mode 0 raf receiver active flag raf is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. raf is cleared when the receiver detects an idle character. 0 no reception in progress 1 reception in progress
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 470 freescale semiconductor 14.3.2.9 sci data registers (scidrh, scidrl) read: anytime; reading accesses sci receive data register write: anytime; writing accesses sci transmit data register; writing to r8 has no effect note if the value of t8 is the same as in the previous transmission, t8 does not have to be rewritten.the same value is transmitted until t8 is rewritten in 8-bit data format, only sci data register low (scidrl) needs to be accessed. when transmitting in 9-bit data format and using 8-bit write instructions, write ?st to sci data register high (scidrh), then scidrl. module base + 0x0006 76543210 rr8 t8 000000 w reset 0 0 0 00000 = unimplemented or reserved figure 14-12. sci data registers (scidrh) module base + 0x0007 76543210 rr7r6r5r4r3r2r1r0 w t7 t6 t5 t4 t3 t2 t1 t0 reset 0 0 0 00000 figure 14-13. sci data registers (scidrl) table 14-13. scidrh and scidrl field descriptions field description scidrh 7 r8 received bit 8 ?r8 is the ninth data bit received when the sci is con?ured for 9-bit data format (m = 1). scidrh 6 t8 transmit bit 8 ?t8 is the ninth data bit transmitted when the sci is con?ured for 9-bit data format (m = 1). scidrl 7:0 r[7:0] t[7:0] r7:r0 ?received bits seven through zero for 9-bit or 8-bit data formats t7:t0 ?transmit bits seven through zero for 9-bit or 8-bit formats
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 471 14.4 functional description this section provides a complete functional description of the sci block, detailing the operation of the design from the end user perspective in a number of subsections. figure 14-14 shows the structure of the sci module. the sci allows full duplex, asynchronous, serial communication between the cpu and remote devices, including other cpus. the sci transmitter and receiver operate independently, although they use the same baud rate generator. the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. figure 14-14. detailed sci block diagram sci data receive shift register sci data register transmit shift register register baud rate generator sbr12:sbr0 bus transmit control 16 receive and wakeup data format control control t8 pf fe nf rdrf idle tie or tcie tdre tc r8 raf loops rwu re pe ilt pt wake m clock ilie rie rxd rsrc sbk loops te rsrc iren r16xclk ir_rxd txd ir_txd r16xclk r32xclk tnp[1:0] iren transmit encoder receive decoder scrxd sctxd infrared infrared tc tdre rdrf/or idle active edge detect break detect rxd bkdfe berrm[1:0] bkdie bkdif rxedgie rxedgif berrie berrif sci interrupt request lin transmit collision detect
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 472 freescale semiconductor 14.4.1 infrared interface submodule this module provides the capability of transmitting narrow pulses to an ir led and receiving narrow pulses and transforming them to serial bits, which are sent to the sci. the irda physical layer speci?ation de?es a half-duplex infrared communication link for exchange data. the full standard includes data rates up to 16 mbits/s. this design covers only data rates between 2.4 kbits/s and 115.2 kbits/s. the infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. the sci transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse for every zero bit. no pulse is transmitted for every one bit. when receiving data, the ir pulses should be detected using an ir photo diode and transformed to cmos levels by the ir receive decoder (external from the mcu). the narrow pulses are then stretched by the infrared submodule to get back to a serial bit stream to be received by the sci.the polarity of transmitted pulses and expected receive pulses can be inverted so that a direct connection can be made to external irda transceiver modules that uses active low pulses. the infrared submodule receives its clock sources from the sci. one of these two clocks are selected in the infrared submodule in order to generate either 3/16, 1/16, 1/32 or 1/4 narrow pulses during transmission. the infrared block receives two clock sources from the sci, r16xclk and r32xclk, which are con?ured to generate the narrow pulse width during transmission. the r16xclk and r32xclk are internal clocks with frequencies 16 and 32 times the baud rate respectively. both r16xclk and r32xclk clocks are used for transmitting data. the receive decoder uses only the r16xclk clock. 14.4.1.1 infrared transmit encoder the infrared transmit encoder converts serial bits of data from transmit shift register to the txd pin. a narrow pulse is transmitted for a zero bit and no pulse for a one bit. the narrow pulse is sent in the middle of the bit with a duration of 1/32, 1/16, 3/16 or 1/4 of a bit time. a narrow high pulse is transmitted for a zero bit when txpol is cleared, while a narrow low pulse is transmitted for a zero bit when txpol is set. 14.4.1.2 infrared receive decoder the infrared receive block converts data from the rxd pin to the receive shift register. a narrow pulse is expected for each zero received and no pulse is expected for each one received. a narrow high pulse is expected for a zero bit when rxpol is cleared, while a narrow low pulse is expected for a zero bit when rxpol is set. this receive decoder meets the edge jitter requirement as de?ed by the irda serial infrared physical layer speci?ation. 14.4.2 lin support this module provides some basic support for the lin protocol. at ?st this is a break detect circuitry making it easier for the lin software to distinguish a break character from an incoming data stream. as a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions.
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 473 14.4.3 data format the sci uses the standard nrz mark/space data format. when infrared is enabled, the sci uses rzi data format where zeroes are represented by light pulses and ones remain low. see figure 14-15 below. figure 14-15. sci data formats each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. clearing the m bit in sci control register 1 con?ures the sci for 8-bit data characters. a frame with eight data bits has a total of 10 bits. setting the m bit con?ures the sci for nine-bit data characters. a frame with nine data bits has a total of 11 bits. when the sci is con?ured for 9-bit data characters, the ninth data bit is the t8 bit in sci data register high (scidrh). it remains unchanged after transmission and can be used repeatedly without rewriting it. a frame with nine data bits has a total of 11 bits. table 14-14. example of 8-bit data formats start bit data bits address bits parity bits stop bit 18001 17011 17 1 1 1 the address bit identi?s the frame as an address character. see section 14.4.6.6, ?eceiver wakeup . 01 table 14-15. example of 9-bit data formats start bit data bits address bits parity bits stop bit 19001 18011 18 1 1 01 bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format (bit m in scicr1 clear) start bit bit 0 next stop bit start bit 9-bit data format (bit m in scicr1 set) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 possible parity bit possible parity bit standard sci data infrared sci data standard sci data infrared sci data
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 474 freescale semiconductor 14.4.4 baud rate generation a 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. the value from 0 to 8191 written to the sbr12:sbr0 bits determines the bus clock divisor. the sbr bits are in the sci baud rate registers (scibdh and scibdl). the baud rate clock is synchronized with the bus clock and drives the receiver. the baud rate clock divided by 16 drives the transmitter. the receiver has an acquisition rate of 16 samples per bit time. baud rate generation is subject to one source of error: integer division of the bus clock may not give the exact target frequency. table 14-16 lists some examples of achieving target baud rates with a bus clock frequency of 25 mhz. when iren = 0 then, sci baud rate = sci bus clock / (16 * scibr[12:0]) 1 the address bit identi?s the frame as an address character. see section 14.4.6.6, ?eceiver wakeup . table 14-16. baud rates (example: bus clock = 25 mhz) bits sbr[12:0] receiver clock (hz) transmitter clock (hz) target baud rate error (%) 41 609,756.1 38,109.8 38,400 .76 81 308,642.0 19,290.1 19,200 .47 163 153,374.2 9585.9 9,600 .16 326 76,687.1 4792.9 4,800 .15 651 38,402.5 2400.2 2,400 .01 1302 19,201.2 1200.1 1,200 .01 2604 9600.6 600.0 600 .00 5208 4800.0 300.0 300 .00
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 475 14.4.5 transmitter figure 14-16. transmitter block diagram 14.4.5.1 transmitter character length the sci transmitter can accommodate either 8-bit or 9-bit data characters. the state of the m bit in sci control register 1 (scicr1) determines the length of data characters. when transmitting 9-bit data, bit t8 in sci data register high (scidrh) is the ninth bit (bit 8). 14.4.5.2 character transmission to transmit data, the mcu writes the data bits to the sci data registers (scidrh/scidrl), which in turn are transferred to the transmitter shift register. the transmit shift register then shifts a frame out through the txd pin, after it has prefaced them with a start bit and appended them with a stop bit. the sci data registers (scidrh and scidrl) are the write-only buffers between the internal data bus and the transmit shift register. pe pt h876543210l 11-bit transmit register stop start t8 tie tdre tcie sbk tc parity generation msb sci data registers load from scidr shift enable preamble (all 1s) break (all 0s) transmitter control m internal bus sbr12:sbr0 baud divider 16 bus clock te sctxd txpol loops loop rsrc control to receiver transmit collision detect tdre irq tc irq sctxd scrxd (from receiver) tcie berrif ber irq berrm[1:0]
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 476 freescale semiconductor the sci also sets a ?g, the transmit data register empty ?g (tdre), every time it transfers data from the buffer (scidrh/l) to the transmitter shift register.the transmit driver routine may respond to this ?g by writing another byte to the transmitter buffer (scidrh/scidrl), while the shift register is still shifting out the ?st byte. to initiate an sci transmission: 1. con?ure the sci: a) select a baud rate. write this value to the sci baud registers (scibdh/l) to begin the baud rate generator. remember that the baud rate generator is disabled when the baud rate is zero. writing to the scibdh has no effect without also writing to scibdl. b) write to scicr1 to con?ure word length, parity, and other con?uration bits (loops,rsrc,m,wake,ilt,pe,pt). c) enable the transmitter, interrupts, receive, and wake up as required, by writing to the scicr2 register bits (tie,tcie,rie,ilie,te,re,rwu,sbk). a preamble or idle character will now be shifted out of the transmitter shift register. 2. transmit procedure for each byte: a) poll the tdre ?g by reading the scisr1 or responding to the tdre interrupt. keep in mind that the tdre bit resets to one. b) if the tdre ?g is set, write the data to be transmitted to scidrh/l, where the ninth bit is written to the t8 bit in scidrh if the sci is in 9-bit data format. a new transmission will not result until the tdre ?g has been cleared. 3. repeat step 2 for each subsequent transmission. note the tdre ?g is set when the shift register is loaded with the next data to be transmitted from scidrh/l, which happens, generally speaking, a little over half-way through the stop bit of the previous frame. speci?ally, this transfer occurs 9/16ths of a bit time after the start of the stop bit of the previous frame. writing the te bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if m = 0) or 11 logic 1s (if m = 1). after the preamble shifts out, control logic transfers the data from the sci data register into the transmit shift register. a logic 0 start bit automatically goes into the least signi?ant bit position of the transmit shift register. a logic 1 stop bit goes into the most signi?ant bit position. hardware supports odd or even parity. when parity is enabled, the most signi?ant bit (msb) of the data character is the parity bit. the transmit data register empty ?g, tdre, in sci status register 1 (scisr1) becomes set when the sci data register transfers a byte to the transmit shift register. the tdre ?g indicates that the sci data register can accept new data from the internal data bus. if the transmit interrupt enable bit, tie, in sci control register 2 (scicr2) is also set, the tdre ?g generates a transmitter interrupt request.
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 477 when the transmit shift register is not transmitting a frame, the txd pin goes to the idle condition, logic 1. if at any time software clears the te bit in sci control register 2 (scicr2), the transmitter enable signal goes low and the transmit signal goes idle. if software clears te while a transmission is in progress (tc = 0), the frame in the transmit shift register continues to shift out. to avoid accidentally cutting off the last frame in a message, always wait for tdre to go high after the last frame before clearing te. to separate messages with preambles with minimum idle line time, use this sequence between messages: 1. write the last byte of the ?st message to scidrh/l. 2. wait for the tdre ?g to go high, indicating the transfer of the last frame to the transmit shift register. 3. queue a preamble by clearing and then setting the te bit. 4. write the ?st byte of the second message to scidrh/l. 14.4.5.3 break characters writing a logic 1 to the send break bit, sbk, in sci control register 2 (scicr2) loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in sci control register 1 (scicr1). as long as sbk is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift register ?ishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. the sci recognizes a break character when there are 10 or 11(m = 0 or m = 1) consecutive zero received. depending if the break detect feature is enabled or not receiving a break character has these effects on sci registers. if the break detect feature is disabled (bkdfe = 0): sets the framing error flag, fe sets the receive data register full flag, rdrf clears the sci data registers (scidrh/l) may set the overrun flag, or, noise flag, nf, parity error flag, pe, or the receiver active flag, raf (see 3.4.4 and 3.4.5 sci status register 1 and 2) if the break detect feature is enabled (bkdfe = 1) there are two scenarios 1 the break is detected right from a start bit or is detected during a byte reception. sets the break detect interrupt flag, bkdif does not change the data register full flag, rdrf or overrun flag or does not change the framing error flag fe, parity error flag pe. does not clear the sci data registers (scidrh/l) may set noise flag nf, or receiver active flag raf. 1. a break character in this context are either 10 or 11 consecutive zero received bits
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 478 freescale semiconductor figure 14-17 shows two cases of break detect. in trace rxd_1 the break symbol starts with the start bit, while in rxd_2 the break starts in the middle of a transmission. if brkdfe = 1, in rxd_1 case there will be no byte transferred to the receive buffer and the rdrf ?g will not be modi?d. also no framing error or parity error will be ?gged from this transfer. in rxd_2 case, however the break signal starts later during the transmission. at the expected stop bit position the byte received so far will be transferred to the receive buffer, the receive data register full ?g will be set, a framing error and if enabled and appropriate a parity error will be set. once the break is detected the brkdif ?g will be set. figure 14-17. break detection if brkdfe = 1 (m = 0) 14.4.5.4 idle characters an idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. idle character length depends on the m bit in sci control register 1 (scicr1). the preamble is a synchronizing idle character that begins the ?st transmission initiated after writing the te bit from 0 to 1. if the te bit is cleared during a transmission, the txd pin becomes idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the frame currently being transmitted. note when queueing an idle character, return the te bit to logic 1 before the stop bit of the current frame shifts out through the txd pin. setting te after the stop bit appears on txd causes data previously written to the sci data register to be lost. toggle the te bit for a queued idle character while the tdre ?g is set and immediately before writing the next byte to the sci data register. if the te bit is clear and the transmission is complete, the sci is not the master of the txd pin start bit position stop bit position brkdif = 1 fe = 1 brkdif = 1 rxd_1 rxd_2 1 23 4567 8 910 1 23 4567 8 910 zero bit counter zero bit counter . . . . . .
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 479 14.4.5.5 lin transmit collision detection this module allows to check for collisions on the lin bus. figure 14-18. collision detect principle if the bit error circuit is enabled (berrm[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the transmitted and the received data stream at a point in time and ?g any mismatch. the timing checks run when transmitter is active (not idle). as soon as a mismatch between the transmitted data and the received data is detected the following happens: the next bit transmitted will have a high level (txpol = 0) or low level (txpol = 1) the transmission is aborted and the byte in transmit buffer is discarded. the transmit data register empty and the transmission complete flag will be set the bit error interrupt flag, berrif, will be set. no further transmissions will take place until the berrif is cleared. figure 14-19. timing diagram bit error detection if the bit error detect feature is disabled, the bit error interrupt ?g is cleared. note the rxpol and txpol bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt ?g may be set incorrectly. txd pin rxd pin lin physical interface synchronizer stage bus clock receive shift register transmit shift register lin bus compare sample bit error point output transmit shift register 01234567891011121314150 input receive shift register berrm[1:0] = 0:1 berrm[1:0] = 1:1 compare sample points sampling begin sampling begin sampling end sampling end
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 480 freescale semiconductor 14.4.6 receiver figure 14-20. sci receiver block diagram 14.4.6.1 receiver character length the sci receiver can accommodate either 8-bit or 9-bit data characters. the state of the m bit in sci control register 1 (scicr1) determines the length of data characters. when receiving 9-bit data, bit r8 in sci data register high (scidrh) is the ninth bit (bit 8). 14.4.6.2 character reception during an sci reception, the receive shift register shifts a frame in from the rxd pin. the sci data register is the read-only buffer between the internal data bus and the receive shift register. after a complete frame shifts into the receive shift register, the data portion of the frame transfers to the sci data register. the receive data register full ?g, rdrf, in sci status register 1 (scisr1) becomes set, all 1s m wake ilt pe pt re h876543210l 11-bit receive shift register stop start data wakeup parity checking msb sci data register r8 ilie rwu rdrf or nf fe pe internal bus bus sbr12:sbr0 baud divider clock idle raf recovery logic rxpol loops loop rsrc control scrxd from txd pin or transmitter idle irq rdrf/or irq break detect logic active edge detect logic brkdfe brkdie brkdif rxedgie rxedgif break irq rx active edge irq rie
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 481 indicating that the received byte can be read. if the receive interrupt enable bit, rie, in sci control register 2 (scicr2) is also set, the rdrf ?g generates an rdrf interrupt request. 14.4.6.3 data sampling the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock (see figure 14-21 ) is re-synchronized: after every start bit after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s.when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 14-21. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. figure 14-17 summarizes the results of the start bit veri?ation samples. if start bit veri?ation is not successful, the rt clock is reset and a new search for a start bit begins. table 14-17. start bit veri?ation rt3, rt5, and rt7 samples start bit veri?ation noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 samples rt clock rt clock count start bit rxd start bit quali?ation start bit data sampling 11 1 1 1 1 110000 0 00 lsb veri?ation
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 482 freescale semiconductor to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-18 summarizes the results of the data bit samples. note the rt8, rt9, and rt10 samples do not affect start bit veri?ation. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit veri?ation, the noise ?g (nf) is set and the receiver assumes that the bit is a start bit (logic 0). to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-19 summarizes the results of the stop bit samples. table 14-18. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 14-19. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 483 in figure 14-22 the veri?ation samples rt3 and rt5 determine that the ?st low detected was noise and not the beginning of a start bit. the rt clock is reset and the start bit search begins again. the noise ?g is not set because the noise occurred before the start bit was found. figure 14-22. start bit search example 1 in figure 14-23 , veri?ation sample at rt3 is high. the rt3 sample sets the noise ?g. although the perceived bit time is misaligned, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. figure 14-23. start bit search example 2 reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 0 1 111000 00 lsb 0 0 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt11 rt10 rt9 rt14 rt13 rt12 rt2 rt1 rt16 rt15 rt3 rt4 rt5 rt6 rt7 samples rt clock rt clock count actual start bit rxd 11 1 1 11000 0 lsb 0 0 perceived start bit
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 484 freescale semiconductor in figure 14-24 , a large burst of noise is perceived as the beginning of a start bit, although the test sample at rt5 is high. the rt5 sample sets the noise ?g. although this is a worst-case misalignment of perceived bit time, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. figure 14-24. start bit search example 3 figure 14-25 shows the effect of noise early in the start bit time. although this noise does not affect proper synchronization with the start bit time, it does set the noise ?g. figure 14-25. start bit search example 4 reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt13 rt12 rt11 rt16 rt15 rt14 rt4 rt3 rt2 rt1 rt5 rt6 rt7 rt8 rt9 samples rt clock rt clock count actual start bit rxd 10 1 11000 0 lsb 0 perceived start bit reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count perceived and actual start bit rxd 11 1 1100 1 lsb 1 1 1 1
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 485 figure 14-26 shows a burst of noise near the beginning of the start bit that resets the rt clock. the sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error ?g. figure 14-26. start bit search example 5 in figure 14-27 , a noise burst makes the majority of data samples rt8, rt9, and rt10 high. this sets the noise ?g but does not reset the rt clock. in start bits only, the rt8, rt9, and rt10 data samples are ignored. figure 14-27. start bit search example 6 14.4.6.4 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error ?g, fe, in sci status register 1 (scisr1). a break character also sets the fe ?g because a break character has no stop bit. the fe ?g is set at the same time that the rdrf ?g is set. reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 samples rt clock rt clock count start bit rxd 11 1 1101 0 lsb 1 1 1 1 1 00 0 00 0 0 0 no start bit found reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 1 1100 0 lsb 1 1 1 1 0 11 0
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 486 freescale semiconductor 14.4.6.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples (rt8, rt9, and rt10) to fall outside the actual stop bit. a noise error will occur if the rt8, rt9, and rt10 samples are not all the same logical values. a framing error will occur if the receiver clock is misaligned in such a way that the majority of the rt8, rt9, and rt10 stop bit samples are a logic zero. as the receiver samples an incoming frame, it re-synchronizes the rt clock on any valid falling edge within the frame. re synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. 14.4.6.5.1 slow data tolerance figure 14-28 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 14-28. slow data lets take rtr as receiver rt clock and rtt as transmitter rt clock. for an 8-bit data character, it takes the receiver 9 bit times x 16 rtr cycles +7 rtr cycles = 151 rtr cycles to start data sampling of the stop bit. with the misaligned character shown in figure 14-28 , the receiver counts 151 rtr cycles at the point when the count of the transmitting device is 9 bit times x 16 rtt cycles = 144 rtt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: ((151 ?144) / 151) x 100 = 4.63% for a 9-bit data character, it takes the receiver 10 bit times x 16 rtr cycles + 7 rtr cycles = 167 rtr cycles to start data sampling of the stop bit. with the misaligned character shown in figure 14-28 , the receiver counts 167 rtr cycles at the point when the count of the transmitting device is 10 bit times x 16 rtt cycles = 160 rtt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 ?160) / 167) x 100 = 4.19% msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 487 14.4.6.5.2 fast data tolerance figure 14-29 shows how much a fast received frame can be misaligned. the fast stop bit ends at rt10 instead of rt16 but is still sampled at rt8, rt9, and rt10. figure 14-29. fast data for an 8-bit data character, it takes the receiver 9 bit times x 16 rtr cycles + 10 rtr cycles = 154 rtr cycles to ?ish data sampling of the stop bit. with the misaligned character shown in figure 14-29 , the receiver counts 154 rtr cycles at the point when the count of the transmitting device is 10 bit times x 16 rtt cycles = 160 rtt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: ((160 ?154) / 160) x 100 = 3.75% for a 9-bit data character, it takes the receiver 10 bit times x 16 rtr cycles + 10 rtr cycles = 170 rtr cycles to ?ish data sampling of the stop bit. with the misaligned character shown in figure 14-29 , the receiver counts 170 rtr cycles at the point when the count of the transmitting device is 11 bit times x 16 rtt cycles = 176 rtt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: ((176 ?170) /176) x 100 = 3.40% 14.4.6.6 receiver wakeup to enable the sci to ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in sci control register 2 (scicr2) puts the receiver into standby state during which receiver interrupts are disabled.the sci will still load the receive data into the scidrh/l registers, but it will not set the rdrf ?g. the transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. the wake bit in sci control register 1 (scicr1) determines how the sci is brought out of the standby state to process an incoming message. the wake bit enables either idle line wakeup or address mark wakeup. idle or next frame stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 488 freescale semiconductor 14.4.6.6.1 idle input line wakeup (wake = 0) in this wakeup method, an idle condition on the rxd pin clears the rwu bit and wakes up the sci. the initial frame or frames of every message contain addressing information. all receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. any receiver for which a message is not addressed can set its rwu bit and return to the standby state. the rwu bit remains set and the receiver remains on standby until another idle character appears on the rxd pin. idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. the idle character that wakes a receiver does not set the receiver idle bit, idle, or the receive data register full ?g, rdrf. the idle line type bit, ilt, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ilt is in sci control register 1 (scicr1). 14.4.6.6.2 address mark wakeup (wake = 1) in this wakeup method, a logic 1 in the most signi?ant bit (msb) position of a frame clears the rwu bit and wakes up the sci. the logic 1 in the msb position marks a frame as an address frame that contains addressing information. all receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow.any receiver for which a message is not addressed can set its rwu bit and return to the standby state. the rwu bit remains set and the receiver remains on standby until another address frame appears on the rxd pin. the logic 1 msb of an address frame clears the receivers rwu bit before the stop bit is received and sets the rdrf ?g. address mark wakeup allows messages to contain idle characters but requires that the msb be reserved for use in address frames. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle can cause the receiver to wake up immediately. 14.4.7 single-wire operation normally, the sci uses two pins for transmitting and receiving. in single-wire operation, the rxd pin is disconnected from the sci. the sci uses the txd pin for both receiving and transmitting. figure 14-30. single-wire operation (loops = 1, rsrc = 1) rxd transmitter receiver txd
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 489 enable single-wire operation by setting the loops bit and the receiver source bit, rsrc, in sci control register 1 (scicr1). setting the loops bit disables the path from the rxd pin to the receiver. setting the rsrc bit connects the txd pin to the receiver. both the transmitter and receiver must be enabled (te = 1 and re = 1).the txdir bit (scisr2[1]) determines whether the txd pin is going to be used as an input (txdir = 0) or an output (txdir = 1) in this mode of operation. note in single-wire operation data from the txd pin is inverted if rxpol is set. 14.4.8 loop operation in loop operation the transmitter output goes to the receiver input. the rxd pin is disconnected from the sci. figure 14-31. loop operation (loops = 1, rsrc = 0) enable loop operation by setting the loops bit and clearing the rsrc bit in sci control register 1 (scicr1). setting the loops bit disables the path from the rxd pin to the receiver. clearing the rsrc bit connects the transmitter output to the receiver input. both the transmitter and receiver must be enabled (te = 1 and re = 1). note in loop operation data from the transmitter is not recognized by the receiver if rxpol and txpol are not the same. 14.5 initialization/application information 14.5.1 reset initialization see section 14.3.2, ?egister descriptions . 14.5.2 modes of operation 14.5.2.1 run mode normal mode of operation. to initialize a sci transmission, see section 14.4.5.2, ?haracter transmission . rxd transmitter receiver txd
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 490 freescale semiconductor 14.5.2.2 wait mode sci operation in wait mode depends on the state of the sciswai bit in the sci control register 1 (scicr1). if sciswai is clear, the sci operates normally when the cpu is in wait mode. if sciswai is set, sci clock generation ceases and the sci module enters a power-conservation state when the cpu is in wait mode. setting sciswai does not affect the state of the receiver enable bit, re, or the transmitter enable bit, te. if sciswai is set, any transmission or reception in progress stops at wait mode entry. the transmission or reception resumes when either an internal or external interrupt brings the cpu out of wait mode. exiting wait mode by reset aborts any transmission or reception in progress and resets the sci. 14.5.2.3 stop mode the sci is inactive during stop mode for reduced power consumption. the stop instruction does not affect the sci register states, but the sci bus clock will be disabled. the sci operation resumes from where it left off after an external interrupt brings the cpu out of stop mode. exiting stop mode by reset aborts any transmission or reception in progress and resets the sci. the receive input active edge detect circuit is still active in stop mode. an active edge on the receive input can be used to bring the cpu out of stop mode. 14.5.3 interrupt operation this section describes the interrupt originated by the sci block.the mcu must service the interrupt requests. table 14-20 lists the eight interrupt sources of the sci. table 14-20. sci interrupt sources interrupt source local enable description tdre scisr1[7] tie active high level. indicates that a byte was transferred from scidrh/l to the transmit shift register. tc scisr1[6] tcie active high level. indicates that a transmit is complete. rdrf scisr1[5] rie active high level. the rdrf interrupt indicates that received data is available in the sci data register. or scisr1[3] active high level. this interrupt indicates that an overrun condition has occurred. idle scisr1[4] ilie active high level. indicates that receiver input has become idle. rxedgif sciasr1[7] rxedgie active high level. indicates that an active edge (falling for rxpol = 0, rising for rxpol = 1) was detected. berrif sciasr1[1] berrie active high level. indicates that a mismatch between transmitted and received data in a single wire application has happened. bkdif sciasr1[0] brkdie active high level. indicates that a break character has been received.
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 491 14.5.3.1 description of interrupt operation the sci only originates interrupt requests. the following is a description of how the sci makes a request and how the mcu should acknowledge that request. the interrupt vector offset and interrupt number are chip dependent. the sci only has a single interrupt line (sci interrupt signal, active high operation) and all the following interrupts, when generated, are ored together and issued through that port. 14.5.3.1.1 tdre description the tdre interrupt is set high by the sci when the transmit shift register receives a byte from the sci data register. a tdre interrupt indicates that the transmit data register (scidrh/l) is empty and that a new byte can be written to the scidrh/l for transmission.clear tdre by reading sci status register 1 with tdre set and then writing to sci data register low (scidrl). 14.5.3.1.2 tc description the tc interrupt is set by the sci when a transmission has been completed. transmission is completed when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be transmitted. no stop bit is transmitted when sending a break character and the tc ?g is set (providing there is no more data queued for transmission) when the break character has been shifted out. a tc interrupt indicates that there is no transmission in progress. tc is set high when the tdre ?g is set and no data, preamble, or break character is being transmitted. when tc is set, the txd pin becomes idle (logic 1). clear tc by reading sci status register 1 (scisr1) with tc set and then writing to sci data register low (scidrl).tc is cleared automatically when data, preamble, or break is queued and ready to be sent. 14.5.3.1.3 rdrf description the rdrf interrupt is set when the data in the receive shift register transfers to the sci data register. a rdrf interrupt indicates that the received data has been transferred to the sci data register and that the byte can now be read by the mcu. the rdrf interrupt is cleared by reading the sci status register one (scisr1) and then reading sci data register low (scidrl). 14.5.3.1.4 or description the or interrupt is set when software fails to read the sci data register before the receive shift register receives the next frame. the newly acquired data in the shift register will be lost in this case, but the data already in the sci data registers is not affected. the or interrupt is cleared by reading the sci status register one (scisr1) and then reading sci data register low (scidrl). 14.5.3.1.5 idle description the idle interrupt is set when 10 consecutive logic 1s (if m = 0) or 11 consecutive logic 1s (if m = 1) appear on the receiver input. once the idle is cleared, a valid frame must again set the rdrf ?g before an idle condition can set the idle ?g. clear idle by reading sci status register 1 (scisr1) with idle set and then reading sci data register low (scidrl).
serial communication interface (s12sciv5) mc9s12xhy-family reference manual, rev. 1.01 492 freescale semiconductor 14.5.3.1.6 rxedgif description the rxedgif interrupt is set when an active edge (falling if rxpol = 0, rising if rxpol = 1) on the rxd pin is detected. clear rxedgif by writing a ??to the sciasr1 sci alternative status register 1. 14.5.3.1.7 berrif description the berrif interrupt is set when a mismatch between the transmitted and the received data in a single wire application like lin was detected. clear berrif by writing a ??to the sciasr1 sci alternative status register 1. this ?g is also cleared if the bit error detect feature is disabled. 14.5.3.1.8 bkdif description the bkdif interrupt is set when a break signal was received. clear bkdif by writing a ??to the sciasr1 sci alternative status register 1. this ?g is also cleared if break detect feature is disabled. 14.5.4 recovery from wait mode the sci interrupt request can be used to bring the cpu out of wait mode. 14.5.5 recovery from stop mode an active edge on the receive input can be used to bring the cpu out of stop mode.
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 493 chapter 15 serial peripheral interface (s12spiv5) 15.1 introduction the spi module allows a duplex, synchronous, serial communication between the mcu and peripheral devices. software can poll the spi status ?gs or the spi operation can be interrupt driven. 15.1.1 glossary of terms 15.1.2 features the spi includes these distinctive features: master mode and slave mode selectable 8 or 16-bit transfer width bidirectional mode slave select output mode fault error ?g with cpu interrupt capability double-buffered data register serial clock with programmable polarity and phase control of spi operation during wait mode 15.1.3 modes of operation the spi functions in three modes: run, wait, and stop. run mode this is the basic mode of operation. wait mode spi serial peripheral interface ss slave select sck serial clock mosi master output, slave input miso master input, slave output momi master output, master input siso slave input, slave output
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual, rev. 1.01 494 freescale semiconductor spi operation in wait mode is a con?urable low power mode, controlled by the spiswai bit located in the spicr2 register. in wait mode, if the spiswai bit is clear, the spi operates like in run mode. if the spiswai bit is set, the spi goes into a power conservative state, with the spi clock generation turned off. if the spi is con?ured as a master, any transmission in progress stops, but is resumed after cpu goes into run mode. if the spi is con?ured as a slave, reception and transmission of data continues, so that the slave stays synchronized to the master. stop mode the spi is inactive in stop mode for reduced power consumption. if the spi is con?ured as a master, any transmission in progress stops, but is resumed after cpu goes into run mode. if the spi is con?ured as a slave, reception and transmission of data continues, so that the slave stays synchronized to the master. for a detailed description of operating modes, please refer to section 15.4.7, ?ow power mode options . 15.1.4 block diagram figure 15-1 gives an overview on the spi architecture. the main parts of the spi are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 495 figure 15-1. spi block diagram 15.2 external signal description this section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. the spi module has a total of four external pins. 15.2.1 mosi ?master out/slave in pin this pin is used to transmit data out of the spi module when it is con?ured as a master and receive data when it is con?ured as slave. 15.2.2 miso ?master in/slave out pin this pin is used to transmit data out of the spi module when it is con?ured as a slave and receive data when it is con?ured as master. spi control register 1 spi control register 2 spi baud rate register spi status register spi data register shifter port control logic mosi sck interrupt control spi msb lsb lsbfe=1 lsbfe=0 lsbfe=0 lsbfe=1 data in lsbfe=1 lsbfe=0 data out baud rate generator prescaler bus clock counter clock select sppr 3 3 spr baud rate phase + polarity control master slave sck in sck out master baud rate slave baud rate phase + polarity control control control cpol cpha 2 bidiroe spc0 2 shift sample clock clock modf spif sptef spi request interrupt ss
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual, rev. 1.01 496 freescale semiconductor 15.2.3 ss ?slave select pin this pin is used to output the select signal from the spi module to another peripheral with which a data transfer is to take place when it is con?ured as a master and it is used as an input to receive the slave select signal when the spi is con?ured as slave. 15.2.4 sck ?serial clock pin in master mode, this is the synchronous output clock. in slave mode, this is the synchronous input clock. 15.3 memory map and register de?ition this section provides a detailed description of address space and registers used by the spi. 15.3.1 module memory map the memory map for the spi is given in figure 15-2 . the address listed for each register is the sum of a base address and an address offset. the base address is de?ed at the soc level and the address offset is de?ed at the module level. reads from the reserved bits return zeros and writes to the reserved bits have no effect. register name bit 7 6 5 4 3 2 1 bit 0 0x0000 spicr1 r spie spe sptie mstr cpol cpha ssoe lsbfe w 0x0001 spicr2 r0 xfrw 0 modfen bidiroe 0 spiswai spc0 w 0x0002 spibr r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w 0x0003 spisr r spif 0 sptef modf 0 0 0 0 w 0x0004 spidrh r r15 r14 r13 r12 r11 r10 r9 r8 t15 t14 t13 t12 t11 t10 t9 t8 w 0x0005 spidrl rr7r6r5r4r3r2r1r0 t7 t6 t5 t4 t3 t2 t1 t0 w 0x0006 reserved r w 0x0007 reserved r w = unimplemented or reserved figure 15-2. spi register summary
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 497 15.3.2 register descriptions this section consists of register descriptions in address order. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. 15.3.2.1 spi control register 1 (spicr1) read: anytime write: anytime module base +0x0000 76543210 r spie spe sptie mstr cpol cpha ssoe lsbfe w reset 0 0 0 00100 figure 15-3. spi control register 1 (spicr1) table 15-1. spicr1 field descriptions field description 7 spie spi interrupt enable bit ?this bit enables spi interrupt requests, if spif or modf status ?g is set. 0 spi interrupts disabled. 1 spi interrupts enabled. 6 spe spi system enable bit ?this bit enables the spi system and dedicates the spi port pins to spi system functions. if spe is cleared, spi is disabled and forced into idle state, status bits in spisr register are reset. 0 spi disabled (lower power consumption). 1 spi enabled, port pins are dedicated to spi functions. 5 sptie spi transmit interrupt enable ?this bit enables spi interrupt requests, if sptef ?g is set. 0 sptef interrupt disabled. 1 sptef interrupt enabled. 4 mstr spi master/slave mode select bit ?this bit selects whether the spi operates in master or slave mode. switching the spi from master to slave or vice versa forces the spi system into idle state. 0 spi is in slave mode. 1 spi is in master mode. 3 cpol spi clock polarity bit this bit selects an inverted or non-inverted spi clock. to transmit data between spi modules, the spi modules must have identical cpol values. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 active-high clocks selected. in idle state sck is low. 1 active-low clocks selected. in idle state sck is high. 2 cpha spi clock phase bit this bit is used to select the spi clock format. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 sampling of data occurs at odd edges (1,3,5,...) of the sck clock. 1 sampling of data occurs at even edges (2,4,6,...) of the sck clock.
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual, rev. 1.01 498 freescale semiconductor 15.3.2.2 spi control register 2 (spicr2) read: anytime write: anytime; writes to the reserved bits have no effect 1 ssoe slave select output enable ?the ss output feature is enabled only in master mode, if modfen is set, by asserting the ssoe as shown in table 15-2 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 lsbfe lsb-first enable ?this bit does not affect the position of the msb and lsb in the data register. reads and writes of the data register always have the msb in the highest bit position. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 data is transferred most signi?ant bit ?st. 1 data is transferred least signi?ant bit ?st. table 15-2. ss input / output selection modfen ssoe master mode slave mode 00 ss not used by spi ss input 01 ss not used by spi ss input 10 ss input with modf feature ss input 11 ss is slave select output ss input module base +0x0001 76543210 r0 xfrw 0 modfen bidiroe 0 spiswai spc0 w reset 0 0 0 00000 = unimplemented or reserved figure 15-4. spi control register 2 (spicr2) table 15-1. spicr1 field descriptions (continued) field description
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 499 table 15-3. spicr2 field descriptions field description 6 xfrw transfer width this bit is used for selecting the data transfer width. if 8-bit transfer width is selected, spidrl becomes the dedicated data register and spidrh is unused. if 16-bit transfer width is selected, spidrh and spidrl form a 16-bit data register. please refer to section 15.3.2.4, ?pi status register (spisr) for information about transmit/receive data handling and the interrupt ?g clearing mechanism. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 8-bit transfer width (n = 8) 1 1 16-bit transfer width (n = 16) 1 1 n is used later in this document as a placeholder for the selected transfer width. 4 modfen mode fault enable bit ?this bit allows the modf failure to be detected. if the spi is in master mode and modfen is cleared, then the ss port pin is not used by the spi. in slave mode, the ss is available only as an input regardless of the value of modfen. for an overview on the impact of the modfen bit on the ss port pin con?uration, refer to table 15-2 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 0 ss port pin is not used by the spi. 1 ss port pin with modf feature. 3 bidiroe output enable in the bidirectional mode of operation this bit controls the mosi and miso output buffer of the spi, when in bidirectional mode of operation (spc0 is set). in master mode, this bit controls the output buffer of the mosi port, in slave mode it controls the output buffer of the miso port. in master mode, with spc0 set, a change of this bit will abort a transmission in progress and force the spi into idle state. 0 output buffer disabled. 1 output buffer enabled. 1 spiswai spi stop in wait mode bit ?this bit is used for power conservation while in wait mode. 0 spi clock operates normally in wait mode. 1 stop spi clock generation when in wait mode. 0 spc0 serial pin control bit 0 ?this bit enables bidirectional pin con?urations as shown in table 15-4 . in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. table 15-4. bidirectional pin con?urations pin mode spc0 bidiroe miso mosi master mode of operation normal 0 x master in master out bidirectional 1 0 miso not used by spi master in 1 master i/o slave mode of operation normal 0 x slave out slave in bidirectional 1 0 slave in mosi not used by spi 1 slave i/o
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual, rev. 1.01 500 freescale semiconductor 15.3.2.3 spi baud rate register (spibr) read: anytime write: anytime; writes to the reserved bits have no effect the baud rate divisor equation is as follows: baudratedivisor = (sppr + 1) ? 2 (spr + 1) eqn. 15-1 the baud rate can be calculated with the following equation: baud rate = busclock / baudratedivisor eqn. 15-2 note for maximum allowed baud rates, please refer to the spi electrical speci?ation in the electricals chapter of this data sheet. module base +0x0002 76543210 r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w reset 0 0 0 00000 = unimplemented or reserved figure 15-5. spi baud rate register (spibr) table 15-5. spibr field descriptions field description 6? sppr[2:0] spi baud rate preselection bits these bits specify the spi baud rates as shown in table 15-6 . in master mode, a change of these bits will abort a transmission in progress and force the spi system into idle state. 2? spr[2:0] spi baud rate selection bits these bits specify the spi baud rates as shown in table 15-6 . in master mode, a change of these bits will abort a transmission in progress and force the spi system into idle state. table 15-6. example spi baud rate selection (25 mhz bus clock) (sheet 1 of 3) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate 0 0 0 0 0 0 2 12.5 mbit/s 0 0 0 0 0 1 4 6.25 mbit/s 0 0 0 0 1 0 8 3.125 mbit/s 0 0 0 0 1 1 16 1.5625 mbit/s 0 0 0 1 0 0 32 781.25 kbit/s 0 0 0 1 0 1 64 390.63 kbit/s 0 0 0 1 1 0 128 195.31 kbit/s 0 0 0 1 1 1 256 97.66 kbit/s 0 0 1 0 0 0 4 6.25 mbit/s 0 0 1 0 0 1 8 3.125 mbit/s 0 0 1 0 1 0 16 1.5625 mbit/s 0 0 1 0 1 1 32 781.25 kbit/s
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 501 0 0 1 1 0 0 64 390.63 kbit/s 0 0 1 1 0 1 128 195.31 kbit/s 0 0 1 1 1 0 256 97.66 kbit/s 0 0 1 1 1 1 512 48.83 kbit/s 0 1 0 0 0 0 6 4.16667 mbit/s 0 1 0 0 0 1 12 2.08333 mbit/s 0 1 0 0 1 0 24 1.04167 mbit/s 0 1 0 0 1 1 48 520.83 kbit/s 0 1 0 1 0 0 96 260.42 kbit/s 0 1 0 1 0 1 192 130.21 kbit/s 0 1 0 1 1 0 384 65.10 kbit/s 0 1 0 1 1 1 768 32.55 kbit/s 0 1 1 0 0 0 8 3.125 mbit/s 0 1 1 0 0 1 16 1.5625 mbit/s 0 1 1 0 1 0 32 781.25 kbit/s 0 1 1 0 1 1 64 390.63 kbit/s 0 1 1 1 0 0 128 195.31 kbit/s 0 1 1 1 0 1 256 97.66 kbit/s 0 1 1 1 1 0 512 48.83 kbit/s 0 1 1 1 1 1 1024 24.41 kbit/s 1 0 0 0 0 0 10 2.5 mbit/s 1 0 0 0 0 1 20 1.25 mbit/s 1 0 0 0 1 0 40 625 kbit/s 1 0 0 0 1 1 80 312.5 kbit/s 1 0 0 1 0 0 160 156.25 kbit/s 1 0 0 1 0 1 320 78.13 kbit/s 1 0 0 1 1 0 640 39.06 kbit/s 1 0 0 1 1 1 1280 19.53 kbit/s 1 0 1 0 0 0 12 2.08333 mbit/s 1 0 1 0 0 1 24 1.04167 mbit/s 1 0 1 0 1 0 48 520.83 kbit/s 1 0 1 0 1 1 96 260.42 kbit/s 1 0 1 1 0 0 192 130.21 kbit/s 1 0 1 1 0 1 384 65.10 kbit/s 1 0 1 1 1 0 768 32.55 kbit/s 1 0 1 1 1 1 1536 16.28 kbit/s 1 1 0 0 0 0 14 1.78571 mbit/s 1 1 0 0 0 1 28 892.86 kbit/s 1 1 0 0 1 0 56 446.43 kbit/s 1 1 0 0 1 1 112 223.21 kbit/s 1 1 0 1 0 0 224 111.61 kbit/s 1 1 0 1 0 1 448 55.80 kbit/s table 15-6. example spi baud rate selection (25 mhz bus clock) (sheet 2 of 3) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual, rev. 1.01 502 freescale semiconductor 15.3.2.4 spi status register (spisr) read: anytime write: has no effect 1 1 0 1 1 0 896 27.90 kbit/s 1 1 0 1 1 1 1792 13.95 kbit/s 1 1 1 0 0 0 16 1.5625 mbit/s 1 1 1 0 0 1 32 781.25 kbit/s 1 1 1 0 1 0 64 390.63 kbit/s 1 1 1 0 1 1 128 195.31 kbit/s 1 1 1 1 0 0 256 97.66 kbit/s 1 1 1 1 0 1 512 48.83 kbit/s 1 1 1 1 1 0 1024 24.41 kbit/s 1 1 1 1 1 1 2048 12.21 kbit/s module base +0x0003 76543210 r spif 0 sptef modf 0000 w reset 0 0 1 00000 = unimplemented or reserved figure 15-6. spi status register (spisr) table 15-7. spisr field descriptions field description 7 spif spif interrupt flag ?this bit is set after received data has been transferred into the spi data register. for information about clearing spif flag, please refer to table 15-8 . 0 transfer not yet complete. 1 new data copied to spidr. 5 sptef spi transmit empty interrupt flag ?if set, this bit indicates that the transmit data register is empty. for information about clearing this bit and placing data into the transmit data register, please refer to table 15-9 . 0 spi data register not empty. 1 spi data register empty. 4 modf mode fault flag this bit is set if the ss input becomes low while the spi is con?ured as a master and mode fault detection is enabled, modfen bit of spicr2 register is set. refer to modfen bit description in section 15.3.2.2, ?pi control register 2 (spicr2) . the ?g is cleared automatically by a read of the spi status register (with modf set) followed by a write to the spi control register 1. 0 mode fault has not occurred. 1 mode fault has occurred. table 15-6. example spi baud rate selection (25 mhz bus clock) (sheet 3 of 3) sppr2 sppr1 sppr0 spr2 spr1 spr0 baud rate divisor baud rate
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 503 table 15-8. spif interrupt flag clearing sequence table 15-9. sptef interrupt flag clearing sequence xfrw bit spif interrupt flag clearing sequence 0 read spisr with spif == 1 then read spidrl 1 read spisr with spif == 1 then byte read spidrl 1 1 data in spidrh is lost in this case. or byte read spidrh 2 2 spidrh can be read repeatedly without any effect on spif. spif flag is cleared only by the read of spidrl after reading spisr with spif == 1. byte read spidrl or word read (spidrh:spidrl) xfrw bit sptef interrupt flag clearing sequence 0 read spisr with sptef == 1 then write to spidrl 1 1 any write to spidrh or spidrl with sptef == 0 is effectively ignored. 1 read spisr with sptef == 1 then byte write to spidrl 12 2 data in spidrh is unde?ed in this case. or byte write to spidrh 13 3 spidrh can be written repeatedly without any effect on sptef. sptef flag is cleared only by writing to spidrl after reading spisr with sptef == 1. byte write to spidrl 1 or word write to (spidrh:spidrl) 1
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual, rev. 1.01 504 freescale semiconductor 15.3.2.5 spi data register (spidr = spidrh:spidrl) read: anytime; read data only valid when spif is set write: anytime the spi data register is both the input and output register for spi data. a write to this register allows data to be queued and transmitted. for an spi con?ured as a master, queued data is transmitted immediately after the previous transmission has completed. the spi transmitter empty ?g sptef in the spisr register indicates when the spi data register is ready to accept new data. received data in the spidr is valid when spif is set. if spif is cleared and data has been received, the received data is transferred from the receive shift register to the spidr and spif is set. if spif is set and not serviced, and a second data value has been received, the second received data is kept as valid data in the receive shift register until the start of another transmission. the data in the spidr does not change. if spif is set and valid data is in the receive shift register, and spif is serviced before the start of a third transmission, the data in the receive shift register is transferred into the spidr and spif remains set (see figure 15-9 ). if spif is set and valid data is in the receive shift register, and spif is serviced after the start of a third transmission, the data in the receive shift register has become invalid and is not transferred into the spidr (see figure 15-10 ). module base +0x0004 76543210 r r15 r14 r13 r12 r11 r10 r9 r8 w t15 t14 t13 t12 t11 t10 t9 t8 reset 0 0 0 00000 figure 15-7. spi data register high (spidrh) module base +0x0005 76543210 r r7 r6 r5 r4 r3 r2 r1 r0 w t7 t6 t5 t4 t3 t2 t1 t0 reset 0 0 0 00000 figure 15-8. spi data register low (spidrl)
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 505 figure 15-9. reception with spif serviced in time figure 15-10. reception with spif serviced too late 15.4 functional description the spi module allows a duplex, synchronous, serial communication between the mcu and peripheral devices. software can poll the spi status ?gs or spi operation can be interrupt driven. the spi system is enabled by setting the spi enable (spe) bit in spi control register 1. while spe is set, the four associated spi port pins are dedicated to the spi function as: slave select ( ss) serial clock (sck) master out/slave in (mosi) master in/slave out (miso) receive shift register spif spi data register data a data b data a data a received data b received data c data c spif serviced data c received data b = unspeci?d = reception in progress receive shift register spif spi data register data a data b data a data a received data b received data c data c spif serviced data c received data b lost = unspeci?d = reception in progress
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual, rev. 1.01 506 freescale semiconductor the main element of the spi system is the spi data register. the n-bit 2 data register in the master and the n-bit 2 data register in the slave are linked by the mosi and miso pins to form a distributed 2n-bit 2 register. when a data transfer operation is performed, this 2n-bit 2 register is serially shifted n 2 bit positions by the s-clock from the master, so data is exchanged between the master and the slave. data written to the master spi data register becomes the output data for the slave, and data read from the master spi data register after a transfer operation is the input data from the slave. a read of spisr with sptef = 1 followed by a write to spidr puts data into the transmit data register. when a transfer is complete and spif is cleared, received data is moved into the receive data register. this data register acts as the spi receive data register for reads and as the spi transmit data register for writes. a common spi data register address is shared for reading data from the read data buffer and for writing data to the transmit data register. the clock phase control bit (cpha) and a clock polarity control bit (cpol) in the spi control register 1 (spicr1) select one of four possible clock formats to be used by the spi system. the cpol bit simply selects a non-inverted or inverted clock. the cpha bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered sck edges or on even numbered sck edges (see section 15.4.3, ?ransmission formats ). the spi can be con?ured to operate as a master or as a slave. when the mstr bit in spi control register1 is set, master mode is selected, when the mstr bit is clear, slave mode is selected. note a change of cpol or mstr bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided. 15.4.1 master mode the spi operates in master mode when the mstr bit is set. only a master spi module can initiate transmissions. a transmission begins by writing to the master spi data register. if the shift register is empty, data immediately transfers to the shift register. data begins shifting out on the mosi pin under the control of the serial clock. serial clock the spr2, spr1, and spr0 baud rate selection bits, in conjunction with the sppr2, sppr1, and sppr0 baud rate preselection bits in the spi baud rate register, control the baud rate generator and determine the speed of the transmission. the sck pin is the spi clock output. through the sck pin, the baud rate generator of the master controls the shift register of the slave peripheral. mosi, miso pin in master mode, the function of the serial data output pin (mosi) and the serial data input pin (miso) is determined by the spc0 and bidiroe control bits. ss pin if modfen and ssoe are set, the ss pin is con?ured as slave select output. the ss output becomes low during each transmission and is high when the spi is in idle state. 2. n depends on the selected transfer width, please refer to section 15.3.2.2, ?pi control register 2 (spicr2)
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 507 if modfen is set and ssoe is cleared, the ss pin is con?ured as input for detecting mode fault error. if the ss input becomes low this indicates a mode fault error where another master tries to drive the mosi and sck lines. in this case, the spi immediately switches to slave mode, by clearing the mstr bit and also disables the slave output buffer miso (or siso in bidirectional mode). so the result is that all outputs are disabled and sck, mosi, and miso are inputs. if a transmission is in progress when the mode fault occurs, the transmission is aborted and the spi is forced into idle state. this mode fault error also sets the mode fault (modf) ?g in the spi status register (spisr). if the spi interrupt enable bit (spie) is set when the modf ?g becomes set, then an spi interrupt sequence is also requested. when a write to the spi data register in the master occurs, there is a half sck-cycle delay. after the delay, sck is started within the master. the rest of the transfer operation differs slightly, depending on the clock format speci?d by the spi clock phase bit, cpha, in spi control register 1 (see section 15.4.3, ?ransmission formats? . note a change of the bits cpol, cpha, ssoe, lsbfe, xfrw, modfen, spc0, or bidiroe with spc0 set, sppr2-sppr0 and spr2-spr0 in master mode will abort a transmission in progress and force the spi into idle state. the remote slave cannot detect this, therefore the master must ensure that the remote slave is returned to idle state. 15.4.2 slave mode the spi operates in slave mode when the mstr bit in spi control register 1 is clear. serial clock in slave mode, sck is the spi clock input from the master. miso, mosi pin in slave mode, the function of the serial data output pin (miso) and serial data input pin (mosi) is determined by the spc0 bit and bidiroe bit in spi control register 2. ss pin the ss pin is the slave select input. before a data transmission occurs, the ss pin of the slave spi must be low. ss must remain low until the transmission is complete. if ss goes high, the spi is forced into idle state. the ss input also controls the serial data output pin, if ss is high (not selected), the serial data output pin is high impedance, and, if ss is low, the ?st bit in the spi data register is driven out of the serial data output pin. also, if the slave is not selected ( ss is high), then the sck input is ignored and no internal shifting of the spi shift register occurs. although the spi is capable of duplex operation, some spi peripherals are capable of only receiving spi data in a slave mode. for these simpler devices, there is no serial data out pin.
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual, rev. 1.01 508 freescale semiconductor note when peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slaves serial data output line. as long as no more than one slave device drives the system slaves serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. if the cpha bit in spi control register 1 is clear, odd numbered edges on the sck input cause the data at the serial data input pin to be latched. even numbered edges cause the value previously latched from the serial data input pin to shift into the lsb or msb of the spi shift register, depending on the lsbfe bit. if the cpha bit is set, even numbered edges on the sck input cause the data at the serial data input pin to be latched. odd numbered edges cause the value previously latched from the serial data input pin to shift into the lsb or msb of the spi shift register, depending on the lsbfe bit. when cpha is set, the ?st edge is used to get the ?st data bit onto the serial data output pin. when cpha is clear and the ss input is low (slave selected), the ?st bit of the spi data is driven out of the serial data output pin. after the nth 3 shift, the transfer is considered complete and the received data is transferred into the spi data register. to indicate transfer is complete, the spif ?g in the spi status register is set. note a change of the bits cpol, cpha, ssoe, lsbfe, modfen, spc0, or bidiroe with spc0 set in slave mode will corrupt a transmission in progress and must be avoided. 15.4.3 transmission formats during an spi transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. the serial clock (sck) synchronizes shifting and sampling of the information on the two serial data lines. a slave select line allows selection of an individual slave spi device; slave devices that are not selected do not interfere with spi bus activities. optionally, on a master spi device, the slave select line can be used to indicate multiple-master bus contention. figure 15-11. master/slave transfer block diagram 3. n depends on the selected transfer width, please refer to section 15.3.2.2, ?pi control register 2 (spicr2) shift register shift register baud rate generator master spi slave spi mosi mosi miso miso sck sck ss ss v dd
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 509 15.4.3.1 clock phase and polarity controls using two bits in the spi control register 1, software selects one of four combinations of serial clock phase and polarity. the cpol clock polarity control bit speci?s an active high or low clock and has no signi?ant effect on the transmission format. the cpha clock phase control bit selects one of two fundamentally different transmission formats. clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. 15.4.3.2 cpha = 0 transfer format the ?st edge on the sck line is used to clock the ?st data bit of the slave into the master and the ?st data bit of the master into the slave. in some peripherals, the ?st bit of the slaves data is available at the slaves data out pin as soon as the slave is selected. in this format, the ?st sck edge is issued a half cycle after ss has become low. a half sck cycle later, the second edge appears on the sck line. when this second edge occurs, the value previously latched from the serial data input pin is shifted into the lsb or msb of the shift register, depending on lsbfe bit. after this second edge, the next bit of the spi master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. this process continues for a total of 16 edges on the sck line, with data being latched on odd numbered edges and shifted on even numbered edges. data reception is double buffered. data is shifted serially into the spi shift register during the transfer and is transferred to the parallel spi data register after the last bit is shifted in. after 2n 4 (last) sck edges: data that was previously in the master spi data register should now be in the slave data register and the data that was in the slave data register should be in the master. the spif ?g in the spi status register is set, indicating that the transfer is complete. figure 15-12 is a timing diagram of an spi transfer where cpha = 0. sck waveforms are shown for cpol = 0 and cpol = 1. the diagram may be interpreted as a master or slave timing diagram because the sck, miso, and mosi pins are connected directly between the master and the slave. the miso signal is the output from the slave and the mosi signal is the output from the master. the ss pin of the master must be either high or recon?ured as a general-purpose output not affecting the spi. 4. n depends on the selected transfer width, please refer to section 15.3.2.2, ?pi control register 2 (spicr2)
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual, rev. 1.01 510 freescale semiconductor figure 15-12. spi clock format 0 (cpha = 0), with 8-bit transfer width selected (xfrw = 0) t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb ?st (lsbfe = 0): lsb ?st (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the ?st sck edge t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time) t l , t t , and t i are guaranteed for the master mode and required for the slave mode. 1 2 34 56 78910111213141516 sck edge number end of idle state begin of idle state
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 511 figure 15-13. spi clock format 0 (cpha = 0), with 16-bit transfer width selected (xfrw = 1) in slave mode, if the ss line is not deasserted between the successive transmissions then the content of the spi data register is not transmitted; instead the last received data is transmitted. if the ss line is deasserted for at least minimum idle time (half sck cycle) between successive transmissions, then the content of the spi data register is transmitted. in master mode, with slave select output enabled the ss line is always deasserted and reasserted between successive transfers for at least minimum idle time. 15.4.3.3 cpha = 1 transfer format some peripherals require the ?st sck edge before the ?st data bit becomes available at the data out pin, the second edge clocks data into the system. in this format, the ?st sck edge is issued by setting the cpha bit at the beginning of the n 5 -cycle transfer operation. the ?st edge of sck occurs immediately after the half sck clock cycle synchronization delay. this ?st edge commands the slave to transfer its ?st data bit to the serial data input pin of the master. a half sck cycle later, the second edge appears on the sck pin. this is the latching edge for both the master and slave. 5. n depends on the selected transfer width, please refer to section 15.3.2.2, ?pi control register 2 (spicr2) t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb ?st (lsbfe = 0) lsb ?st (lsbfe = 1) msb lsb lsb msb bit 13 bit 2 bit 14 bit 1 bit 12 bit 3 bit 11 bit 4 bit 5 change o sel ss (i) mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the ?st sck edge t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time) t l , t t , and t i are guaranteed for the master mode and required for the slave mode. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sck edge number end of idle state begin of idle state 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bit 10 bit 9 bit 8 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 6 bit 5 bit 7 bit 8 bit 9 bit 10bit 11 bit 12bit 13 bit 14
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual, rev. 1.01 512 freescale semiconductor when the third edge occurs, the value previously latched from the serial data input pin is shifted into the lsb or msb of the spi shift register, depending on lsbfe bit. after this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. this process continues for a total of n 5 edges on the sck line with data being latched on even numbered edges and shifting taking place on odd numbered edges. data reception is double buffered, data is serially shifted into the spi shift register during the transfer and is transferred to the parallel spi data register after the last bit is shifted in. after 2n 5 sck edges: data that was previously in the spi data register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master. the spif ?g bit in spisr is set indicating that the transfer is complete. figure 15-14 shows two clocking variations for cpha = 1. the diagram may be interpreted as a master or slave timing diagram because the sck, miso, and mosi pins are connected directly between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the ss pin of the master must be either high or recon?ured as a general-purpose output not affecting the spi. figure 15-14. spi clock format 1 (cpha = 1), with 8-bit transfer width selected (xfrw = 0) t l t t for t t , t l , t l minimum 1/2 sck t i t l if next transfer begins here begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb ?st (lsbfe = 0): lsb ?st (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) mosi pin miso pin master only mosi/miso t l = minimum leading time before the ?st sck edge, not required for back-to-back transfers t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time), not required for back-to-back transfers 1 2 34 56 78910111213141516 sck edge number end of idle state begin of idle state
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 513 figure 15-15. spi clock format 1 (cpha = 1), with 16-bit transfer width selected (xfrw = 1) the ss line can remain active low between successive transfers (can be tied low at all times). this format is sometimes preferred in systems having a single ?ed master and a single slave that drive the miso data line. back-to-back transfers in master mode in master mode, if a transmission has completed and new data is available in the spi data register, this data is sent out immediately without a trailing and minimum idle time. the spi interrupt request ?g (spif) is common to both the master and slave modes. spif gets set one half sck cycle after the last sck edge. 15.4.4 spi baud rate generation baud rate generation consists of a series of divider stages. six bits in the spi baud rate register (sppr2, sppr1, sppr0, spr2, spr1, and spr0) determine the divisor to the spi module clock which results in the spi baud rate. the spi clock rate is determined by the product of the value in the baud rate preselection bits (sppr2?ppr0) and the value in the baud rate selection bits (spr2?pr0). the module clock divisor equation is shown in equation 15-3 . baudratedivisor = (sppr + 1) ? 2 (spr + 1) eqn. 15-3 t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb ?st (lsbfe = 0) lsb ?st (lsbfe = 1) msb lsb lsb msb bit 13 bit 2 bit 14 bit 1 bit 12 bit 3 bit 11 bit 4 bit 5 change o sel ss (i) mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the ?st sck edge, not required for back-to-back transfers t t = minimum trailing time after the last sck edge t i = minimum idling time between transfers (minimum ss high time), not required for back-to-back transfers 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sck edge number end of idle state begin of idle state 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bit 10 bit 9 bit 8 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 6 bit 5 bit 7 bit 8 bit 9 bit 10bit 11 bit 12bit 13 bit 14
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual, rev. 1.01 514 freescale semiconductor when all bits are clear (the default condition), the spi module clock is divided by 2. when the selection bits (spr2?pr0) are 001 and the preselection bits (sppr2?ppr0) are 000, the module clock divisor becomes 4. when the selection bits are 010, the module clock divisor becomes 8, etc. when the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. when the preselection bits are 010, the divisor is multiplied by 3, etc. see table 15-6 for baud rate calculations for all bit conditions, based on a 25 mhz bus clock. the two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. the baud rate generator is activated only when the spi is in master mode and a serial transfer is taking place. in the other cases, the divider is disabled to decrease i dd current. note for maximum allowed baud rates, please refer to the spi electrical speci?ation in the electricals chapter of this data sheet. 15.4.5 special features 15.4.5.1 ss output the ss output feature automatically drives the ss pin low during transmission to select external devices and drives it high during idle to deselect external devices. when ss output is selected, the ss output pin is connected to the ss input pin of the external device. the ss output is available only in master mode during normal spi operation by asserting ssoe and modfen bit as shown in table 15-2 . the mode fault feature is disabled while ss output is enabled. note care must be taken when using the ss output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters. 15.4.5.2 bidirectional mode (momi or siso) the bidirectional mode is selected when the spc0 bit is set in spi control register 2 (see table 15-10 ). in this mode, the spi uses only one serial data pin for the interface with external device(s). the mstr bit decides which pin to use. the mosi pin becomes the serial data i/o (momi) pin for the master mode, and the miso pin becomes serial data i/o (siso) pin for the slave mode. the miso pin in master mode and mosi pin in slave mode are not used by the spi.
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 515 the direction of each serial i/o pin depends on the bidiroe bit. if the pin is con?ured as an output, serial data from the shift register is driven out on the pin. the same pin is also the serial input to the shift register. the sck is output for the master mode and input for the slave mode. the ss is the input or output for the master mode, and it is always the input for the slave mode. the bidirectional mode does not affect sck and ss functions. note in bidirectional master mode, with mode fault enabled, both data pins miso and mosi can be occupied by the spi, though mosi is normally used for transmissions in bidirectional mode and miso is not used by the spi. if a mode fault occurs, the spi is automatically switched to slave mode. in this case miso becomes occupied by the spi and mosi is not used. this must be considered, if the miso pin is used for another purpose. 15.4.6 error conditions the spi has one error condition: mode fault error 15.4.6.1 mode fault error if the ss input becomes low while the spi is con?ured as a master, it indicates a system error where more than one master may be trying to drive the mosi and sck lines simultaneously. this condition is not permitted in normal operation, the modf bit in the spi status register is set automatically, provided the modfen bit is set. in the special case where the spi is in master mode and modfen bit is cleared, the ss pin is not used by the spi. in this special case, the mode fault error function is inhibited and modf remains cleared. in case table 15-10. normal mode and bidirectional mode when spe = 1 master mode mstr = 1 slave mode mstr = 0 normal mode spc0 = 0 bidirectional mode spc0 = 1 spi mosi miso serial out serial in spi mosi miso serial in serial out spi momi serial out serial in bidiroe spi siso serial in serial out bidiroe
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual, rev. 1.01 516 freescale semiconductor the spi system is con?ured as a slave, the ss pin is a dedicated input pin. mode fault error doesnt occur in slave mode. if a mode fault error occurs, the spi is switched to slave mode, with the exception that the slave output buffer is disabled. so sck, miso, and mosi pins are forced to be high impedance inputs to avoid any possibility of con?ct with another output driver. a transmission in progress is aborted and the spi is forced into idle state. if the mode fault error occurs in the bidirectional mode for a spi system con?ured in master mode, output enable of the momi (mosi in bidirectional mode) is cleared if it was set. no mode fault error occurs in the bidirectional mode for spi system con?ured in slave mode. the mode fault ?g is cleared automatically by a read of the spi status register (with modf set) followed by a write to spi control register 1. if the mode fault ?g is cleared, the spi becomes a normal master or slave again. note if a mode fault error occurs and a received data byte is pending in the receive shift register, this data byte will be lost. 15.4.7 low power mode options 15.4.7.1 spi in run mode in run mode with the spi system enable (spe) bit in the spi control register clear, the spi system is in a low-power, disabled state. spi registers remain accessible, but clocks to the core of this module are disabled. 15.4.7.2 spi in wait mode spi operation in wait mode depends upon the state of the spiswai bit in spi control register 2. if spiswai is clear, the spi operates normally when the cpu is in wait mode if spiswai is set, spi clock generation ceases and the spi module enters a power conservation state when the cpu is in wait mode. if spiswai is set and the spi is configured for master, any transmission and reception in progress stops at wait mode entry. the transmission and reception resumes when the spi exits wait mode. if spiswai is set and the spi is configured as a slave, any transmission and reception in progress continues if the sck continues to be driven from the master. this keeps the slave synchronized to the master and the sck. if the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is currently sending its spidr to the master, it will continue to send the same byte. else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte).
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 517 note care must be taken when expecting data from a master while the slave is in wait or stop mode. even though the shift register will continue to operate, the rest of the spi is shut down (i.e., a spif interrupt will not be generated until exiting stop or wait mode). also, the byte from the shift register will not be copied into the spidr register until after the slave spi has exited wait or stop mode. in slave mode, a received byte pending in the receive shift register will be lost when entering wait or stop mode. an spif ?g and spidr copy is generated only if wait mode is entered or exited during a tranmission. if the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a spif nor a spidr copy will occur. 15.4.7.3 spi in stop mode stop mode is dependent on the system. the spi enters stop mode when the module clock is disabled (held high or low). if the spi is in master mode and exchanging data when the cpu enters stop mode, the transmission is frozen until the cpu exits stop mode. after stop, data to and from the external spi is exchanged correctly. in slave mode, the spi will stay synchronized with the master. the stop mode is not dependent on the spiswai bit. 15.4.7.4 reset the reset values of registers and signals are described in section 15.3, ?emory map and register de?ition , which details the registers and their bit ?lds. if a data transmission occurs in slave mode after reset without a write to spidr, it will transmit garbage, or the data last received from the master before the reset. reading from the spidr after reset will always read zeros. 15.4.7.5 interrupts the spi only originates interrupt requests when spi is enabled (spe bit in spicr1 set). the following is a description of how the spi makes a request and how the mcu should acknowledge that request. the interrupt vector offset and interrupt priority are chip dependent. the interrupt ?gs modf, spif, and sptef are logically ored to generate an interrupt request. 15.4.7.5.1 modf modf occurs when the master detects an error on the ss pin. the master spi must be con?ured for the modf feature (see table 15-2 ). after modf is set, the current transfer is aborted and the following bit is changed: mstr = 0, the master bit in spicr1 resets. the modf interrupt is re?cted in the status register modf ?g. clearing the ?g will also clear the interrupt. this interrupt will stay active while the modf ?g is set. modf has an automatic clearing process which is described in section 15.3.2.4, ?pi status register (spisr) .
serial peripheral interface (s12spiv5) mc9s12xhy-family reference manual, rev. 1.01 518 freescale semiconductor 15.4.7.5.2 spif spif occurs when new data has been received and copied to the spi data register. after spif is set, it does not clear until it is serviced. spif has an automatic clearing process, which is described in section 15.3.2.4, ?pi status register (spisr) . 15.4.7.5.3 sptef sptef occurs when the spi data register is ready to accept new data. after sptef is set, it does not clear until it is serviced. sptef has an automatic clearing process, which is described in section 15.3.2.4, ?pi status register (spisr) .
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 519 chapter 16 timer module (tim16b8cv2) block description 16.1 introduction the basic timer consists of a 16-bit, software-programmable counter driven by a enhanced programmable prescaler. table 16-1. revision history revision number revision date sections affected description of changes v02.04 1 jul 2008 16.3.2.12/16-53 5 16.3.2.13/16-53 5 16.3.2.16/16-53 8 16.4.2/16-543 16.4.3/16-543 - revised ?g clearing procedure, whereby ten bit must be set when clearing ?gs. v02.05 9 jul 2009 16.3.2.12/16-53 5 16.3.2.13/16-53 5 16.3.2.15/16-53 7 16.3.2.16/16-53 8 16.3.2.19/16-54 0 16.4.2/16-543 16.4.3/16-543 - revised ?g clearing procedure, whereby ten or paen bit must be set when clearing ?gs. - add fomula to describe prescaler v02.06 26 aug 2009 16.1.2/16-520 16.3.2.15/16-53 7 16.3.2.2/16-526 16.3.2.3/16-527 16.3.2.4/16-528 16.4.3/16-543 - correct typo: tscr ->tscr1 - correct reference: figure 1-25 -> figure 1-31 - add description, ? counter over?w when ttov[7] is set? to be the condition of channel 7 override event. - phrase the description of oc7m to make it more explicit v02.07 04 may 2010 16.3.2.8/16-531 16.3.2.11/16-53 4 16.4.3/16-543 - add table 16-10 - in tcre bit description part,add note - add figure 16-31
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 520 freescale semiconductor this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. pulse widths can vary from microseconds to many seconds. this timer contains 8 complete input capture/output compare channels and one pulse accumulator. the input capture function is used to detect a selected transition edge and record the time. the output compare function is used for generating output signals or for timer software delays. the 16-bit pulse accumulator is used to operate as a simple event counter or a gated time accumulator. the pulse accumulator shares timer channel 7 when in event mode. a full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word. 16.1.1 features the tim16b8cv2 includes these distinctive features: eight input capture/output compare channels. clock prescaling. 16-bit counter. 16-bit pulse accumulator. 16.1.2 modes of operation stop: timer is off because clocks are stopped. freeze: timer counter keep on running, unless tsfrz in tscr1 (0x0006) is set to 1. wait: counters keep on running, unless tswai in tscr1 (0x0006) is set to 1. normal: timer counter keep on running, unless ten in tscr1 (0x0006) is cleared to 0.
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 521 16.1.3 block diagrams figure 16-1. tim16b8cv2 block diagram prescaler 16-bit counter input capture output compare 16-bit pulse accumulator ioc0 ioc2 ioc1 ioc5 ioc3 ioc4 ioc6 ioc7 pa input interrupt pa overflow interrupt timer overflow interrupt timer channel 0 interrupt timer channel 7 interrupt registers bus clock input capture output compare input capture output compare input capture output compare input capture output compare input capture output compare input capture output compare input capture output compare channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 522 freescale semiconductor figure 16-2. 16-bit pulse accumulator block diagram figure 16-3. interrupt flag setting edge detector intermodule bus pt7 m clock divide by 64 clock select clk0 clk1 4:1 mux timclk paclk paclk / 256 paclk / 65536 prescaled clock (pclk) (timer clock) interrupt mux (pamod) pacnt ptn edge detector 16-bit main timer tcn input capture reg. set cnf interrupt
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 523 figure 16-4. channel 7 output compare/pulse accumulator logic 16.2 external signal description the tim16b8cv2 module has a total of eight external pins. 16.2.1 ioc7 ?input capture and output compare channel 7 pin this pin serves as input capture or output compare for channel 7. this can also be con?ured as pulse accumulator input. 16.2.2 ioc6 ?input capture and output compare channel 6 pin this pin serves as input capture or output compare for channel 6. 16.2.3 ioc5 ?input capture and output compare channel 5 pin this pin serves as input capture or output compare for channel 5. 16.2.4 ioc4 ?input capture and output compare channel 4 pin this pin serves as input capture or output compare for channel 4. pin 16.2.5 ioc3 ?input capture and output compare channel 3 pin this pin serves as input capture or output compare for channel 3. 16.2.6 ioc2 ?input capture and output compare channel 2 pin this pin serves as input capture or output compare for channel 2. pulse accumulator pa d ten channel 7 output compare ocpd tios7
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 524 freescale semiconductor 16.2.7 ioc1 ?input capture and output compare channel 1 pin this pin serves as input capture or output compare for channel 1. 16.2.8 ioc0 ?input capture and output compare channel 0 pin this pin serves as input capture or output compare for channel 0. note for the description of interrupts see section 16.6, ?nterrupts . 16.3 memory map and register de?ition this section provides a detailed description of all memory and registers. 16.3.1 module memory map the memory map for the tim16b8cv2 module is given below in figure 16-5 . the address listed for each register is the address offset. the total address for each register is the sum of the base address for the tim16b8cv2 module and the address offset for each register. 16.3.2 register descriptions this section consists of register descriptions in address order. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. register name bit 7 654321 bit 0 0x0000 tios r ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 w 0x0001 cforc r00000000 w foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 0x0002 oc7m r oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 w 0x0003 oc7d r oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 w 0x0004 tcnth r tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 w 0x0005 tcntl r tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 w = unimplemented or reserved figure 16-5. tim16b8cv2 register summary (sheet 1 of 3)
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 525 0x0006 tscr1 r ten tswai tsfrz tffca prnt 000 w 0x0007 ttov r tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 w 0x0008 tctl1 r om7 ol7 om6 ol6 om5 ol5 om4 ol4 w 0x0009 tctl2 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 w 0x000a tctl3 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w 0x000b tctl4 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a w 0x000c tie r c7i c6i c5i c4i c3i c2i c1i c0i w 0x000d tscr2 r toi 000 tcre pr2 pr1 pr0 w 0x000e tflg1 r c7f c6f c5f c4f c3f c2f c1f c0f w 0x000f tflg2 r tof 0000000 w 0x0010?x001f tcxh?cxl r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0020 pactl r0 paen pamod pedge clk1 clk0 paovi pai w 0x0021 paflg r000000 paovf paif w 0x0022 pacnth r pacnt15 pacnt14 pacnt13 pacnt12 pacnt11 pacnt10 pacnt9 pacnt8 w 0x0023 pacntl r pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 w 0x0024?x002b reserved r w register name bit 7 654321 bit 0 = unimplemented or reserved figure 16-5. tim16b8cv2 register summary (sheet 2 of 3)
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 526 freescale semiconductor 16.3.2.1 timer input capture/output compare select (tios) read: anytime write: anytime 16.3.2.2 timer compare force register (cforc) 0x002c ocpd r ocpd7 ocpd6 ocpd5 ocpd4 ocpd3 ocpd2 ocpd1 ocpd0 w 0x002d r 0x002e ptpsr r ptps7 ptps6 ptps5 ptps4 ptps3 ptps2 ptps1 ptps0 w 0x002f reserved r w module base + 0x0000 76543210 r ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 w reset 00000000 figure 16-6. timer input capture/output compare select (tios) table 16-2. tios field descriptions field description 7:0 ios[7:0] input capture or output compare channel con?uration 0 the corresponding channel acts as an input capture. 1 the corresponding channel acts as an output compare. module base + 0x0001 76543210 r00000000 w foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 reset 00000000 figure 16-7. timer compare force register (cforc) register name bit 7 654321 bit 0 = unimplemented or reserved figure 16-5. tim16b8cv2 register summary (sheet 3 of 3)
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 527 read: anytime but will always return 0x0000 (1 state is transient) write: anytime 16.3.2.3 output compare 7 mask register (oc7m) read: anytime write: anytime table 16-3. cforc field descriptions field description 7:0 foc[7:0] force output compare action for channel 7:0 a write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare ??to occur immediately. the action taken is the same as if a successful comparison had just taken place with the tcx register except the interrupt ?g does not get set. note: a channel 7 event, which can be a counter over?w when ttov[7] is set or a successful output compare on channel 7, overrides any channel 6:0 compares. if forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt ?g won? get set. module base + 0x0002 76543210 r oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 w reset 00000000 figure 16-8. output compare 7 mask register (oc7m) table 16-4. oc7m field descriptions field description 7:0 oc7m[7:0] output compare 7 mask ?a channel 7 event, which can be a counter over?w when ttov[7] is set or a successful output compare on channel 7, overrides any channel 6:0 compares. for each oc7m bit that is set, the output compare action re?cts the corresponding oc7d bit. 0 the corresponding oc7dx bit in the output compare 7 data register will not be transferred to the timer port on a channel 7 event, even if the corresponding pin is setup for output compare. 1 the corresponding oc7dx bit in the output compare 7 data register will be transferred to the timer port on a channel 7 event. note: the corresponding channel must also be setup for output compare (iosx = 1 and ocpdx = 0) for data to be transferred from the output compare 7 data register to the timer port.
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 528 freescale semiconductor 16.3.2.4 output compare 7 data register (oc7d) read: anytime write: anytime 16.3.2.5 timer count register (tcnt) the 16-bit main timer is an up counter. a full access for the counter register should take place in one clock cycle. a separate read/write for high byte and low byte will give a different result than accessing them as a word. read: anytime module base + 0x0003 76543210 r oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 w reset 00000000 figure 16-9. output compare 7 data register (oc7d) table 16-5. oc7d field descriptions field description 7:0 oc7d[7:0] output compare 7 data a channel 7 event, which can be a counter over?w when ttov[7] is set or a successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register. module base + 0x0004 15 14 13 12 11 10 9 9 r tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 w reset 00000000 figure 16-10. timer count register high (tcnth) module base + 0x0005 76543210 r tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 w reset 00000000 figure 16-11. timer count register low (tcntl)
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 529 write: has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). the period of the ?st count after a write to the tcnt registers may be a different size because the write is not synchronized with the prescaler clock. 16.3.2.6 timer system control register 1 (tscr1) read: anytime write: anytime module base + 0x0006 76543210 r ten tswai tsfrz tffca prnt 000 w reset 00000000 = unimplemented or reserved figure 16-12. timer system control register 1 (tscr1) table 16-6. tscr1 field descriptions field description 7 ten timer enable 0 disables the main timer, including the counter. can be used for reducing power consumption. 1 allows the timer to function normally. if for any reason the timer is not active, there is no 64 clock for the pulse accumulator because the 64 is generated by the timer prescaler. 6 tswai timer module stops while in wait 0 allows the timer module to continue running during wait. 1 disables the timer module when the mcu is in the wait mode. timer interrupts cannot be used to get the mcu out of wait. tswai also affects pulse accumulator. 5 tsfrz timer stops while in freeze mode 0 allows the timer counter to continue running while in freeze mode. 1 disables the timer counter whenever the mcu is in freeze mode. this is useful for emulation. tsfrz does not stop the pulse accumulator.
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 530 freescale semiconductor 16.3.2.7 timer toggle on over?w register 1 (ttov) read: anytime write: anytime 4 tffca timer fast flag clear all 0 allows the timer ?g clearing to function normally. 1 for tflg1(0x000e), a read from an input capture or a write to the output compare channel (0x0010?x001f) causes the corresponding channel ?g, cnf, to be cleared. for tflg2 (0x000f), any access to the tcnt register (0x0004, 0x0005) clears the tof ?g. any access to the pacnt registers (0x0022, 0x0023) clears the paovf and paif ?gs in the paflg register (0x0021). this has the advantage of eliminating software overhead in a separate clear sequence. extra care is required to avoid accidental ?g clearing due to unintended accesses. 3 prnt precision timer 0 enables legacy timer. pr0, pr1, and pr2 bits of the tscr2 register are used for timer counter prescaler selection. 1 enables precision timer. all bits of the ptpsr register are used for precision timer prescaler selection, and all bits. this bit is writable only once out of reset. module base + 0x0007 76543210 r tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 w reset 00000000 figure 16-13. timer toggle on over?w register 1 (ttov) table 16-7. ttov field descriptions field description 7:0 tov[7:0] toggle on over?w bits tovx toggles output compare pin on over?w. this feature only takes effect when in output compare mode. when set, it takes precedence over forced output compare but not channel 7 override events. 0 toggle output compare pin on over?w feature disabled. 1 toggle output compare pin on over?w feature enabled. table 16-6. tscr1 field descriptions (continued) field description
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 531 16.3.2.8 timer control register 1/timer control register 2 (tctl1/tctl2) read: anytime write: anytime module base + 0x0008 76543210 r om7 ol7 om6 ol6 om5 ol5 om4 ol4 w reset 00000000 figure 16-14. timer control register 1 (tctl1) module base + 0x0009 76543210 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 w reset 00000000 figure 16-15. timer control register 2 (tctl2) table 16-8. tctl1/tctl2 field descriptions field description 7:0 omx output mode these eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful ocx compare. when either omx or olx is 1, the pin associated with ocx becomes an output tied to ocx. note: to enable output action by omx bits on timer port, the corresponding bit in oc7m should be cleared. for an output line to be driven by an ocx the ocpdx must be cleared. 7:0 olx output level these eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful ocx compare. when either omx or olx is 1, the pin associated with ocx becomes an output tied to ocx. note: to enable output action by olx bits on timer port, the corresponding bit in oc7m should be cleared. for an output line to be driven by an ocx the ocpdx must be cleared. table 16-9. compare result output action omx olx action 0 0 no output compare action on the timer output signal 0 1 toggle ocx output line 1 0 clear ocx output line to zero 1 1 set ocx output line to one
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 532 freescale semiconductor to operate the 16-bit pulse accumulator independently of input capture or output compare 7 and 0 respectively the user must set the corresponding bits iosx = 1, omx = 0 and olx = 0. oc7m7 in the oc7m register must also be cleared. to enable output action using the om7 and ol7 bits on the timer port,the corresponding bit oc7m7 in the oc7m register must also be cleared. the settings for these bits can be seen in table 16-10 table 16-10. the oc7 and ocx event priority note: in table 16-10 , the ios7 and iosx should be set to 1 iosx is the register tios bit x, oc7mx is the register oc7m bit x, tcx is timer input capture/output compare register, iocx is channel x, omx/olx is the register tctl1/tctl2, oc7dx is the register oc7d bit x. iocx = oc7dx+ omx/olx, means that both oc7 event and ocx event will change channel x value. 16.3.2.9 timer control register 3/timer control register 4 (tctl3 and tctl4) oc7m7=0 oc7m7=1 oc7mx=1 oc7mx=0 oc7mx=1 oc7mx=0 tc7=tcx tc7>tcx tc7=tcx tc7>tcx tc7=tcx tc7>tcx tc7=tcx tc7>tcx iocx=oc7dx ioc7=om7/o l7 iocx=oc7dx +omx/olx ioc7=om7/o l7 iocx=omx/olx ioc7=om7/ol7 iocx=oc7dx ioc7=oc7d7 iocx=oc7dx +omx/olx ioc7=oc7d7 iocx=omx/olx ioc7=oc7d7 module base + 0x000a 76543210 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w reset 00000000 figure 16-16. timer control register 3 (tctl3) module base + 0x000b 76543210 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a w reset 00000000 figure 16-17. timer control register 4 (tctl4)
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 533 read: anytime write: anytime. 16.3.2.10 timer interrupt enable register (tie) read: anytime write: anytime. table 16-11. tctl3/tctl4 field descriptions field description 7:0 edgnb edgna input capture edge control ?these eight pairs of control bits con?ure the input capture edge detector circuits. table 16-12. edge detector circuit con?uration edgnb edgna con?uration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge (rising or falling) module base + 0x000c 76543210 r c7i c6i c5i c4i c3i c2i c1i c0i w reset 00000000 figure 16-18. timer interrupt enable register (tie) table 16-13. tie field descriptions field description 7:0 c7i:c0i input capture/output compare ??interrupt enable the bits in tie correspond bit-for-bit with the bits in the tflg1 status register. if cleared, the corresponding ?g is disabled from causing a hardware interrupt. if set, the corresponding ?g is enabled to cause a interrupt.
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 534 freescale semiconductor 16.3.2.11 timer system control register 2 (tscr2) read: anytime write: anytime. module base + 0x000d 76543210 r toi 000 tcre pr2 pr1 pr0 w reset 00000000 = unimplemented or reserved figure 16-19. timer system control register 2 (tscr2) table 16-14. tscr2 field descriptions field description 7 toi timer over?w interrupt enable 0 interrupt inhibited. 1 hardware interrupt requested when tof ?g set. 3 tcre timer counter reset enable this bit allows the timer counter to be reset by a successful output compare 7 event. this mode of operation is similar to an up-counting modulus counter. 0 counter reset inhibited and counter free runs. 1 counter reset by a successful output compare 7. note: if tc7 = 0x0000 and tcre = 1, tcnt will stay at 0x0000 continuously. if tc7 = 0xffff and tcre = 1, tof will never be set when tcnt is reset from 0xffff to 0x0000. note: tcre=1 and tc7!=0, the tcnt cycle period will be tc7 x "prescaler counter width" + "1 bus clock", for a more detail explanation please refer to section 16.4.3, ?utput compare 2 pr[2:0] timer prescaler select ?these three bits select the frequency of the timer prescaler clock derived from the bus clock as shown in table 16-15 . table 16-15. timer clock selection pr2 pr1 pr0 timer clock 0 0 0 bus clock / 1 0 0 1 bus clock / 2 0 1 0 bus clock / 4 0 1 1 bus clock / 8 1 0 0 bus clock / 16 1 0 1 bus clock / 32 1 1 0 bus clock / 64 1 1 1 bus clock / 128
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 535 note the newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. 16.3.2.12 main timer interrupt flag 1 (tflg1) read: anytime write: used in the clearing mechanism (set bits cause corresponding bits to be cleared). writing a zero will not affect current status of the bit. 16.3.2.13 main timer interrupt flag 2 (tflg2) tflg2 indicates when interrupt conditions have occurred. to clear a bit in the ?g register, write the bit to one while ten bit of tscr1 or paen bit of pactl is set to one. read: anytime write: used in clearing mechanism (set bits cause corresponding bits to be cleared). any access to tcnt will clear tflg2 register if the tffca bit in tscr register is set. module base + 0x000e 76543210 r c7f c6f c5f c4f c3f c2f c1f c0f w reset 00000000 figure 16-20. main timer interrupt flag 1 (tflg1) table 16-16. trlg1 field descriptions field description 7:0 c[7:0]f input capture/output compare channel ??flag ?these flags are set when an input capture or output compare event occurs. clearing requires writing a one to the corresponding ?g bit while ten or paen is set to one. when tffca bit in tscr register is set, a read from an input capture or a write into an output compare channel (0x0010?x001f) will cause the corresponding channel ?g cxf to be cleared. module base + 0x000f 76543210 r tof 0000000 w reset 00000000 unimplemented or reserved figure 16-21. main timer interrupt flag 2 (tflg2)
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 536 freescale semiconductor 16.3.2.14 timer input capture/output compare registers high and low 0? (tcxh and tcxl) depending on the tios bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a de?ed transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. read: anytime write: anytime for output compare function.writes to these registers have no meaning or effect during input capture. all timer input capture/output compare registers are reset to 0x0000. note read/write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. table 16-17. trlg2 field descriptions field description 7 tof timer over?w flag set when 16-bit free-running timer over?ws from 0xffff to 0x0000. clearing this bit requires writing a one to bit 7 of tflg2 register while the ten bit of tscr1 or paen bit of pactl is set to one (see also tcre control bit explanation.) module base + 0x0010 = tc0h 0x0012 = tc1h 0x0014 = tc2h 0x0016 = tc3h 0x0018 = tc4h 0x001a = tc5h 0x001c = tc6h 0x001e = tc7h 15 14 13 12 11 10 9 0 r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w reset 00000000 figure 16-22. timer input capture/output compare register x high (tcxh) module base + 0x0011 = tc0l 0x0013 = tc1l 0x0015 = tc2l 0x0017 = tc3l 0x0019 = tc4l 0x001b = tc5l 0x001d = tc6l 0x001f = tc7l 76543210 r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reset 00000000 figure 16-23. timer input capture/output compare register x low (tcxl)
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 537 16.3.2.15 16-bit pulse accumulator control register (pactl) when paen is set, the pact is enabled.the pact shares the input pin with ioc7. read: any time write: any time module base + 0x0020 76543210 r0 paen pamod pedge clk1 clk0 paovi pai w reset 00000000 unimplemented or reserved figure 16-24. 16-bit pulse accumulator control register (pactl) table 16-18. pactl field descriptions field description 6 paen pulse accumulator system enable ?paen is independent from ten. with timer disabled, the pulse accumulator can function unless pulse accumulator is disabled. 0 16-bit pulse accumulator system disabled. 1 pulse accumulator system enabled. 5 pamod pulse accumulator mode ?this bit is active only when the pulse accumulator is enabled (paen = 1). see table 16-19 . 0 event counter mode. 1 gated time accumulation mode. 4 pedge pulse accumulator edge control this bit is active only when the pulse accumulator is enabled (paen = 1). for pamod bit = 0 (event counter mode). see table 16-19 . 0 falling edges on ioc7 pin cause the count to be incremented. 1 rising edges on ioc7 pin cause the count to be incremented. for pamod bit = 1 (gated time accumulation mode). 0 ioc7 input pin high enables m (bus clock) divided by 64 clock to pulse accumulator and the trailing falling edge on ioc7 sets the paif ?g. 1 ioc7 input pin low enables m (bus clock) divided by 64 clock to pulse accumulator and the trailing rising edge on ioc7 sets the paif ?g. 3:2 clk[1:0] clock select bits refer to table 16-20 . 1 paov i pulse accumulator over?w interrupt enable 0 interrupt inhibited. 1 interrupt requested if paovf is set. 0 pa i pulse accumulator input interrupt enable 0 interrupt inhibited. 1 interrupt requested if paif is set.
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 538 freescale semiconductor note if the timer is not active (ten = 0 in tscr), there is no divide-by-64 because the 64 clock is generated by the timer prescaler. for the description of paclk please refer figure 16-30 . if the pulse accumulator is disabled (paen = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. the change from one selected clock to the other happens immediately after these bits are written. 16.3.2.16 pulse accumulator flag register (paflg) read: anytime write: anytime when the tffca bit in the tscr register is set, any access to the pacnt register will clear all the ?gs in the paflg register. timer module or pulse accumulator must stay enabled (ten=1 or paen=1) while clearing these bits. table 16-19. pin action pamod pedge pin action 0 0 falling edge 0 1 rising edge 1 0 div. by 64 clock enabled with pin high level 1 1 div. by 64 clock enabled with pin low level table 16-20. timer clock selection clk1 clk0 timer clock 0 0 use timer prescaler clock as timer counter clock 0 1 use paclk as input to timer counter clock 1 0 use paclk/256 as timer counter clock frequency 1 1 use paclk/65536 as timer counter clock frequency module base + 0x0021 76543210 r000000 paovf paif w reset 00000000 unimplemented or reserved figure 16-25. pulse accumulator flag register (paflg)
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 539 16.3.2.17 pulse accumulators count registers (pacnt) read: anytime write: anytime these registers contain the number of active input edges on its input pin since the last reset. when pacnt over?ws from 0xffff to 0x0000, the interrupt ?g paovf in paflg (0x0021) is set. full count register access should take place in one clock cycle. a separate read/write for high byte and low byte will give a different result than accessing them as a word. note reading the pulse accumulator counter registers immediately after an active edge on the pulse accumulator input pin may miss the last count because the input has to be synchronized with the bus clock ?st. table 16-21. paflg field descriptions field description 1 paov f pulse accumulator over?w flag set when the 16-bit pulse accumulator over?ws from 0xffff to 0x0000. clearing this bit requires writing a one to this bit in the paflg register while ten bit of tscr1 or paen bit of pactl register is set to one. 0 paif pulse accumulator input edge flag set when the selected edge is detected at the ioc7 input pin.in event mode the event edge triggers paif and in gated time accumulation mode the trailing edge of the gate signal at the ioc7 input pin triggers paif. clearing this bit requires writing a one to this bit in the paflg register while ten bit of tscr1 or paen bit of pactl register is set to one. any access to the pacnt register will clear all the ?gs in this register when tffca bit in register tscr(0x0006) is set. module base + 0x0022 15 14 13 12 11 10 9 0 r pacnt15 pacnt14 pacnt13 pacnt12 pacnt11 pacnt10 pacnt9 pacnt8 w reset 00000000 figure 16-26. pulse accumulator count register high (pacnth) module base + 0x0023 76543210 r pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 w reset 00000000 figure 16-27. pulse accumulator count register low (pacntl)
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 540 freescale semiconductor 16.3.2.18 output compare pin disconnect register(ocpd) read: anytime write: anytime all bits reset to zero. 16.3.2.19 precision timer prescaler select register (ptpsr) read: anytime write: anytime all bits reset to zero. module base + 0x002c 76543210 r ocpd7 ocpd6 ocpd5 ocpd4 ocpd3 ocpd2 ocpd1 ocpd0 w reset 00000000 figure 16-28. ouput compare pin disconnect register (ocpd) table 16-22. ocpd field description field description ocpd[7:0} output compare pin disconnect bits 0 enables the timer channel port. ouptut compare action will occur on the channel pin. these bits do not affect the input capture or pulse accumulator functions 1 disables the timer channel port. output compare action will not occur on the channel pin, but the output compare ?g still become set . module base + 0x002e 76543210 r ptps7 ptps6 ptps5 ptps4 ptps3 ptps2 ptps1 ptps0 w reset 00000000 figure 16-29. precision timer prescaler select register (ptpsr)
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 541 the prescaler can be calculated as follows depending on logical value of the ptps[7:0] and prnt bit: prnt = 1 : prescaler = ptps[7:0] + 1 table 16-24. precision timer prescaler selection examples when prnt = 1 16.4 functional description this section provides a complete functional description of the timer tim16b8cv2 block. please refer to the detailed timer block diagram in figure 16-30 as necessary. table 16-23. ptpsr field descriptions field description 7:0 ptps[7:0] precision timer prescaler select bits these eight bits specify the division rate of the main timer prescaler. these are effective only when the prnt bit of tscr1 is set to 1. table 16-24 shows some selection examples in this case. the newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. ptps7 ptps6 ptps5 ptps4 ptps3 ptps2 ptps1 ptps0 prescale factor 00000000 1 00000001 2 00000010 3 00000011 4 00000100 5 00000101 6 00000110 7 00000111 8 00001111 16 00011111 32 00111111 64 01111111 128 11111111 256
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 542 freescale semiconductor figure 16-30. detailed timer block diagram 16.4.1 prescaler the prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. the prescaler select bits, pr[2:0], select the prescaler divisor. pr[2:0] are in timer system control register 2 (tscr2). prescaler channel 0 ioc0 pin 16-bit counter logic pr[2:1:0] divide-by-64 tc0 edge detect pacnt(hi):pacnt(lo) paovf pedge paovi ten pae 16-bit comparator tcnt(hi):tcnt(lo) channel 1 tc1 16-bit comparator 16-bit counter interrupt logic tof toi c0f c1f edge detect ioc1 pin logic edge detect cxf channel7 tc7 16-bit comparator c7f ioc7 pin logic edge detect om:ol0 tov0 om:ol1 tov1 om:ol7 tov7 edg1a edg1b edg7a edg7b edg0b tcre paif clear counter paif pai interrupt logic cxi interrupt request paovf ch. 7 compare ch.7 capture ch. 1 capture mux clk[1:0] paclk paclk/256 paclk/65536 ioc1 pin ioc0 pin ioc7 pin paclk paclk/256 paclk/65536 te ch. 1 compare ch. 0compare ch. 0 capture pa input channel2 edg0a channel 7 output compare ioc0 ioc1 ioc7 bus clock bus clock paovf paovi tof c0f c1f c7f
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 543 the prescaler divides the bus clock by a prescalar value. prescaler select bits pr[2:0] of in timer system control register 2 (tscr2) are set to de?e a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the prnt bit in tscr1 is disabled. by enabling the prnt bit of the tscr1 register, the performance of the timer can be enhanced. in this case, it is possible to set additional prescaler settings for the main timer counter in the present timer by using ptpsr[7:0] bits of ptpsr register. 16.4.2 input capture clearing the i/o (input/output) select bit, iosx, con?ures channel x as an input capture channel. the input capture function captures the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, tcx. the minimum pulse width for the input capture input is greater than two bus clocks. an input capture on channel x sets the cxf ?g. the cxi bit enables the cxf ?g to generate interrupt requests. timer module or pulse accumulator must stay enabled (ten bit of tscr1 or paen bit of pactl regsiter must be set to one) while clearing cxf (writing one to cxf). 16.4.3 output compare setting the i/o select bit, iosx, con?ures channel x as an output compare channel. the output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. when the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin if the corresponding ocpdx bit is set to zero. an output compare on channel x sets the cxf ?g. the cxi bit enables the cxf ?g to generate interrupt requests. timer module or pulse accumulator must stay enabled (ten bit of tscr1 or paen bit of pactl regsiter must be set to one) while clearing cxf (writing one to cxf). the output mode and level bits, omx and olx, select set, clear, toggle on output compare. clearing both omx and olx results in no output compare action on the output compare channel pin. setting a force output compare bit, focx, causes an output compare on channel x. a forced output compare does not set the channel ?g. a channel 7 event, which can be a counter over?w when ttov[7] is set or a successful output compare on channel 7, overrides output compares on all other output compare channels. the output compare 7 mask register masks the bits in the output compare 7 data register. the timer counter reset enable bit, tcre, enables channel 7 output compares to reset the timer counter. a channel 7 output compare can reset the timer counter even if the ioc7 pin is being used as the pulse accumulator input. writing to the timer port bit of an output compare pin does not affect the pin state. the value written is stored in an internal latch. when the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. when tcre is set and tc7 is not equal to 0, then tcnt will cycle from 0 to tc7. when tcnt reaches tc7 value, it will last only one bus cycle then reset to 0.
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 544 freescale semiconductor note: in figure 16-31 ,if pr[2:0] is equal to 0, one prescaler counter equal to one bus clock figure 16-31. the tcnt cycle diagram under tcre=1 condition 16.4.3.1 oc channel initialization internal register whose output drives ocx can be programmed before timer drives ocx. the desired state can be programmed to this internal register by writing a one to cforcx bit with tiosx, ocpdx and ten bits set to one. setting ocpdx to zero allows interal register to drive the programmed state to ocx. this allows a glitch free switch over of port from general purpose i/o to timer output once the ocpdx bit is set to zero. 16.4.4 pulse accumulator the pulse accumulator (pacnt) is a 16-bit counter that can operate in two modes: event counter mode ?counting edges of selected polarity on the pulse accumulator input pin, pai. gated time accumulation mode counting pulses from a divide-by-64 clock. the pamod bit selects the mode of operation. the minimum pulse width for the pai input is greater than two bus clocks. 16.4.5 event counter mode clearing the pamod bit con?ures the pacnt for event counter operation. an active edge on the ioc7 pin increments the pulse accumulator counter. the pedge bit selects falling edges or rising edges to increment the count. note the pacnt input and timer channel 7 use the same pin ioc7. to use the ioc7, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, om7 and ol7. also clear the channel 7 output compare 7 mask bit, oc7m7. the pulse accumulator counter register re?ct the number of active input edges on the pacnt input pin since the last reset. the paovf bit is set when the accumulator rolls over from 0xffff to 0x0000. the pulse accumulator over?w interrupt enable bit, paovi, enables the paovf ?g to generate interrupt requests. tc7 0 1 ----- tc7-1 tc7 0 tc7 event tc7 event prescaler counter 1 bus clock
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual rev. 1.01 freescale semiconductor 545 note the pulse accumulator counter can operate in event counter mode even when the timer enable bit, ten, is clear. 16.4.6 gated time accumulation mode setting the pamod bit con?ures the pulse accumulator for gated time accumulation operation. an active level on the pacnt input pin enables a divided-by-64 clock to drive the pulse accumulator. the pedge bit selects low levels or high levels to enable the divided-by-64 clock. the trailing edge of the active level at the ioc7 pin sets the paif. the pai bit enables the paif ?g to generate interrupt requests. the pulse accumulator counter register re?ct the number of pulses from the divided-by-64 clock since the last reset. note the timer prescaler generates the divided-by-64 clock. if the timer is not active, there is no divided-by-64 clock. 16.5 resets the reset state of each individual bit is listed within section 16.3, ?emory map and register de?ition which details the registers and their bit ?lds. 16.6 interrupts this section describes interrupts originated by the tim16b8cv2 block. table 16-25 lists the interrupts generated by the tim16b8cv2 to communicate with the mcu. the tim16b8cv2 uses a total of 11 interrupt vectors. the interrupt vector offsets and interrupt numbers are chip dependent. table 16-25. tim16b8cv1 interrupts interrupt offset 1 1 chip dependent. vector 1 priority 1 source description c[7:0]f timer channel 7? active high timer channel interrupts 7? paovi pulse accumulator input active high pulse accumulator input interrupt paovf pulse accumulator over?w pulse accumulator over?w interrupt tof timer over?w timer over?w interrupt
timer module (tim16b8cv2) block description mc9s12xhy-family reference manual, rev. 1.01 546 freescale semiconductor 16.6.1 channel [7:0] interrupt (c[7:0]f) this active high outputs will be asserted by the module to request a timer channel 7 ?0 interrupt to be serviced by the system controller. 16.6.2 pulse accumulator input interrupt (paovi) this active high output will be asserted by the module to request a timer pulse accumulator input interrupt to be serviced by the system controller. 16.6.3 pulse accumulator over?w interrupt (paovf) this active high output will be asserted by the module to request a timer pulse accumulator over?w interrupt to be serviced by the system controller. 16.6.4 timer over?w interrupt (tof) this active high output will be asserted by the module to request a timer over?w interrupt to be serviced by the system controller.
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 547 chapter 17 liquid crystal display (lcd40f4bv2) block description revision history 17.1 introduction the lcd40f4bv2 driver module has 40 frontplane drivers and 4 backplane drivers so that a maximum of 160 lcd segments are controllable. each segment is controlled by a corresponding bit in the lcd ram. four multiplex modes (1/1, 1/2, 1/3, 1/4 duty), and three bias (1/1, 1/2, 1/3) methods are available. the v 0 voltage is the lowest level of the output waveform and v 3 becomes the highest level. all frontplane and backplane pins can be multiplexed with other port functions. the lcd40f4bv2 driver system consists of five major sub-modules: timing and control ?consists of registers and control logic for frame clock generation, bias voltage level select, frame duty select, backplane select, and frontplane select/enable to produce the required frame frequency and voltage waveforms. lcd ram contains the data to be displayed on the lcd. data can be read from or written to the display ram at any time. frontplane drivers ?consists of 40 frontplane drivers. backplane drivers ?consists of 4 backplane drivers. voltage generator ?based on voltage applied to vlcd, it generates the voltage levels for the timing and control logic to produce the frontplane and backplane waveforms. table 17-1. lcd40f4bv2 revision history version number revision date effective date author description of changes 01.00 26-jul-00 initial lcd module spec 01.08 27-mar-08 new specification for 9s12hy family based on 9s12h family specification 01.09 25-apr-08 update for 9s12hy defining last registers as unimplemented 02.01 29-jul-09 add pseudo stop feature
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 548 freescale semiconductor 17.1.1 features the lcd40f4bv2 includes these distinctive features: supports ve lcd operation modes 40 frontplane drivers 4 backplane drivers each frontplane has an enable bit respectively programmable frame clock generator programmable bias voltage level selector on-chip generation of 4 different output voltage levels 17.1.2 modes of operation the lcd40f4bv2 module supports ve operation modes with different numbers of backplanes and different biasing levels. during wait mode the lcd operation can be suspended under software control. depending on the state of internal bits, the lcd can operate normally or the lcd clock generation can be turned off and the lcd40f4bv2 module enters a power conservation state. this is a high level description only, detailed descriptions of operating modes are contained in section 17.4.2, ?peration in wait mode , and section 17.4.3, ?peration in stop mode . 17.1.3 block diagram figure 17-1 is a block diagram of the lcd40f4bv2 module.
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 549 figure 17-1. lcd40f4bv2 block diagram lcd ram 20 bytes timing and control logic frontplane drivers voltage generator backplane drivers internal address/data/clocks v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 fp[39:0] vlcd bp[3:0] prescaler ircclk lcd clock
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 550 freescale semiconductor 17.2 external signal description the lcd40f4bv2 module has a total of 45 external pins. 17.2.1 bp[3:0] ?analog backplane pins this output signal vector represents the analog backplane waveforms of the lcd40f4bv2 module and is connected directly to the corresponding pads. 17.2.2 fp[39:0] ?analog frontplane pins this output signal vector represents the analog frontplane waveforms of the lcd40f4bv2 module and is connected directly to the corresponding pads. 17.2.3 vlcd ?lcd supply voltage pin positive supply voltage for the lcd waveform generation. 17.3 memory map and register de?ition this section provides a detailed description of all memory and registers. 17.3.1 module memory map the memory map for the lcd40f4bv2 module is given in table 17-3 . the address listed for each register is the address offset. the total address for each register is the sum of the base address for the lcd40f4bv2 module and the address offset for each register. table 17-2. signal properties name port function reset state 4 backplane waveforms bp[3:0] backplane waveform signals that connect directly to the pads high impedance 40 frontplane waveforms fp[39:0] frontplane waveform signals that connect directly to the pads high impedance lcd voltage vlcd lcd supply voltage
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 551 table 17-3. lcd40f4bv2 memory map address offset use access 0x0000 lcd control register 0 (lcdcr0) read/write 0x0001 lcd control register 1 (lcdcr1) read/write 0x0002 lcd frontplane enable register 0 (fpenr0) read/write 0x0003 lcd frontplane enable register 1 (fpenr1) read/write 0x0004 lcd frontplane enable register 2 (fpenr2) read/write 0x0005 lcd frontplane enable register 3 (fpenr3) read/write 0x0006 lcd frontplane enable register 4 (fpenr4) read/write 0x0007 unimplemented 0x0008 lcdram (location 0) read/write 0x0009 lcdram (location 1) read/write 0x000a lcdram (location 2) read/write 0x000b lcdram (location 3) read/write 0x000c lcdram (location 4) read/write 0x000d lcdram (location 5) read/write 0x000e lcdram (location 6) read/write 0x000f lcdram (location 7) read/write 0x0010 lcdram (location 8) read/write 0x0011 lcdram (location 9) read/write 0x0012 lcdram (location 10) read/write 0x0013 lcdram (location 11) read/write 0x0014 lcdram (location 12) read/write 0x0015 lcdram (location 13) read/write 0x0016 lcdram (location 14) read/write 0x0017 lcdram (location 15) read/write 0x0018 lcdram (location 16) read/write 0x0019 lcdram (location 17) read/write 0x001a lcdram (location 18) read/write 0x001b lcdram (location 19) read/write 0x001c- 0x001f unimplemented
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 552 freescale semiconductor 17.3.2 register descriptions this section consists of register descriptions. each description includes a standard register diagram. details of register bit and field function follow the register diagrams, in bit order. 17.3.2.1 lcd control register 0 (lcdcr0) read: anytime write: lcden anytime. to avoid segment flicker the clock prescaler bits, the bias select bit and the duty select bits must not be changed when the lcd is enabled. module base + 0x0000 76543210 r lcden 0 lclk2 lclk1 lclk0 bias duty1 duty0 w reset 0 0 0 00000 = unimplemented or reserved figure 17-2. lcd control register 0 (lcdcr0) table 17-4. lcdcr0 field descriptions field description 7 lcden lcd40f4bv2 driver system enable ?the lcden bit starts the lcd waveform generator. 0 all frontplane and backplane pins are disabled. in addition, the lcd40f4bv2 system is disabled and all lcd waveform generation clocks are stopped. 1 lcd driver system is enabled. all fp[39:0] pins with fp[39:0]en set, will output an lcd driver waveform the bp[3:0] pins will output an lcd40f4bv2 driver waveform based on the settings of duty0 and duty1. 5:3 lclk[2:0] lcd clock prescaler the lcd clock prescaler bits determine the ircclk divider value to produce the lcd clock frequency. for detailed description of the correlation between lcd clock prescaler bits and the divider value please refer to table 17-8 . 2 bias bias voltage level select ?this bit selects the bias voltage levels during various lcd operating modes, as shown in table 17-9 . 1:0 duty[1:0] lcd duty select ?the duty1 and duty0 bits select the duty (multiplex mode) of the lcd40f4bv2 driver system, as shown in table 17-9 .
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 553 17.3.2.2 lcd control register 1 (lcdcr1) read: anytime write: anytime module base + 0x0001 76543210 r 0 0 0 0 0 0 lcdswai lcdrpstp w reset 0 0 0 00000 unimplemented or reserved figure 17-3. lcd control register 1 (lcdcr1) table 17-5. lcdcr1 field descriptions field description 1 lcdswai lcd stop in wait mode ?this bit controls the lcd operation while in wait mode. 0 lcd operates normally in wait mode. 1 stop lcd40f4bv2 driver system when in wait mode. 0 lcdrpstp lcd run in pseudo stop mode this bit controls the lcd operation while in pseudo stop mode. 0 stop lcd32f4b driver system when in pseudo stop mode. 1 lcd operates normally in pseudo stop mode.
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 554 freescale semiconductor 17.3.2.3 lcd frontplane enable register 0? (fpenr0?penr4) these bits enable the frontplane output waveform on the corresponding frontplane pin when lcden = 1. read: anytime write: anytime module base + 0x0002 76543210 r fp7en fp6en fp5en fp4en fp3en fp2en fp1en fp0en w reset 0 0 0 00000 figure 17-4. lcd frontplane enable register 0 (fpenr0) module base + 0x0003 76543210 r fp15en fp14en fp13en fp12en fp11en fp10en fp9en fp8en w reset 0 0 0 00000 figure 17-5. lcd frontplane enable register 1 (fpenr1) module base + 0x0004 76543210 r fp23en fp22en fp21en fp20en fp19en fp18en fp17en fp16en w reset 0 0 0 00000 figure 17-6. lcd frontplane enable register 2 (fpenr2) module base + 0x0005 76543210 r fp31en fp30en fp29en fp28en fp27en fp26en fp25en fp24en w reset 0 0 0 00000 figure 17-7. lcd frontplane enable register 3 (fpenr3) module base + 0x0005 76543210 r fp39en fp38en fp37en fp36en fp35en fp34en fp33en fp32en w reset 0 0 0 00000 figure 17-8. lcd frontplane enable register 4 (fpenr4)
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 555 17.3.2.4 lcd ram (lcdram) the lcd ram consists of 20 bytes. after reset the lcd ram contents will be indeterminate (i), as indicated by figure 17-9 . table 17-6. fpenr0?penr4 field descriptions field description 39:0 fp[39:0]en frontplane output enable ?the fp[39:0]en bit enables the frontplane driver outputs. if lcden = 0, these bits have no effect on the state of the i/o pins. it is recommended to set fp[39:0]en bits before lcden is set. 0 frontplane driver output disabled on fp[39:0]. 1 frontplane driver output enabled on fp[39:0]. 76543210 0x0008 r fp1bp3 fp1bp2 fp1bp1 fp1bp0 fp0bp3 fp0bp2 fp0bp1 fp0bp0 lcdram w reset i i i i i i i i 0x0009 r fp3bp3 fp3bp2 fp3bp1 fp3bp0 fp2bp3 fp2bp2 fp2bp1 fp2bp0 lcdram w reset i i i i i i i i 0x000a r fp5bp3 fp5bp2 fp5bp1 fp5bp0 fp4bp3 fp4bp2 fp4bp1 fp4bp0 lcdram w reset i i i i i i i i 0x000b r fp7bp3 fp7bp2 fp7bp1 fp7bp0 fp6bp3 fp6bp2 fp6bp1 fp6bp0 lcdram w reset i i i i i i i i 0x000c r fp9bp3 fp9bp2 fp9bp1 fp9bp0 fp8bp3 fp8bp2 fp8bp1 fp8bp0 lcdram w reset i i i i i i i i 0x000d r fp11bp3 fp11bp2 fp11bp1 fp11bp0 fp10bp3 fp10bp2 fp10bp1 fp10bp0 lcdram w reset i i i i i i i i 0x000e r fp13bp3 fp13bp2 fp13bp1 fp13bp0 fp12bp3 fp12bp2 fp12bp1 fp12bp0 lcdram w reset i i i i i i i i 0x000f r fp15bp3 fp15bp2 fp15bp1 fp15bp0 fp14bp3 fp14bp2 fp14bp1 fp14bp0 lcdram w reset i i i i i i i i 0x0010 r fp17bp3 fp17bp2 fp17bp1 fp17bp0 fp16bp3 fp16bp2 fp16bp1 fp16bp0 lcdram w reset i i i i i i i i i = value is indeterminate figure 17-9. lcd ram (lcdram)
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 556 freescale semiconductor read: anytime write: anytime 0x0011 r fp19bp3 fp19bp2 fp19bp1 fp19bp0 fp18bp3 fp18bp2 fp18bp1 fp18bp0 lcdram w reset i i i i i i i i 0x0012 r fp21bp3 fp21bp2 fp21bp1 fp21bp0 fp20bp3 fp20bp2 fp20bp1 fp20bp0 lcdram w reset i i i i i i i i 0x0013 r fp23bp3 fp23bp2 fp23bp1 fp23bp0 fp22bp3 fp22bp2 fp22bp1 fp22bp0 lcdram w reset i i i i i i i i 0x0014 r fp25bp3 fp25bp2 fp25bp1 fp25bp0 fp24bp3 fp24bp2 fp24bp1 fp24bp0 lcdram w reset i i i i i i i i 0x0015 r fp27bp3 fp27bp2 fp27bp1 fp27bp0 fp26bp3 fp26bp2 fp26bp1 fp26bp0 lcdram w reset i i i i i i i i 0x0016 r fp29bp3 fp29bp2 fp29bp1 fp29bp0 fp28bp3 fp28bp2 fp28bp1 fp28bp0 lcdram w reset i i i i i i i i 0x0017 r fp31bp3 fp31bp2 fp31bp1 fp31bp0 fp30bp3 fp30bp2 fp30bp1 fp30bp0 lcdram w reset i i i i i i i i 0x0018 r fp33bp3 fp33bp2 fp33bp1 fp33bp0 fp32bp3 fp32bp2 fp32bp1 fp32bp0 lcdram w reset i i i i i i i i 0x0019 r fp35bp3 fp35bp2 fp35bp1 fp35bp0 fp34bp3 fp34bp2 fp34bp1 fp34bp0 lcdram w reset i i i i i i i i 0x001a r fp37bp3 fp37bp2 fp37bp1 fp37bp0 fp36bp3 fp36bp2 fp36bp1 fp36bp0 lcdram w reset i i i i i i i i 0x001b r fp39bp3 fp39bp2 fp39bp1 fp39bp0 fp38bp3 fp38bp2 fp38bp1 fp38bp0 lcdram w reset i i i i i i i i i = value is indeterminate figure 17-9. lcd ram (lcdram) (continued)
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 557 17.4 functional description this section provides a complete functional description of the lcd40f4bv2 block, detailing the operation of the design from the end user perspective in a number of subsections. 17.4.1 lcd driver description 17.4.1.1 frontplane, backplane, and lcd system during reset during a reset the following conditions exist: the lcd40f4bv2 system is configured in the default mode, 1/4 duty and 1/3 bias, that means all backplanes are used. all frontplane enable bits, fp[39:0]en are cleared and the on/off control for the display, the lcden bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high impedance state. the mcu pin state during reset is defined by the port integration module (pim). 17.4.1.2 lcd clock and frame frequency the frequency of the source clock (ircclk) and divider determine the lcd clock frequency. the divider is set by the lcd clock prescaler bits, lclk[2:0], in the lcd control register 0 (lcdcr0). table 17-8 shows the lcd clock and frame frequency for some multiplexed mode at ircclk = 16 mhz, 8 mhz, 4 mhz, 2 mhz, 1 mhz, and 0.5 mhz. table 17-7. lcd ram field descriptions field description 39:0 3:0 fp[39:0] bp[3:0] lcd segment on the fp[39:0]bp[3:0] bit displays (turns on) the lcd segment connected between fp[39:0] and bp[3:0]. 0 lcd segment off 1 lcd segment on table 17-8. lcd clock and frame frequency source clock frequency in mhz lcd clock prescaler divider lcd clock frequency [hz] frame frequency [hz] lclk2 lclk1 lclk0 1/1 duty 1/2 duty 1/3 duty 1/4 duty ircclk = 0.5 0 0 0 0 0 1 1024 2048 488 244 488 244 244 122 163 81 122 61 ircclk = 1.0 0 0 0 1 1 0 2048 4096 488 244 488 244 244 122 163 81 122 61 ircclk = 2.0 0 0 1 1 0 1 4096 8192 488 244 488 244 244 122 163 81 122 61 ircclk = 4.0 0 1 1 0 1 0 8192 16384 488 244 488 244 244 122 163 81 122 61 ircclk = 8.0 1 1 0 0 0 1 16384 32768 488 244 488 244 244 122 163 81 122 61
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 558 freescale semiconductor for other combinations of ircclk and divider not shown in table 17-8 , the following formula may be used to calculate the lcd frame frequency for each multiplex mode: the possible divider values are shown in table 17-8 . 17.4.1.3 lcd ram for a segment on the lcd to be displayed, data must be written to the lcd ram which is shown in section 17.3, ?emory map and register definition . the 160 bits in the lcd ram correspond to the 160 segments that are driven by the frontplane and backplane drivers. writing a 1 to a given location will result in the corresponding display segment being driven with a differential rms voltage necessary to turn the segment on when the lcden bit is set and the corresponding fp[39:0]en bit is set. writing a 0 to a given location will result in the corresponding display segment being driven with a differential rms voltage necessary to turn the segment off. the lcd ram is a dual port ram that interfaces with the internal address and data buses of the mcu. it is possible to read from lcd ram locations for scrolling purposes. when lcden = 0, the lcd ram can be used as on-chip ram. writing or reading of the lcden bit does not change the contents of the lcd ram. after a reset, the lcd ram contents will be indeterminate. 17.4.1.4 lcd driver system enable and frontplane enable sequencing if lcden = 0 (lcd40f4bv2 driver system disabled) and the frontplane enable bit, fp[39:0]en, is set, the frontplane driver waveform will not appear on the output until lcden is set. if lcden = 1 (lcd40f4bv2 driver system enabled), the frontplane driver waveform will appear on the output as soon as the corresponding frontplane enable bit, fp[39:0]en, in the registers fpenr0?penr4 is set. 17.4.1.5 lcd bias and modes of operation the lcd40f4bv2 driver has five modes of operation: 1/1 duty (1 backplane), 1/1 bias (2 voltage levels) 1/2 duty (2 backplanes), 1/2 bias (3 voltage levels) 1/2 duty (2 backplanes), 1/3 bias (4 voltage levels) 1/3 duty (3 backplanes), 1/3 bias (4 voltage levels) 1/4 duty (4 backplanes), 1/3 bias (4 voltage levels) ircclk = 16.0 1 1 1 1 0 1 65536 131072 244 122 244 122 122 61 81 40 61 31 table 17-8. lcd clock and frame frequency source clock frequency in mhz lcd clock prescaler divider lcd clock frequency [hz] frame frequency [hz] lclk2 lclk1 lclk0 1/1 duty 1/2 duty 1/3 duty 1/4 duty lcd frame frequency (hz) ircclk (hz) () divider -------------------------------------- duty ? =
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 559 the voltage levels required for the different operating modes are generated internally based on vlcd. changing vlcd alters the differential rms voltage across the segments in the on and off states, thereby setting the display contrast. the backplane waveforms are continuous and repetitive every frame. they are fixed within each operating mode and are not affected by the data in the lcd ram. the frontplane waveforms generated are dependent on the state (on or off) of the lcd segments as defined in the lcd ram. the lcd40f4bv2 driver hardware uses the data in the lcd ram to construct the frontplane waveform to create a differential rms voltage necessary to turn the segment on or off. the lcd duty is decided by the duty1 and duty0 bits in the lcd control register 0 (lcdcr0). the number of bias voltage levels is determined by the bias bit in lcdcr0. table 17-9 summarizes the multiplex modes (duties) and the bias voltage levels that can be selected for each multiplex mode (duty). the backplane pins have their corresponding backplane waveform output bp[3:0] in high impedance state when in the off state as indicated in table 17-9 . in the off state the corresponding pins bp[3:0]can be used for other functionality, for example as general purpose i/o ports. 17.4.2 operation in wait mode the lcd40f4bv2 driver system operation during wait mode is controlled by the lcd stop in wait (lcdswai) bit in the lcd control register 1 (lcdcr1). if lcdswai is reset, the lcd40f4bv2 driver system continues to operate during wait mode. if lcdswai is set, the lcd40f4bv2 driver system is turned off during wait mode. in this case, the lcd waveform generation clocks are stopped and the lcd40f4bv2 drivers pull down to vssx those frontplane and backplane pins that were enabled before entering wait mode. the contents of the lcd ram and the lcd registers retain the values they had prior to entering wait mode. 17.4.3 operation in stop mode all lcd40f4bv2 driver system clocks are stopped, the lcd40f4bv2 driver system pulls down to vssx those frontplane and backplane pins that were enabled before entering stop mode. also, during stop mode, the contents of the lcd ram and the lcd registers retain the values they had prior to entering stop mode. as a result, after exiting from stop mode, the lcd40f4bv2 driver system clocks will run (if lcden = 1) and the frontplane and backplane pins retain the functionality they had prior to entering stop mode. table 17-9. lcd duty and bias duty lcdcr0 register backplanes bias (bias = 0) bias (bias = 1) duty1 duty0 bp3 bp2 bp1 bp0 1/1 1/2 1/3 1/1 1/2 1/3 1/1 1/2 1/3 1/4 0 1 1 0 1 0 1 0 off off off bp3 off off bp2 bp2 off bp1 bp1 bp1 bp0 bp0 bp0 bp0 yes na na na na yes na na na na yes yes yes na na na na na na na na yes yes yes
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 560 freescale semiconductor 17.4.4 lcd waveform examples figure 17-10 through figure 17-14 show the timing examples of the lcd output waveforms for the available modes of operation.
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 561 17.4.4.1 1/1 duty multiplexed with 1/1 bias mode duty = 1/1:duty1 = 0, duty0 = 1 bias = 1/1:bias = 0 or bias = 1 v 0 = v 1 = vssx, v 2 = v 3 = vlcd - bp1, bp2, and bp3 are not used, a maximum of 40 segments are displayed. figure 17-10. 1/1 duty and 1/1 bias 0 0 vlcd vssx bp0 +vlcd -vlcd bp0-fpx (off) +vlcd -vlcd bp0-fpy (on) vlcd vssx fpx (xxx0) vlcd vssx fpy (xxx1) 1 frame
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 562 freescale semiconductor 17.4.4.2 1/2 duty multiplexed with 1/2 bias mode duty = 1/2:duty1 = 1, duty0 = 0 bias = 1/2:bias = 0 v 0 = vssx, v 1 = v 2 = vlcd * 1/2, v 3 = vlcd - bp2 and bp3 are not used, a maximum of 80 segments are displayed. figure 17-11. 1/2 duty and 1/2 bias 0 vlcd vssx bp0 +vlcd -vlcd bp0-fpx (off) 1 frame vlcd 1/2 vlcd vssx bp1 vlcd vssx fpx (xx10) vlcd vssx fpy (xx00) vlcd vssx fpz (xx11) +vlcd 1/2 -vlcd 1/2 0 +vlcd -vlcd bp1-fpx (on) +vlcd 1/2 -vlcd 1/2 0 +vlcd -vlcd bp0-fpy (off) +vlcd 1/2 -vlcd 1/2 0 +vlcd -vlcd bp0-fpz (on) +vlcd 1/2 -vlcd 1/2 vlcd 1/2 vlcd 1/2 vlcd 1/2 vlcd 1/2
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 563 17.4.4.3 1/2 duty multiplexed with 1/3 bias mode duty = 1/2:duty1 = 1, duty0 = 0 bias = 1/3:bias = 1 v 0 = vssx, v 1 = vlcd * 1/3, v 2 = vlcd * 2/3, v 3 = vlcd - bp2 and bp3 are not used, a maximum of 80 segments are displayed.
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 564 freescale semiconductor figure 17-12. 1/2 duty and 1/3 bias -vlcd 1/3 +vlcd 1/3 -vlcd 1/3 +vlcd 1/3 -vlcd 1/3 vlcd 1/3 0 vlcd vssx bp0 -vlcd bp0-fpx (off) 1 frame vlcd 2/3 +vlcd 2/3 -vlcd 2/3 vlcd vssx bp1 vlcd 2/3 vlcd vssx fpx (xx10) vlcd 2/3 vlcd vssx fpy (xx00) vlcd 2/3 vlcd vssx fpz (xx11) vlcd 2/3 +vlcd 1/3 -vlcd 1/3 0 +vlcd -vlcd bp1-fpx (on) +vlcd 2/3 -vlcd 2/3 +vlcd 1/3 0 +vlcd -vlcd bp0-fpy (off) +vlcd 2/3 -vlcd 2/3 0 +vlcd -vlcd bp0-fpz (on) +vlcd 2/3 -vlcd 2/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 +vlcd
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 565 17.4.4.4 1/3 duty multiplexed with 1/3 bias mode duty = 1/3:duty1 = 1, duty0 = 1 bias = 1/3:bias = 0 or bias = 1 v 0 = vssx, v 1 = vlcd * 1/3, v 2 = vlcd * 2/3, v 3 = vlcd - bp3 is not used, a maximum of 120 segments are displayed. figure 17-13. 1/3 duty and 1/3 bias +vlcd 1/3 -vlcd 1/3 +vlcd 1/3 -vlcd 1/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 0 vlcd vssx bp0 +vlcd -vlcd bp0-fpx (off) 1 frame vlcd 2/3 +vlcd 2/3 -vlcd 2/3 vlcd vssx bp1 vlcd 2/3 vlcd vssx bp2 vlcd 2/3 0 +vlcd -vlcd bp1-fpx (on) +vlcd 2/3 -vlcd 2/3 vlcd vssx fpx (x010) vlcd 2/3
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 566 freescale semiconductor 17.4.4.5 1/4 duty multiplexed with 1/3 bias mode duty = 1/4:duty1 = 0, duty0 = 0 bias = 1/3:bias = 0 or bias = 1 v 0 = vssx, v 1 = vlcd * 1/3, v 2 = vlcd * 2/3, v 3 = vlcd - a maximum of 160 segments are displayed. figure 17-14. 1/4 duty and 1/3 bias +vlcd 1/3 -vlcd 1/3 +vlcd 1/3 -vlcd 1/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 vlcd 1/3 0 vlcd vssx bp0 +vlcd -vlcd bp0-fpx (on) 1 frame vlcd 2/3 +vlcd 2/3 -vlcd 2/3 vlcd vssx bp1 vlcd 2/3 vlcd vssx bp2 vlcd 2/3 0 +vlcd -vlcd bp1-fpx (off) +vlcd 2/3 -vlcd 2/3 vlcd vssx fpx (1001) vlcd 2/3 vlcd vssx bp3 vlcd 2/3
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 567 17.5 resets the reset values of registers and signals are described in section 17.3, ?emory map and register definition . the behavior of the lcd40f4bv2 system during reset is described in section 17.4.1, ?cd driver description . 17.6 interrupts this module does not generate any interrupts.
liquid crystal display (lcd40f4bv2) block description mc9s12xhy-family reference manual, rev. 1.01 568 freescale semiconductor
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 569 preliminary chapter 18 256 kbyte flash module (s12xftmr256k1v1) 18.1 introduction the ftmr256k1 module implements the following: 256 kbytes of p-flash (program flash) memory 8 kbytes of d-flash (data flash) memory the flash memory is ideal for single-supply applications allowing for ?ld reprogramming without requiring external high voltage sources for program or erase operations. the flash module includes a memory controller that executes commands to modify flash memory contents. the user interface to the memory controller consists of the indexed flash common command object (fccob) register which is written to with the command, global address, data, and any required command parameters. the memory controller must complete the execution of a command before the fccob register can be written to with a new command. caution a flash word or phrase must be in the erased state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. the flash memory may be read as bytes, aligned words, or misaligned words. read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. for flash memory, an erased bit reads 1 and a programmed bit reads 0. it is not possible to read from a flash block while any command is executing on that speci? flash block. it is possible to read from a flash block while a command is executing on a different flash block. both p-flash and d-flash memories are implemented with error correction codes (ecc) that can resolve single bit faults and detect double bit faults. for p-flash memory, the ecc implementation requires that programming be done on an aligned 8 byte basis (a flash phrase). since p-flash memory is always read by phrase, only one single bit fault in the phrase containing the byte or word accessed will be corrected. 18.1.1 glossary command write sequence ?an mcu instruction sequence to execute built-in algorithms (including program and erase) on the flash memory. d-flash memory ?the d-flash memory constitutes the nonvolatile memory store for data.
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 570 preliminary d-flash sector the d-flash sector is the smallest portion of the d-flash memory that can be erased. the d-flash sector consists of four 64 byte rows for a total of 256 bytes. nvm command mode an nvm mode using the cpu to setup the fccob register to pass parameters required for flash command execution. phrase an aligned group of four 16-bit words within the p-flash memory. each phrase includes eight ecc bits for single bit fault correction and double bit fault detection within the phrase. p-flash memory the p-flash memory constitutes the main nonvolatile memory store for applications. p-flash sector ?the p-flash sector is the smallest portion of the p-flash memory that can be erased. each p-flash sector contains 1024 bytes. program ifr ?nonvolatile information register located in the p-flash block that contains the device id, version id, and the program once ?ld. the program ifr is visible in the global memory map by setting the pgmifron bit in the mmcctl1 register. 18.1.2 features 18.1.2.1 p-flash features 256 kbytes of p-flash memory composed of one 256 kbyte flash block divided into 256 sectors of 1024 bytes single bit fault correction and double bit fault detection within a 64-bit phrase during read operations automated program and erase algorithm with verify and generation of ecc parity bits fast sector erase and phrase program operation flexible protection scheme to prevent accidental program or erase of p-flash memory 18.1.2.2 d-flash features 8 kbytes of d-flash memory composed of one 8 kbyte flash block divided into 32 sectors of 256 bytes single bit fault correction and double bit fault detection within a word during read operations automated program and erase algorithm with verify and generation of ecc parity bits fast sector erase and word program operation protection scheme to prevent accidental program or erase of d-flash memory ability to program up to four words in a burst sequence
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 571 18.1.2.3 other flash module features no external high-voltage power supply required for flash memory program and erase operations interrupt generation on flash command completion and flash error detection security mechanism to prevent unauthorized access to the flash memory 18.1.3 block diagram the block diagram of the flash module is shown in figure 18-1 . figure 18-1. ftmr256k1 block diagram oscillator clock divider clock (xtal) command interrupt request fclk protection security registers flash interface p-flash 32kx72 sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 16bit internal bus 16kx72 16kx72 error interrupt request cpu memory controller d-flash 4kx22 sector 0 sector 1 sector 31 scratch ram 384x16
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 572 freescale semiconductor 18.2 external signal description the flash module contains no signals that connect off-chip. 18.3 memory map and registers this section describes the memory map and registers for the flash module. read data from unimplemented memory space in the flash module is unde?ed. write access to unimplemented or reserved memory space in the flash module will be ignored by the flash module. 18.3.1 module memory map the s12x architecture places the p-flash memory between global addresses 0x7c_0000 and 0x7f_ffff as shown in table 18-1 . the p-flash memory map is shown in figure 18-2 . the fprot register, described in section 18.3.1.9 , can be set to protect regions in the flash memory from accidental program or erase. three separate memory regions, one growing upward from global address 0x7f_8000 in the flash memory (called the lower region), one growing downward from global address 0x7f_ffff in the flash memory (called the higher region), and the remaining addresses in the flash memory, can be activated for protection. the flash memory addresses covered by these protectable regions are shown in the p-flash memory map. the higher address region is mainly targeted to hold the boot loader code since it covers the vector space. default protection settings as well as security information that allows the mcu to restrict access to the flash module are stored in the flash con?uration ?ld as described in table 18-2 . table 18-1. p-flash memory addressing global address size (bytes) description 0x7c_0000 ?0x7f_ffff 256 k p-flash block 0 contains flash con?uration field (see table 18-2 ) table 18-2. flash con?uration field 1 global address size (bytes) description 0x7f_ff00 ?0x7f_ff07 8 backdoor comparison key refer to section 18.4.2.11, ?erify backdoor access key command , and section 18.5.1, ?nsecuring the mcu using backdoor key access 0x7f_ff08 0x7f_ff0b 2 4 reserved 0x7f_ff0c 2 1 p-flash protection byte . refer to section 18.3.1.9, ?-flash protection register (fprot) 0x7f_ff0d 2 1 d-flash protection byte . refer to section 18.3.1.10, ?-flash protection register (dfprot) 0x7f_ff0e 2 1 flash nonvolatile byte refer to section 18.3.1.15, ?lash option register (fopt)
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 573 0x7f_ff0f 2 1 flash security byte refer to section 18.3.1.2, ?lash security register (fsec) 1 older versions may have swapped protection byte addresses 2 0x7ff08 - 0x7f_ff0f form a flash phrase and must be programmed in a single command write sequence. each byte in the 0x7f_ff08 - 0x7f_ff0b reserved ?ld should be programmed to 0xff. table 18-2. flash con?uration field 1 global address size (bytes) description
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 574 freescale semiconductor figure 18-2. p-flash memory map flash con?uration field 0x7f_c000 flash protected/unprotected lower region 1, 2, 4, 8 kbytes 0x7f_8000 0x7f_9000 0x7f_8400 0x7f_8800 0x7f_a000 p-flash end = 0x7f_ffff 0x7f_f800 0x7f_f000 0x7f_e000 flash protected/unprotected higher region 2, 4, 8, 16 kbytes flash protected/unprotected region 8 kbytes (up to 29 kbytes) 16 bytes (0x7f_ff00 - 0x7f_ff0f) flash protected/unprotected region 224 kbytes p-flash start = 0x7c_0000
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 575 register descriptions the flash module contains a set of 20 control and status registers located between flash module base + 0x0000 and 0x0013. a summary of the flash module registers is given in figure 18-3 with detailed descriptions in the following subsections. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and memory controller behavior. table 18-3. program ifr fields global address (pgmifron) size (bytes) field description 0x40_0000 ?0x40_0007 8 device id 0x40_0008 ?0x40_00e7 224 reserved 0x40_00e8 ?0x40_00e9 2 version id 0x40_00ea ?0x40_00ff 22 reserved 0x40_0100 ?0x40_013f 64 program once field refer to section 18.4.2.6, ?rogram once command 0x40_0140 ?0x40_01ff 192 reserved 0x12_ffff 0x12_4000 0x12_1000 memory controller scratch ram (mgramon) 768 bytes d-flash nonvolatile information register (dfifron) 128 bytes d-flash memory 8 kbytes d-flash start = 0x10_0000 0x12_0000 0x12_2000 0x12_e800 d-flash end = 0x10_1fff
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 576 freescale semiconductor address & name 76543210 0x0000 fclkdiv r fdivld fdiv6 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w 0x0001 fsec r keyen1 keyen0 rnv5 rnv4 rnv3 rnv2 sec1 sec0 w 0x0002 fccobix r0 0 0 0 0 ccobix2 ccobix1 ccobix0 w 0x0003 feccrix r0 0 0 0 0 eccrix2 eccrix1 eccrix0 w 0x0004 fcnfg r ccie 00 ignsf 00 fdfd fsfd w 0x0005 fercnfg r 0 dfdie sfdie w 0x0006 fstat r ccif 0 accerr fpviol mgbusy rsvd mgstat1 mgstat0 w 0x0007 ferstat r0 0 0 0 0 0 dfdif sfdif w 0x0008 fprot r fpopen rnv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 w 0x0009 dfprot r dpopen 00 dps4 dps3 dps2 dps1 dps0 w 0x000a fccobhi r ccob15 ccob14 ccob13 ccob12 ccob11 ccob10 ccob9 ccob8 w 0x000b fccoblo r ccob7 ccob6 ccob5 ccob4 ccob3 ccob2 ccob1 ccob0 w 0x000c frsv0 r00000000 w 0x000d frsv1 r00000000 w figure 18-3. ftmr256k1 register summary
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 577 18.3.1.1 flash clock divider register (fclkdiv) the fclkdiv register is used to control timed events in program and erase algorithms. all bits in the fclkdiv register are readable, bits 6? are write once and bit 7 is not writable. 0x000e feccrhi r eccr15 eccr14 eccr13 eccr12 eccr11 eccr10 eccr9 eccr8 w 0x000f feccrlo r eccr7 eccr6 eccr5 eccr4 eccr3 eccr2 eccr1 eccr0 w 0x0010 fopt r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w 0x0011 frsv2 r00000000 w 0x0012 frsv3 r00000000 w 0x0013 frsv4 r00000000 w = unimplemented or reserved offset module base + 0x0000 76543210 r fdivld fdiv[6:0] w reset 00000000 = unimplemented or reserved figure 18-4. flash clock divider register (fclkdiv) address & name 76543210 figure 18-3. ftmr256k1 register summary (continued)
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 578 freescale semiconductor caution the fclkdiv register should never be written while a flash command is executing (ccif=0). the fclkdiv register is writable during the flash reset sequence even though ccif is clear. table 18-4. fclkdiv field descriptions field description 7 fdivld clock divider loaded 0 fclkdiv register has not been written 1 fclkdiv register has been written since the last reset 6? fdiv[6:0] clock divider bits ?fdiv[6:0] must be set to effectively divide oscclk down to generate an internal flash clock, fclk, with a target frequency of 1 mhz for use by the flash module to control timed events during program and erase algorithms. table 18-5 shows recommended values for fdiv[6:0] based on oscclk frequency. please refer to section 18.4.1, ?lash command operations , for more information.
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 579 table 18-5. fdiv vs oscclk frequency oscclk frequency (mhz) fdiv[6:0] oscclk frequency (mhz) fdiv[6:0] min 1 1 fdiv shown generates an fclk frequency of >0.8 mhz max 2 2 fdiv shown generates an fclk frequency of 1.05 mhz min 1 max 2 1.60 2.10 0x01 33.60 34.65 0x20 2.40 3.15 0x02 34.65 35.70 0x21 3.20 4.20 0x03 35.70 36.75 0x22 4.20 5.25 0x04 36.75 37.80 0x23 5.25 6.30 0x05 37.80 38.85 0x24 6.30 7.35 0x06 38.85 39.90 0x25 7.35 8.40 0x07 39.90 40.95 0x26 8.40 9.45 0x08 40.95 42.00 0x27 9.45 10.50 0x09 42.00 43.05 0x28 10.50 11.55 0x0a 43.05 44.10 0x29 11.55 12.60 0x0b 44.10 45.15 0x2a 12.60 13.65 0x0c 45.15 46.20 0x2b 13.65 14.70 0x0d 46.20 47.25 0x2c 14.70 15.75 0x0e 47.25 48.30 0x2d 15.75 16.80 0x0f 48.30 49.35 0x2e 16.80 17.85 0x10 49.35 50.40 0x2f 17.85 18.90 0x11 18.90 19.95 0x12 19.95 21.00 0x13 21.00 22.05 0x14 22.05 23.10 0x15 23.10 24.15 0x16 24.15 25.20 0x17 25.20 26.25 0x18 26.25 27.30 0x19 27.30 28.35 0x1a 28.35 29.40 0x1b 29.40 30.45 0x1c 30.45 31.50 0x1d 31.50 32.55 0x1e 32.55 33.60 0x1f
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 580 freescale semiconductor 18.3.1.2 flash security register (fsec) the fsec register holds all bits associated with the security of the mcu and flash module. all bits in the fsec register are readable but not writable. during the reset sequence, the fsec register is loaded with the contents of the flash security byte in the flash configuration field at global address 0x7f_ff0f located in p-flash memory (see table 18-2 ) as indicated by reset condition f in figure 18-5 . if a double bit fault is detected while reading the p-flash phrase containing the flash security byte during the reset sequence, all bits in the fsec register will be set to leave the flash module in a secured state with backdoor key access disabled. offset module base + 0x0001 76543210 r keyen[1:0] rnv[5:2] sec[1:0] w reset f f ffffff = unimplemented or reserved figure 18-5. flash security register (fsec) table 18-6. fsec field descriptions field description 7? keyen[1:0] backdoor key security enable bits the keyen[1:0] bits de?e the enabling of backdoor key access to the flash module as shown in table 18-7 . 5? rnv[5:2} reserved nonvolatile bits ?the rnv bits should remain in the erased state for future enhancements. 1? sec[1:0] flash security bits ?the sec[1:0] bits de?e the security state of the mcu as shown in table 18-8 . if the flash module is unsecured using backdoor key access, the sec bits are forced to 10. table 18-7. flash keyen states keyen[1:0] status of backdoor key access 00 disabled 01 disabled 1 1 preferred keyen state to disable backdoor key access. 10 enabled 11 disabled table 18-8. flash security states sec[1:0] status of security 00 secured 01 secured 1 10 unsecured 11 secured
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 581 the security function in the flash module is described in section 18.5 . 18.3.1.3 flash ccob index register (fccobix) the fccobix register is used to index the fccob register for flash memory operations. ccobix bits are readable and writable while remaining bits read 0 and are not writable. 18.3.1.4 flash eccr index register (feccrix) the feccrix register is used to index the feccr register for ecc fault reporting. eccrix bits are readable and writable while remaining bits read 0 and are not writable. 1 preferred sec state to set mcu to secured state. offset module base + 0x0002 76543210 r00000 ccobix[2:0] w reset 00000000 = unimplemented or reserved figure 18-6. fccob index register (fccobix) table 18-9. fccobix field descriptions field description 2? ccobix[1:0] common command register index the ccobix bits are used to select which word of the fccob register array is being read or written to. see section 18.3.1.11, ?lash common command object register (fccob) , for more details. offset module base + 0x0003 76543210 r00000 eccrix[2:0] w reset 00000000 = unimplemented or reserved figure 18-7. feccr index register (feccrix) table 18-10. feccrix field descriptions field description 2-0 eccrix[2:0] ecc error register index ?the eccrix bits are used to select which word of the feccr register array is being read. see section 18.3.1.14, ?lash ecc error results register (feccr) , for more details.
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 582 freescale semiconductor 18.3.1.5 flash con?uration register (fcnfg) the fcnfg register enables the flash command complete interrupt and forces ecc faults on flash array read access from the cpu or xgate. ccie, ignsf, fdfd, and fsfd bits are readable and writable while remaining bits read 0 and are not writable. 18.3.1.6 flash error con?uration register (fercnfg) the fercnfg register enables the flash error interrupts for the ferstat flags. offset module base + 0x0004 76543210 r ccie 00 ignsf 00 fdfd fsfd w reset 00000000 = unimplemented or reserved figure 18-8. flash con?uration register (fcnfg) table 18-11. fcnfg field descriptions field description 7 ccie command complete interrupt enable ?the ccie bit controls interrupt generation when a flash command has completed. 0 command complete interrupt disabled 1 an interrupt will be requested whenever the ccif ?g in the fstat register is set (see section 18.3.1.7 ) 4 ignsf ignore single bit fault ?the ignsf controls single bit fault reporting in the ferstat register (see section 18.3.1.8 ). 0 all single bit faults detected during array reads are reported 1 single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 fdfd force double bit fault detect the fdfd bit allows the user to simulate a double bit fault during flash array read operations and check the associated interrupt routine. the fdfd bit is cleared by writing a 0 to fdfd. the feccr registers will not be updated during the flash array read operation with fdfd set unless an actual double bit fault is detected. 0 flash array read operations will set the dfdif ?g in the ferstat register only if a double bit fault is detected 1 any flash array read operation will force the dfdif ?g in the ferstat register to be set (see section 18.3.1.7 ) and an interrupt will be generated as long as the dfdie interrupt enable in the fercnfg register is set (see section 18.3.1.6 ) 0 fsfd force single bit fault detect the fsfd bit allows the user to simulate a single bit fault during flash array read operations and check the associated interrupt routine. the fsfd bit is cleared by writing a 0 to fsfd. the feccr registers will not be updated during the flash array read operation with fsfd set unless an actual single bit fault is detected. 0 flash array read operations will set the sfdif ?g in the ferstat register only if a single bit fault is detected 1 flash array read operation will force the sfdif ?g in the ferstat register to be set (see section 18.3.1.7 ) and an interrupt will be generated as long as the sfdie interrupt enable in the fercnfg register is set (see section 18.3.1.6 )
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 583 all assigned bits in the fercnfg register are readable and writable. 18.3.1.7 flash status register (fstat) the fstat register reports the operational status of the flash module. ccif, accerr, and fpviol bits are readable and writable, mgbusy and mgstat bits are readable but not writable, while remaining bits read 0 and are not writable. offset module base + 0x0005 76543210 r 0 dfdie sfdie w reset 00000000 = unimplemented or reserved figure 18-9. flash error con?uration register (fercnfg) table 18-12. fercnfg field descriptions field description 1 dfdie double bit fault detect interrupt enable the dfdie bit controls interrupt generation when a double bit fault is detected during a flash block read operation. 0 dfdif interrupt disabled 1 an interrupt will be requested whenever the dfdif ?g is set (see section 18.3.1.8 ) 0 sfdie single bit fault detect interrupt enable the sfdie bit controls interrupt generation when a single bit fault is detected during a flash block read operation. 0 sfdif interrupt disabled whenever the sfdif ?g is set (see section 18.3.1.8 ) 1 an interrupt will be requested whenever the sfdif ?g is set (see section 18.3.1.8 ) offset module base + 0x0006 76543210 r ccif 0 accerr fpviol mgbusy rsvd mgstat[1:0] w reset 1000000 1 1 reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see section 18.6 ). 0 1 = unimplemented or reserved figure 18-10. flash status register (fstat)
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 584 freescale semiconductor 18.3.1.8 flash error status register (ferstat) the ferstat register re?cts the error status of internal flash operations. all ?gs in the ferstat register are readable and only writable to clear the ?g. table 18-13. fstat field descriptions field description 7 ccif command complete interrupt flag ?the ccif ?g indicates that a flash command has completed. the ccif ?g is cleared by writing a 1 to ccif to launch a command and ccif will stay low until command completion or command violation. 0 flash command in progress 1 flash command has completed 5 accerr flash access error flag ?the accerr bit indicates an illegal access has occurred to the flash memory caused by either a violation of the command write sequence (see section 18.4.1.2 ) or issuing an illegal flash command. while accerr is set, the ccif ?g cannot be cleared to launch a command. the accerr bit is cleared by writing a 1 to accerr. writing a 0 to the accerr bit has no effect on accerr. 0 no access error detected 1 access error detected 4 fpviol flash protection violation flag ?he fpviol bit indicates an attempt was made to program or erase an address in a protected area of p-flash or d-flash memory during a command write sequence. the fpviol bit is cleared by writing a 1 to fpviol. writing a 0 to the fpviol bit has no effect on fpviol. while fpviol is set, it is not possible to launch a command or start a command write sequence. 0 no protection violation detected 1 protection violation detected 3 mgbusy memory controller busy flag ?the mgbusy ?g re?cts the active state of the memory controller . 0 memory controller is idle 1 memory controller is busy executing a flash command (ccif = 0) 2 rsvd reserved bit ?this bit is reserved and always reads 0 . 1? mgstat[1:0] memory controller command completion status flag one or more mgstat ?g bits are set if an error is detected during execution of a flash command or during the flash reset sequence. see section 18.4.2, ?lash command description , and section 18.6, ?nitialization ?for details. offset module base + 0x0007 76543210 r000000 dfdif sfdif w reset 00000000 = unimplemented or reserved figure 18-11. flash error status register (ferstat)
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 585 18.3.1.9 p-flash protection register (fprot) the fprot register defines which p-flash sectors are protected against program and erase operations. the (unreserved) bits of the fprot register are writable with the restriction that the size of the protected region can only be increased (see section 18.3.1.9.1, ?-flash protection restrictions , and table 18-19 ). during the reset sequence, the fprot register is loaded with the contents of the p-flash protection byte in the flash configuration field at global address 0x7f_ff0c located in p-flash memory (see table 18-2 ) as indicated by reset condition ??in figure 18-12 . to change the p-flash protection that will be loaded during the reset sequence, the upper sector of the p-flash memory must be unprotected, then the p-flash protection byte must be reprogrammed. if a double bit fault is detected while reading the p-flash phrase containing the p-flash protection byte during the reset sequence, the fpopen bit will be cleared and remaining bits in the fprot register will be set to leave the p-flash memory fully protected. trying to alter data in any protected area in the p-flash memory will result in a protection violation error and the fpviol bit will be set in the fstat register. the block erase of a p-flash block is not possible if any of the p-flash sectors contained in the same p-flash block are protected. table 18-14. ferstat field descriptions field description 1 dfdif double bit fault detect interrupt flag ?the setting of the dfdif ?g indicates that a double bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation was attempted on a flash block that was under a flash command operation. the dfdif ?g is cleared by writing a 1 to dfdif. writing a 0 to dfdif has no effect on dfdif. 0 no double bit fault detected 1 double bit fault detected or an invalid flash array read operation attempted 0 sfdif single bit fault detect interrupt flag ?with the ignsf bit in the fcnfg register clear, the sfdif ?g indicates that a single bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation was attempted on a flash block that was under a flash command operation. the sfdif ?g is cleared by writing a 1 to sfdif. writing a 0 to sfdif has no effect on sfdif. 0 no single bit fault detected 1 single bit fault detected and corrected or an invalid flash array read operation attempted offset module base + 0x0008 76543210 r fpopen rnv6 fphdis fphs[1:0] fpldis fpls[1:0] w reset f f ffffff = unimplemented or reserved figure 18-12. flash protection register (fprot)
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 586 freescale semiconductor table 18-15. fprot field descriptions field description 7 fpopen flash protection operation enable ?the fpopen bit determines the protection function for program or erase operations as shown in table 18-16 for the p-flash block. 0 when fpopen is clear, the fphdis and fpldis bits de?e unprotected address ranges as speci?d by the corresponding fphs and fpls bits 1 when fpopen is set, the fphdis and fpldis bits enable protection for the address range speci?d by the corresponding fphs and fpls bits 6 rnv[6] reserved nonvolatile bit ?the rnv bit should remain in the erased state for future enhancements. 5 fphdis flash protection higher address range disable ?the fphdis bit determines whether there is a protected/unprotected area in a speci? region of the p-flash memory ending with global address 0x7f_ffff. 0 protection/unprotection enabled 1 protection/unprotection disabled 4? fphs[1:0] flash protection higher address size the fphs bits determine the size of the protected/unprotected area in p-flash memory as shown in table 18-17 . the fphs bits can only be written to while the fphdis bit is set. 2 fpldis flash protection lower address range disable ?the fpldis bit determines whether there is a protected/unprotected area in a speci? region of the p-flash memory beginning with global address 0x7f_8000. 0 protection/unprotection enabled 1 protection/unprotection disabled 1? fpls[1:0] flash protection lower address size the fpls bits determine the size of the protected/unprotected area in p-flash memory as shown in table 18-18 . the fpls bits can only be written to while the fpldis bit is set. table 18-16. p-flash protection function fpopen fphdis fpldis function 1 1 for range sizes, refer to table 18-17 and table 18-18 . 1 1 1 no p-flash protection 1 1 0 protected low range 1 0 1 protected high range 1 0 0 protected high and low ranges 0 1 1 full p-flash memory protected 0 1 0 unprotected low range 0 0 1 unprotected high range 0 0 0 unprotected high and low ranges table 18-17. p-flash protection higher address range fphs[1:0] global address range protected size 00 0x7f_f800?x7f_ffff 2 kbytes 01 0x7f_f000?x7f_ffff 4 kbytes 10 0x7f_e000?x7f_ffff 8 kbytes 11 0x7f_c000?x7f_ffff 16 kbytes
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 587 all possible p-flash protection scenarios are shown in figure 18-13 . although the protection scheme is loaded from the flash memory at global address 0x7f_ff0c during the reset sequence, it can be changed by the user. the p-flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. table 18-18. p-flash protection lower address range fpls[1:0] global address range protected size 00 0x7f_8000?x7f_83ff 1 kbyte 01 0x7f_8000?x7f_87ff 2 kbytes 10 0x7f_8000?x7f_8fff 4 kbytes 11 0x7f_8000?x7f_9fff 8 kbytes
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 588 freescale semiconductor figure 18-13. p-flash protection scenarios 7 6 5 4 fphs[1:0] fpls[1:0] 3 2 1 0 fphs[1:0] fpls[1:0] fphdis = 1 fpldis = 1 fphdis = 1 fpldis = 0 fphdis = 0 fpldis = 1 fphdis = 0 fpldis = 0 scenario scenario unprotected region protected region with size protected region protected region with size defined by fpls defined by fphs not defined by fpls, fphs 0x7f_8000 0x7f_ffff 0x7f_8000 0x7f_ffff flash start flash start fpopen = 1 fpopen = 0
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 589 18.3.1.9.1 p-flash protection restrictions the general guideline is that p-flash protection can only be added and not removed. table 18-19 specifies all valid transitions between p-flash protection scenarios. any attempt to write an invalid scenario to the fprot register will be ignored. the contents of the fprot register reflect the active protection scenario. see the fphs and fpls bit descriptions for additional restrictions. 18.3.1.10 d-flash protection register (dfprot) the dfprot register de?es which d-flash sectors are protected against program and erase operations. the (unreserved) bits of the dfprot register are writable with the restriction that protection can be added but not removed. writes must increase the dps value and the dpoen bit can only be written from 1 (protection disabled) to 0 (protection enabled). if the dpopen bit is set, the state of the dps bits is irrelevant. during the reset sequence, the dfprot register is loaded with the contents of the d-flash protection byte in the flash configuration field at global address 0x7f_ff0d located in p-flash memory (see table 18-2 ) as indicated by reset condition f in figure 18-14 . to change the d-flash protection that will be loaded during the reset sequence, the p-flash sector containing the d-flash protection byte must be unprotected, then the d-flash protection byte must be programmed. if a double bit fault is detected while reading the table 18-19. p-flash protection scenario transitions from protection scenario to protection scenario 1 1 allowed transitions marked with x, see figure 18-13 for a de?ition of the scenarios. 01234567 0 xxxx 1 xx 2 xx 3 x 4 xx 5 xxxx 6 xxxx 7 xxxxxxxx offset module base + 0x0009 76543210 r dpopen 00 dps[4:0] w reset f 0 0 fffff = unimplemented or reserved figure 18-14. d-flash protection register (dfprot)
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 590 freescale semiconductor p-flash phrase containing the d-flash protection byte during the reset sequence, the dpopen bit will be cleared and dps bits will be set to leave the d-flash memory fully protected. trying to alter data in any protected area in the d-flash memory will result in a protection violation error and the fpviol bit will be set in the fstat register. block erase of the d-flash memory is not possible if any of the d-flash sectors are protected. table 18-20. dfprot field descriptions field description 7 dpopen d-flash protection control 0 enables d-flash memory protection from program and erase with protected address range de?ed by dps bits 1 disables d-flash memory protection from program and erase 4? dps[4:0] d-flash protection size the dps[4:0] bits determine the size of the protected area in the d-flash memory as shown in table 18-21 . table 18-21. d-flash protection address range dps[4:0] global address range protected size 0_0000 0x10_0000 ?0x10_00ff 256 bytes 0_0001 0x10_0000 ?0x10_01ff 512 bytes 0_0010 0x10_0000 ?0x10_02ff 768 bytes 0_0011 0x10_0000 ?0x10_03ff 1024 bytes 0_0100 0x10_0000 ?0x10_04ff 1280 bytes 0_0101 0x10_0000 ?0x10_05ff 1536 bytes 0_0110 0x10_0000 ?0x10_06ff 1792 bytes 0_0111 0x10_0000 ?0x10_07ff 2048 bytes 0_1000 0x10_0000 ?0x10_08ff 2304 bytes 0_1001 0x10_0000 ?0x10_09ff 2560 bytes 0_1010 0x10_0000 ?0x10_0aff 2816 bytes 0_1011 0x10_0000 ?0x10_0bff 3072 bytes 0_1100 0x10_0000 ?0x10_0cff 3328 bytes 0_1101 0x10_0000 ?0x10_0dff 3584 bytes 0_1110 0x10_0000 ?0x10_0eff 3840 bytes 0_1111 0x10_0000 ?0x10_0fff 4096 bytes 1_0000 0x10_0000 ?0x10_10ff 4352 bytes 1_0001 0x10_0000 ?0x10_11ff 4608 bytes 1_0010 0x10_0000 ?0x10_12ff 4864 bytes 1_0011 0x10_0000 ?0x10_13ff 5120 bytes 1_0100 0x10_0000 ?0x10_14ff 5376 bytes 1_0101 0x10_0000 ?0x10_15ff 5632 bytes
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 591 18.3.1.11 flash common command object register (fccob) the fccob is an array of six words addressed via the ccobix index found in the fccobix register. byte wide reads and writes are allowed to the fccob register. 18.3.1.11.1 fccob - nvm command mode nvm command mode uses the indexed fccob register to provide a command code and its relevant parameters to the memory controller. the user first sets up all required fccob fields and then initiates the command? execution by writing a 1 to the ccif bit in the fstat register (a 1 written by the user clears the ccif command completion flag to 0). when the user clears the ccif bit in the fstat register all fccob parameter fields are locked and cannot be changed by the user until the command completes 1_0110 0x10_0000 ?0x10_16ff 5888 bytes 1_0111 0x10_0000 ?0x10_17ff 6144 bytes 1_1000 0x10_0000 ?0x10_18ff 6400 bytes 1_1001 0x10_0000 ?0x10_19ff 6656 bytes 1_1010 0x10_0000 ?0x10_1aff 6912 bytes 1_1011 0x10_0000 ?0x10_1bff 7168 bytes 1_1100 0x10_0000 ?0x10_1cff 7424 bytes 1_1101 0x10_0000 ?0x10_1dff 7680 bytes 1_1110 0x10_0000 ?0x10_1eff 7936 bytes 1_1111 0x10_0000 ?0x10_1fff 8192 bytes offset module base + 0x000a 76543210 r ccob[15:8] w reset 00000000 figure 18-15. flash common command object high register (fccobhi) offset module base + 0x000b 76543210 r ccob[7:0] w reset 00000000 figure 18-16. flash common command object low register (fccoblo) table 18-21. d-flash protection address range dps[4:0] global address range protected size
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 592 freescale semiconductor (as evidenced by the memory controller returning ccif to 1). some commands return information to the fccob register array. the generic format for the fccob parameter fields in nvm command mode is shown in table 18-22 . the return values are available for reading after the ccif flag in the fstat register has been returned to 1 by the memory controller. writes to the unimplemented parameter fields (ccobix = 110 and ccobix = 111) are ignored with reads from these fields returning 0x0000. table 18-22 shows the generic flash command format. the high byte of the first word in the ccob array contains the command code, followed by the parameters for this specific flash command. for details on the fccob settings required by each command, see the flash command descriptions in section 18.4.2 . 18.3.1.12 flash reserved0 register (frsv0) this flash register is reserved for factory testing. all bits in the frsv0 register read 0 and are not writable. table 18-22. fccob - nvm command mode (typical usage) ccobix[2:0] byte fccob parameter fields (nvm command mode) 000 hi fcmd[7:0] de?ing flash command lo 0, global address [22:16] 001 hi global address [15:8] lo global address [7:0] 010 hi data 0 [15:8] lo data 0 [7:0] 011 hi data 1 [15:8] lo data 1 [7:0] 100 hi data 2 [15:8] lo data 2 [7:0] 101 hi data 3 [15:8] lo data 3 [7:0] offset module base + 0x000c 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 18-17. flash reserved0 register (frsv0)
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 593 18.3.1.13 flash reserved1 register (frsv1) this flash register is reserved for factory testing. all bits in the frsv1 register read 0 and are not writable. 18.3.1.14 flash ecc error results register (feccr) the feccr registers contain the result of a detected ecc fault for both single bit and double bit faults. the feccr register provides access to several ecc related fields as defined by the eccrix index bits in the feccrix register (see section 18.3.1.4 ). once ecc fault information has been stored, no other fault information will be recorded until the specific ecc fault flag has been cleared. in the event of simultaneous ecc faults the priority for fault recording is double bit fault over single bit fault. all feccr bits are readable but not writable. offset module base + 0x000d 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 18-18. flash reserved1 register (frsv1) offset module base + 0x000e 76543210 r eccr[15:8] w reset 00000000 = unimplemented or reserved figure 18-19. flash ecc error results high register (feccrhi) offset module base + 0x000f 76543210 r eccr[7:0] w reset 00000000 = unimplemented or reserved figure 18-20. flash ecc error results low register (feccrlo)
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 594 freescale semiconductor the p-flash word addressed by eccrix = 001 contains the lower 16 bits of the global address. the following four words addressed by eccrix = 010 to 101 contain the 64-bit wide data phrase. the four data words and the parity byte are the uncorrected data read from the p-flash block. the d-flash word addressed by eccrix = 001 contains the lower 16 bits of the global address. the uncorrected 16-bit data word is addressed by eccrix = 010. 18.3.1.15 flash option register (fopt) the fopt register is the flash option register. all bits in the fopt register are readable but are not writable. table 18-23. feccr index settings eccrix[2:0] feccr register content bits [15:8] bit[7] bits[6:0] 000 parity bits read from flash block 0 global address [22:16] 001 global address [15:0] 010 data 0 [15:0] 011 data 1 [15:0] (p-flash only) 100 data 2 [15:0] (p-flash only) 101 data 3 [15:0] (p-flash only) 110 not used, returns 0x0000 when read 111 not used, returns 0x0000 when read table 18-24. feccr index=000 bit descriptions field description 15:8 par[7:0] ecc parity bits ?contains the 8 parity bits from the 72 bit wide p-flash data word or the 6 parity bits, allocated to par[5:0], from the 22 bit wide d-flash word with par[7:6]=00. 6? gaddr[22:16] global address ?the gaddr[22:16] ?ld contains the upper seven bits of the global address having caused the error. offset module base + 0x0010 76543210 r nv[7:0] w reset f f ffffff = unimplemented or reserved figure 18-21. flash option register (fopt)
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 595 during the reset sequence, the fopt register is loaded from the flash nonvolatile byte in the flash configuration field at global address 0x7f_ff0e located in p-flash memory (see table 18-2 ) as indicated by reset condition f in figure 18-21 . if a double bit fault is detected while reading the p-flash phrase containing the flash nonvolatile byte during the reset sequence, all bits in the fopt register will be set. 18.3.1.16 flash reserved2 register (frsv2) this flash register is reserved for factory testing. all bits in the frsv2 register read 0 and are not writable. 18.3.1.17 flash reserved3 register (frsv3) this flash register is reserved for factory testing. all bits in the frsv3 register read 0 and are not writable. 18.3.1.18 flash reserved4 register (frsv4) this flash register is reserved for factory testing. table 18-25. fopt field descriptions field description 7? nv[7:0] nonvolatile bits the nv[7:0] bits are available as nonvolatile bits. refer to the device user guide for proper use of the nv bits. offset module base + 0x0011 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 18-22. flash reserved2 register (frsv2) offset module base + 0x0012 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 18-23. flash reserved3 register (frsv3)
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 596 freescale semiconductor all bits in the frsv4 register read 0 and are not writable. 18.4 functional description 18.4.1 flash command operations flash command operations are used to modify flash memory contents. the next sections describe: how to write the fclkdiv register that is used to generate a time base (fclk) derived from oscclk for flash program and erase command operations the command write sequence used to set flash command parameters and launch execution valid flash commands available for execution 18.4.1.1 writing the fclkdiv register prior to issuing any flash program or erase command after a reset, the user is required to write the fclkdiv register to divide oscclk down to a target fclk of 1 mhz. table 18-5 shows recommended values for the fdiv ?ld based on oscclk frequency. note programming or erasing the flash memory cannot be performed if the bus clock runs at less than 1 mhz. setting fdiv too high can destroy the flash memory due to overstress. setting fdiv too low can result in incomplete programming or erasure of the flash memory cells. when the fclkdiv register is written, the fdivld bit is set automatically. if the fdivld bit is 0, the fclkdiv register has not been written since the last reset. if the fclkdiv register has not been written, offset module base + 0x0013 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 18-24. flash reserved4 register (frsv4)
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 597 any flash program or erase command loaded during a command write sequence will not execute and the accerr bit in the fstat register will set. 18.4.1.2 command write sequence the memory controller will launch all valid flash commands entered using a command write sequence. before launching a command, the accerr and fpviol bits in the fstat register must be clear (see section 18.3.1.7 ) and the ccif flag should be tested to determine the status of the current command write sequence. if ccif is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the fccob register are ignored. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and memory controller behavior. 18.4.1.2.1 de?e fccob contents the fccob parameter ?lds must be loaded with all required parameters for the flash command being executed. access to the fccob parameter ?lds is controlled via the ccobix bits in the fccobix register (see section 18.3.1.3 ). the contents of the fccob parameter ?lds are transferred to the memory controller when the user clears the ccif command completion ?g in the fstat register (writing 1 clears the ccif to 0). the ccif ?g will remain clear until the flash command has completed. upon completion, the memory controller will return ccif to 1 and the fccob register will be used to communicate any results. the ?w for a generic command write sequence is shown in figure 18-25 .
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 598 freescale semiconductor figure 18-25. generic flash command write sequence flowchart write to fccobix register write: fstat register (to launch command) clear ccif 0x80 clear accerr/fpviol 0x30 write: fstat register yes no access error and protection violation read: fstat register read: fstat register no start yes check ccif set? fccob accerr/ fpviol set? exit write: fclkdiv register read: fclkdiv register yes no clock register written check fdivld set? no bit polling for command completion check yes ccif set? to identify speci? command parameter to load. write to fccob register to load required command parameter. yes no more parameters? availability check results from previous command note: fclkdiv must be set after each reset
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 599 18.4.1.3 valid flash module commands 18.4.1.4 p-flash commands table 18-27 summarizes the valid p-flash commands along with the effects of the commands on the p-flash block and other resources within the flash module. table 18-26. flash commands by mode fcmd command unsecured secured ns 1 1 unsecured normal single chip mode. nx 2 2 unsecured normal expanded mode. ss 3 3 unsecured special single chip mode. st 4 4 unsecured special mode. ns 5 5 secured normal single chip mode. nx 6 6 secured normal expanded mode. ss 7 7 secured special single chip mode. st 8 8 secured special mode. 0x01 erase verify all blocks ???????? 0x02 erase verify block ???????? 0x03 erase verify p-flash section ????? 0x04 read once ????? 0x06 program p-flash ????? 0x07 program once ????? 0x08 erase all blocks ?? ?? 0x09 erase flash block ????? 0x0a erase p-flash sector ????? 0x0b unsecure flash ?? ?? 0x0c verify backdoor access key ?? 0x0d set user margin level ????? 0x0e set field margin level ?? 0x10 erase verify d-flash section ????? 0x11 program d-flash ????? 0x12 erase d-flash sector ?????
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 600 freescale semiconductor 18.4.1.5 d-flash commands table 18-28 summarizes the valid d-flash commands along with the effects of the commands on the d-flash block. table 18-27. p-flash commands fcmd command function on p-flash memory 0x01 erase verify all blocks verify that all p-flash (and d-flash) blocks are erased. 0x02 erase verify block verify that a p-flash block is erased. 0x03 erase verify p-flash section verify that a given number of words starting at the address provided are erased. 0x04 read once read a dedicated 64 byte ?ld in the nonvolatile information register in p-flash block 0 that was previously programmed using the program once command. 0x06 program p-flash program a phrase in a p-flash block. 0x07 program once program a dedicated 64 byte ?ld in the nonvolatile information register in p-flash block 0 that is allowed to be programmed only once. 0x08 erase all blocks erase all p-flash (and d-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a p-flash (or d-flash) block. an erase of the full p-flash block is only possible when fpldis, fphdis and fpopen bits in the fprot register are set prior to launching the command. 0x0a erase p-flash sector erase all bytes in a p-flash sector. 0x0b unsecure flash supports a method of releasing mcu security by erasing all p-flash (and d-flash) blocks and verifying that all p-flash (and d-flash) blocks are erased. 0x0c verify backdoor access key supports a method of releasing mcu security by verifying a set of security keys. 0x0d set user margin level speci?s a user margin read level for all p-flash blocks. 0x0e set field margin level speci?s a ?ld margin read level for all p-flash blocks (special modes only). table 18-28. d-flash commands fcmd command function on d-flash memory 0x01 erase verify all blocks verify that all d-flash (and p-flash) blocks are erased. 0x02 erase verify block verify that the d-flash block is erased. 0x08 erase all blocks erase all d-flash (and p-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a d-flash (or p-flash) block. an erase of the full d-flash block is only possible when dpopen bit in the dfprot register is set prior to launching the command.
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 601 18.4.2 flash command description this section provides details of all available flash commands launched by a command write sequence. the accerr bit in the fstat register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the memory controller: starting any command write sequence that programs or erases flash memory before initializing the fclkdiv register writing an invalid command as part of the command write sequence for additional possible errors, refer to the error handling table provided for each command if a flash block is read during execution of an algorithm (ccif = 0) on that same block, the read operation will return invalid data. if the sfdif or dfdif flags were not previously set when the invalid read operation occurred, both the sfdif and dfdif flags will be set and the feccr registers will be loaded with the global address used in the invalid read operation with the data and parity fields set to all 0. if the accerr or fpviol bits are set in the fstat register, the user must clear these bits before starting any command write sequence (see section 18.3.1.7 ). caution a flash word or phrase must be in the erased state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. 18.4.2.1 erase verify all blocks command the erase verify all blocks command will verify that all p-flash and d-flash blocks have been erased. 0x0b unsecure flash supports a method of releasing mcu security by erasing all d-flash (and p-flash) blocks and verifying that all d-flash (and p-flash) blocks are erased. 0x0d set user margin level speci?s a user margin read level for the d-flash block. 0x0e set field margin level speci?s a ?ld margin read level for the d-flash block (special modes only). 0x10 erase verify d-flash section verify that a given number of words starting at the address provided are erased. 0x11 program d-flash program up to four words in the d-flash block. 0x12 erase d-flash sector erase all bytes in a sector of the d-flash block. table 18-29. erase verify all blocks command fccob requirements ccobix[2:0] fccob parameters 000 0x01 not required table 18-28. d-flash commands fcmd command function on d-flash memory
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 602 freescale semiconductor upon clearing ccif to launch the erase verify all blocks command, the memory controller will verify that the entire flash memory space is erased. the ccif ?g will set after the erase verify all blocks operation has completed. 18.4.2.2 erase verify block command the erase verify block command allows the user to verify that an entire p-flash or d-flash block has been erased. the fccob upper global address bits determine which block must be veri?d. upon clearing ccif to launch the erase verify block command, the memory controller will verify that the selected p-flash or d-flash block is erased. the ccif ?g will set after the erase verify block operation has completed. 18.4.2.3 erase verify p-flash section command the erase verify p-flash section command will verify that a section of code in the p-flash memory is erased. the erase verify p-flash section command defines the starting point of the code to be verified and the number of phrases. the section to be verified cannot cross a 256 kbyte boundary in the p-flash memory space. table 18-30. erase verify all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 18-31. erase verify block command fccob requirements ccobix[2:0] fccob parameters 000 0x02 global address [22:16] of the flash block to be veri?d . table 18-32. erase verify block command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if an invalid global address [22:16] is supplied fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 603 upon clearing ccif to launch the erase verify p-flash section command, the memory controller will verify the selected section of flash memory is erased. the ccif ?g will set after the erase verify p-flash section operation has completed. 18.4.2.4 read once command the read once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of p-flash block 0. the read once field is programmed using the program once command described in section 18.4.2.6 . the read once command must not be executed from the flash block containing the program once reserved field to avoid code runaway. upon clearing ccif to launch the read once command, a read once phrase is fetched and stored in the fccob indexed register. the ccif ?g will set after the read once operation has completed. valid table 18-33. erase verify p-flash section command fccob requirements ccobix[2:0] fccob parameters 000 0x03 global address [22:16] of a p-flash block 001 global address [15:0] of the ?st phrase to be veri?d 010 number of phrases to be veri?d table 18-34. erase verify p-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 010 at command launch set if command not available in current mode (see table 18-26 ) set if an invalid global address [22:0] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) set if the requested section crosses a 256 kbyte boundary fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 18-35. read once command fccob requirements ccobix[2:0] fccob parameters 000 0x04 not required 001 read once phrase index (0x0000 - 0x0007) 010 read once word 0 value 011 read once word 1 value 100 read once word 2 value 101 read once word 3 value
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 604 freescale semiconductor phrase index values for the read once command range from 0x0000 to 0x0007. during execution of the read once command, any attempt to read addresses within p-flash block will return invalid data. 18.4.2.5 program p-flash command the program p-flash operation will program a previously erased phrase in the p-flash memory using an embedded algorithm. caution a p-flash phrase must be in the erased state before being programmed. cumulative programming of bits within a flash phrase is not allowed. upon clearing ccif to launch the program p-flash command, the memory controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. the ccif ?g will set after the program p-flash operation has completed. table 18-36. read once command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 18-26 ) set if an invalid phrase index is supplied fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 18-37. program p-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x06 global address [22:16] to identify p-flash block 001 global address [15:0] of phrase location to be programmed 1 1 global address [2:0] must be 000 010 word 0 program value 011 word 1 program value 100 word 2 program value 101 word 3 program value
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 605 18.4.2.6 program once command the program once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in p-flash block 0. the program once reserved field can be read using the read once command as described in section 18.4.2.4 . the program once command must only be issued once since the nonvolatile information register in p-flash block 0 cannot be erased. the program once command must not be executed from the flash block containing the program once reserved field to avoid code runaway. upon clearing ccif to launch the program once command, the memory controller ?st veri?s that the selected phrase is erased. if erased, then the selected phrase will be programmed and then veri?d with read back. the ccif ?g will remain clear, setting only after the program once operation has completed. the reserved nonvolatile information register accessed by the program once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. valid phrase index values for the program once command range from 0x0000 to 0x0007. during execution of the program once command, any attempt to read addresses within p-flash block 0 will return invalid data. table 18-38. program p-flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 101 at command launch set if command not available in current mode (see table 18-26 ) set if an invalid global address [22:0] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) fpviol set if the global address [22:0] points to a protected area mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 18-39. program once command fccob requirements ccobix[2:0] fccob parameters 000 0x07 not required 001 program once phrase index (0x0000 - 0x0007) 010 program once word 0 value 011 program once word 1 value 100 program once word 2 value 101 program once word 3 value
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 606 freescale semiconductor r, 18.4.2.7 erase all blocks command the erase all blocks operation will erase the entire p-flash and d-flash memory space. upon clearing ccif to launch the erase all blocks command, the memory controller will erase the entire flash memory space and verify that it is erased. if the memory controller veri?s that the entire flash memory space was properly erased, security will be released. during the execution of this command (ccif=0) the user must not write to any flash module register. the ccif ?g will set after the erase all blocks operation has completed. 18.4.2.8 erase flash block command the erase flash block operation will erase all addresses in a p-flash or d-flash block. table 18-40. program once command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 101 at command launch set if command not available in current mode (see table 18-26 ) set if an invalid phrase index is supplied set if the requested phrase has already been programmed 1 1 if a program once phrase is initially programmed to 0xffff_ffff_ffff_ffff, the program once command will be allowed to execute again on that same phrase. fpviol none mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 18-41. erase all blocks command fccob requirements ccobix[2:0] fccob parameters 000 0x08 not required table 18-42. erase all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if command not available in current mode (see table 18-26 ) fpviol set if any area of the p-flash or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 607 upon clearing ccif to launch the erase flash block command, the memory controller will erase the selected flash block and verify that it is erased. the ccif ?g will set after the erase flash block operation has completed. 18.4.2.9 erase p-flash sector command the erase p-flash sector operation will erase all addresses in a p-flash sector. upon clearing ccif to launch the erase p-flash sector command, the memory controller will erase the selected flash sector and then verify that it is erased. the ccif ?g will be set after the erase p-flash sector operation has completed. table 18-43. erase flash block command fccob requirements ccobix[2:0] fccob parameters 000 0x09 global address [22:16] to identify flash block 001 global address [15:0] in flash block to be erased table 18-44. erase flash block command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 18-26 ) set if an invalid global address [22:16] is supplied set if the supplied p-flash address is not phrase-aligned or if the d-flash address is not word-aligned fpviol set if an area of the selected flash block is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 18-45. erase p-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x0a global address [22:16] to identify p-flash block to be erased 001 global address [15:0] anywhere within the sector to be erased. refer to section 18.1.2.1 for the p-flash sector size.
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 608 freescale semiconductor 18.4.2.10 unsecure flash command the unsecure flash command will erase the entire p-flash and d-flash memory space and, if the erase is successful, will release security. upon clearing ccif to launch the unsecure flash command, the memory controller will erase the entire p-flash and d-flash memory space and verify that it is erased. if the memory controller veri?s that the entire flash memory space was properly erased, security will be released. if the erase verify is not successful, the unsecure flash operation sets mgstat1 and terminates without changing the security state. during the execution of this command (ccif=0) the user must not write to any flash module register. the ccif ?g is set after the unsecure flash operation has completed. 18.4.2.11 verify backdoor access key command the verify backdoor access key command will only execute if it is enabled by the keyen bits in the fsec register (see table 18-7 ). the verify backdoor access key command releases security if user-supplied keys match those stored in the flash security bytes of the flash configuration field (see table 18-46. erase p-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 18-26 ) set if an invalid global address [22:16] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) fpviol set if the selected p-flash sector is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 18-47. unsecure flash command fccob requirements ccobix[2:0] fccob parameters 000 0x0b not required table 18-48. unsecure flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if command not available in current mode (see table 18-26 ) fpviol set if any area of the p-flash or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 609 table 18-2 ). the verify backdoor access key command must not be executed from the flash block containing the backdoor comparison key to avoid code runaway. upon clearing ccif to launch the verify backdoor access key command, the memory controller will check the fsec keyen bits to verify that this command is enabled. if not enabled, the memory controller sets the accerr bit in the fstat register and terminates. if the command is enabled, the memory controller compares the key provided in fccob to the backdoor comparison key in the flash con?uration ?ld with key 0 compared to 0x7f_ff00, etc. if the backdoor keys match, security will be released. if the backdoor keys do not match, security is not released and all future attempts to execute the verify backdoor access key command are aborted (set accerr) until a reset occurs. the ccif flag is set after the verify backdoor access key operation has completed. 18.4.2.12 set user margin level command the set user margin level command causes the memory controller to set the margin level for future read operations of a specific p-flash or d-flash block. table 18-49. verify backdoor access key command fccob requirements ccobix[2:0] fccob parameters 000 0x0c not required 001 key 0 010 key 1 011 key 2 100 key 3 table 18-50. verify backdoor access key command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 100 at command launch set if an incorrect backdoor key is supplied set if backdoor key access has not been enabled (keyen[1:0] != 10, see section 18.3.1.2 ) set if the backdoor key has mismatched since the last reset fpviol none mgstat1 none mgstat0 none table 18-51. set user margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0d global address [22:16] to identify the flash block 001 margin level setting
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 610 freescale semiconductor upon clearing ccif to launch the set user margin level command, the memory controller will set the user margin level for the targeted block and then set the ccif ?g. valid margin level settings for the set user margin level command are de?ed in table 18-52 . note user margin levels can be used to check that flash memory contents have adequate margin for normal level read operations. if unexpected results are encountered when checking flash memory contents at user margin levels, a potential loss of information has been detected. 18.4.2.13 set field margin level command the set field margin level command, valid in special modes only, causes the memory controller to set the margin level specified for future read operations of a specific p-flash or d-flash block. table 18-52. valid set user margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level 1 1 read margin to the erased state 0x0002 user margin-0 level 2 2 read margin to the programmed state table 18-53. set user margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 18-26 ) set if an invalid global address [22:16] is supplied set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none table 18-54. set field margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0e global address [22:16] to identify the flash block 001 margin level setting
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 611 upon clearing ccif to launch the set field margin level command, the memory controller will set the ?ld margin level for the targeted block and then set the ccif ?g. valid margin level settings for the set field margin level command are de?ed in table 18-55 . caution field margin levels must only be used during verify of the initial factory programming. note field margin levels can be used to check that flash memory contents have adequate margin for data retention at the normal level setting. if unexpected results are encountered when checking flash memory contents at ?ld margin levels, the flash memory contents should be erased and reprogrammed. 18.4.2.14 erase verify d-flash section command the erase verify d-flash section command will verify that a section of code in the d-flash is erased. the erase verify d-flash section command defines the starting point of the data to be verified and the number of words. table 18-55. valid set field margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level 1 1 read margin to the erased state 0x0002 user margin-0 level 2 2 read margin to the programmed state 0x0003 field margin-1 level 1 0x0004 field margin-0 level 2 table 18-56. set field margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 18-26 ) set if an invalid global address [22:16] is supplied set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 612 freescale semiconductor upon clearing ccif to launch the erase verify d-flash section command, the memory controller will verify the selected section of d-flash memory is erased. the ccif ?g will set after the erase verify d-flash section operation has completed. 18.4.2.15 program d-flash command the program d-flash operation programs one to four previously erased words in the d-flash block. the program d-flash operation will confirm that the targeted location(s) were successfully programmed upon completion. caution a flash word must be in the erased state before being programmed. cumulative programming of bits within a flash word is not allowed. table 18-57. erase verify d-flash section command fccob requirements ccobix[2:0] fccob parameters 000 0x10 global address [22:16] to identify the d-flash block 001 global address [15:0] of the ?st word to be veri?d 010 number of words to be veri?d table 18-58. erase verify d-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 010 at command launch set if command not available in current mode (see table 18-26 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) set if the requested section breaches the end of the d-flash block fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 18-59. program d-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x11 global address [22:16] to identify the d-flash block 001 global address [15:0] of word to be programmed 010 word 0 program value 011 word 1 program value, if desired 100 word 2 program value, if desired
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 613 upon clearing ccif to launch the program d-flash command, the user-supplied words will be transferred to the memory controller and be programmed if the area is unprotected. the ccobix index value at program d-flash command launch determines how many words will be programmed in the d-flash block. the ccif ?g is set when the operation has completed. 18.4.2.16 erase d-flash sector command the erase d-flash sector operation will erase all addresses in a sector of the d-flash block. upon clearing ccif to launch the erase d-flash sector command, the memory controller will erase the selected flash sector and verify that it is erased. the ccif ?g will set after the erase d-flash sector operation has completed. 101 word 3 program value, if desired table 18-60. program d-flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] < 010 at command launch set if ccobix[2:0] > 101 at command launch set if command not available in current mode (see table 18-26 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) set if the requested group of words breaches the end of the d-flash block fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 18-61. erase d-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x12 global address [22:16] to identify d-flash block 001 global address [15:0] anywhere within the sector to be erased. see section 18.1.2.2 for d-flash sector size. table 18-59. program d-flash command fccob requirements ccobix[2:0] fccob parameters
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 614 freescale semiconductor 18.4.3 interrupts the flash module can generate an interrupt when a flash command operation has completed or when a flash command operation has detected an ecc fault. note vector addresses and their relative interrupt priority are determined at the mcu level. 18.4.3.1 description of flash interrupt operation the flash module uses the ccif ?g in combination with the ccie interrupt enable bit to generate the flash command interrupt request. the flash module uses the dfdif and sfdif ?gs in combination with the dfdie and sfdie interrupt enable bits to generate the flash error interrupt request. for a detailed description of the register bits involved, refer to section 18.3.1.5, ?lash configuration register (fcnfg) ? section 18.3.1.6, ?lash error configuration register (fercnfg) ? section 18.3.1.7, ?lash status register (fstat) ? and section 18.3.1.8, ?lash error status register (ferstat) ? the logic used for generating the flash module interrupts is shown in figure 18-26 . table 18-62. erase d-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 18-26 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 18-63. flash interrupt sources interrupt source interrupt flag local enable global (ccr) mask flash command complete ccif (fstat register) ccie (fcnfg register) i bit ecc double bit fault on flash read dfdif (ferstat register) dfdie (fercnfg register) i bit ecc single bit fault on flash read sfdif (ferstat register) sfdie (fercnfg register) i bit
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 615 figure 18-26. flash module interrupts implementation 18.4.4 wait mode the flash module is not affected if the mcu enters wait mode. the flash module can recover the mcu from wait via the ccif interrupt (see section 18.4.3, ?nterrupts ). 18.4.5 stop mode if a flash command is active (ccif = 0) when the mcu requests stop mode, the current flash operation will be completed before the cpu is allowed to enter stop mode. 18.5 security the flash module provides security information to the mcu. the flash security state is de?ed by the sec bits of the fsec register (see table 18-8 ). during reset, the flash module initializes the fsec register using data read from the security byte of the flash con?uration ?ld at global address 0x7f_ff0f. the security state out of reset can be permanently changed by programming the security byte of the flash con?uration ?ld. this assumes that you are starting from a mode where the necessary p-flash erase and program commands are available and that the upper region of the p-flash is unprotected. if the flash security byte is successfully programmed, its new value will take affect after the next mcu reset. the following subsections describe these security-related subjects: unsecuring the mcu using backdoor key access unsecuring the mcu in special single chip mode using bdm mode and security effects on flash command availability 18.5.1 unsecuring the mcu using backdoor key access the mcu may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7f_ff00?x7f_ff07). if the keyen[1:0] bits are in the enabled state (see section 18.3.1.2 ), the verify backdoor access key command (see section 18.4.2.11 ) allows the user to present four prospective keys for comparison to the flash error interrupt request ccif ccie dfdif dfdie sfdif sfdie flash command interrupt request
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 616 freescale semiconductor keys stored in the flash memory via the memory controller. if the keys presented in the verify backdoor access key command match the backdoor keys stored in the flash memory, the sec bits in the fsec register (see table 18-8 ) will be changed to unsecure the mcu. key values of 0x0000 and 0xffff are not permitted as backdoor keys. while the verify backdoor access key command is active, p-flash block 0 will not be available for read access and will return invalid data. the user code stored in the p-flash memory must have a method of receiving the backdoor keys from an external stimulus. this external stimulus would typically be through one of the on-chip serial ports. if the keyen[1:0] bits are in the enabled state (see section 18.3.1.2 ), the mcu can be unsecured by the backdoor key access sequence described below: 1. follow the command sequence for the verify backdoor access key command as explained in section 18.4.2.11 2. if the verify backdoor access key command is successful, the mcu is unsecured and the sec[1:0] bits in the fsec register are forced to the unsecure state of 10 the verify backdoor access key command is monitored by the memory controller and an illegal key will prohibit future use of the verify backdoor access key command. a reset of the mcu is the only method to re-enable the verify backdoor access key command. after the backdoor keys have been correctly matched, the mcu will be unsecured. after the mcu is unsecured, the sector containing the flash security byte can be erased and the flash security byte can be reprogrammed to the unsecure state, if desired. in the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x7f_ff00?x7f_ff07 in the flash con?uration ?ld. the security as de?ed in the flash security byte (0x7f_ff0f) is not changed by using the verify backdoor access key command sequence. the backdoor keys stored in addresses 0x7f_ff00?x7f_ff07 are unaffected by the verify backdoor access key command sequence. after the next reset of the mcu, the security state of the flash module is determined by the flash security byte (0x7f_ff0f). the verify backdoor access key command sequence has no effect on the program and erase protections de?ed in the flash protection register, fprot. 18.5.2 unsecuring the mcu in special single chip mode using bdm the mcu can be unsecured in special single chip mode by erasing the p-flash and d-flash memory by one of the following methods: reset the mcu into special single chip mode, delay while the erase test is performed by the bdm, send bdm commands to disable protection in the p-flash and d-flash memory, and execute the erase all blocks command write sequence to erase the p-flash and d-flash memory. reset the mcu into special expanded wide mode, disable protection in the p-flash and d-flash memory and run code from external memory to execute the erase all blocks command write sequence to erase the p-flash and d-flash memory. after the ccif ?g sets to indicate that the erase all blocks operation has completed, reset the mcu into special single chip mode. the bdm will execute the erase verify all blocks command write sequence to verify that the p-flash and d-flash memory is erased. if the p-flash and d-flash memory are verified as
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 617 erased the mcu will be unsecured. all bdm commands will be enabled and the flash security byte may be programmed to the unsecure state by the following method: send bdm commands to execute a ?rogram p-flash?command sequence to program the flash security byte to the unsecured state and reset the mcu. 18.5.3 mode and security effects on flash command availability the availability of flash module commands depends on the mcu operating mode and security state as shown in table 18-26 . 18.6 initialization on each system reset the flash module executes a reset sequence which establishes initial values for the flash block configuration parameters, the fprot and dfprot protection registers, and the fopt and fsec registers. the flash module reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. if a double bit fault is detected during the reset sequence, both mgstat bits in the fstat register will be set. ccif remains clear throughout the reset sequence. the flash module holds off all cpu access for the initial portion of the reset sequence. while flash reads are possible when the hold is removed, writes to the fccobix, fccobhi, and fccoblo registers are ignored to prevent command activity while the memory controller remains busy. completion of the reset sequence is marked by setting ccif high which enables writes to the fccobix, fccobhi, and fccoblo registers to launch any available flash command. if a reset occurs while any flash command is in progress, that command will be immediately aborted. the state of the word being programmed or the sector/block being erased is not guaranteed.
256 kbyte flash module (s12xftmr256k1v1) mc9s12xhy-family reference manual, rev. 1.01 618 freescale semiconductor
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 619 preliminary chapter 19 128 kbyte flash module (s12xftmr128k1v1) 19.1 introduction the module implements the following: kbytes of p-flash (program flash) memory kbytes of d-flash (data flash) memory the flash memory is ideal for single-supply applications allowing for ?ld reprogramming without requiring external high voltage sources for program or erase operations. the flash module includes a memory controller that executes commands to modify flash memory contents. the user interface to the memory controller consists of the indexed flash common command object (fccob) register which is written to with the command, global address, data, and any required command parameters. the memory controller must complete the execution of a command before the fccob register can be written to with a new command. caution a flash word or phrase must be in the erased state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. the flash memory may be read as bytes, aligned words, or misaligned words. read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. for flash memory, an erased bit reads 1 and a programmed bit reads 0. it is not possible to read from a flash block while any command is executing on that speci? flash block. it is possible to read from a flash block while a command is executing on a different flash block. both p-flash and d-flash memories are implemented with error correction codes (ecc) that can resolve single bit faults and detect double bit faults. for p-flash memory, the ecc implementation requires that programming be done on an aligned 8 byte basis (a flash phrase). since p-flash memory is always read by phrase, only one single bit fault in the phrase containing the byte or word accessed will be corrected. 19.1.1 glossary command write sequence ?an mcu instruction sequence to execute built-in algorithms (including program and erase) on the flash memory. d-flash memory ?the d-flash memory constitutes the nonvolatile memory store for data.
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 620 preliminary d-flash sector the d-flash sector is the smallest portion of the d-flash memory that can be erased. the d-flash sector consists of four 64 byte rows for a total of 256 bytes. nvm command mode an nvm mode using the cpu to setup the fccob register to pass parameters required for flash command execution. phrase an aligned group of four 16-bit words within the p-flash memory. each phrase includes eight ecc bits for single bit fault correction and double bit fault detection within the phrase. p-flash memory the p-flash memory constitutes the main nonvolatile memory store for applications. p-flash sector ?the p-flash sector is the smallest portion of the p-flash memory that can be erased. each p-flash sector contains 1024 bytes. program ifr ?nonvolatile information register located in the p-flash block that contains the device id, version id, and the program once ?ld. the program ifr is visible in the global memory map by setting the pgmifron bit in the mmcctl1 register. 19.1.2 features 19.1.2.1 p-flash features single bit fault correction and double bit fault detection within a 64-bit phrase during read operations automated program and erase algorithm with verify and generation of ecc parity bits fast sector erase and phrase program operation flexible protection scheme to prevent accidental program or erase of p-flash memory 19.1.2.2 d-flash features single bit fault correction and double bit fault detection within a word during read operations automated program and erase algorithm with verify and generation of ecc parity bits fast sector erase and word program operation protection scheme to prevent accidental program or erase of d-flash memory ability to program up to four words in a burst sequence 19.1.2.3 other flash module features no external high-voltage power supply required for flash memory program and erase operations interrupt generation on flash command completion and flash error detection security mechanism to prevent unauthorized access to the flash memory
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 621 19.1.3 block diagram the block diagram of the flash module is shown in . external signal description the flash module contains no signals that connect off-chip. 19.2 memory map and registers this section describes the memory map and registers for the flash module. read data from unimplemented memory space in the flash module is unde?ed. write access to unimplemented or reserved memory space in the flash module will be ignored by the flash module. oscillator clock divider clock (xtal) command interrupt request fclk protection security registers flash interface 16bit internal bus sector 0 sector 1 sector 127 16kx72 p-flash error interrupt request cpu d-flash 4kx22 sector 0 sector 1 sector 31 scratch ram 384x16bits memory controller
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 622 freescale semiconductor 19.2.1 module memory map the s12x architecture places the p-flash memory between global addresses . the p-flash memory map is shown in . the fprot register, described in section 19.2.1.9 , can be set to protect regions in the flash memory from accidental program or erase. three separate memory regions, one growing upward from global address 0x7f_8000 in the flash memory (called the lower region), one growing downward from global address 0x7f_ffff in the flash memory (called the higher region), and the remaining addresses in the flash memory, can be activated for protection. the flash memory addresses covered by these protectable regions are shown in the p-flash memory map. the higher address region is mainly targeted to hold the boot loader code since it covers the vector space. default protection settings as well as security information that allows the mcu to restrict access to the flash module are stored in the flash con?uration ?ld as described in table 19-1 . table 19-1. flash con?uration field 1 1 older versions may have swapped protection byte addresses global address size (bytes) description 0x7f_ff00 ?0x7f_ff07 8 backdoor comparison key refer to section 19.3.2.11, ?erify backdoor access key command , and section 19.4.1, ?nsecuring the mcu using backdoor key access 0x7f_ff08 0x7f_ff0b 2 2 0x7ff08 - 0x7f_ff0f form a flash phrase and must be programmed in a single command write sequence. each byte in the 0x7f_ff08 - 0x7f_ff0b reserved ?ld should be programmed to 0xff. 4 reserved 0x7f_ff0c 2 1 p-flash protection byte . refer to section 19.2.1.9, ?-flash protection register (fprot) 0x7f_ff0d 2 1 d-flash protection byte . refer to section 19.2.1.10, ?-flash protection register (dfprot) 0x7f_ff0e 2 1 flash nonvolatile byte refer to section 19.2.1.15, ?lash option register (fopt) 0x7f_ff0f 2 1 flash security byte refer to section 19.2.1.2, ?lash security register (fsec)
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 623 flash con?uration field 0x7f_c000 flash protected/unprotected lower region 1, 2, 4, 8 kbytes 0x7f_8000 0x7f_9000 0x7f_8400 0x7f_8800 0x7f_a000 p-flash end = 0x7f_ffff 0x7f_f800 0x7f_f000 0x7f_e000 flash protected/unprotected higher region 2, 4, 8, 16 kbytes flash protected/unprotected region 8 kbytes (up to 29 kbytes) 16 bytes (0x7f_ff00 - 0x7f_ff0f) flash protected/unprotected region 96 kbytes p-flash start = 0x7e_0000
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 624 freescale semiconductor register descriptions the flash module contains a set of 20 control and status registers located between flash module base + 0x0000 and 0x0013. a summary of the flash module registers is given in figure 19-1 with detailed descriptions in the following subsections. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and memory controller behavior. table 19-2. program ifr fields global address (pgmifron) size (bytes) field description 0x40_0000 ?0x40_0007 8 device id 0x40_0008 ?0x40_00e7 224 reserved 0x40_00e8 ?0x40_00e9 2 version id 0x40_00ea ?0x40_00ff 22 reserved 0x40_0100 ?0x40_013f 64 program once field refer to section 19.3.2.6, ?rogram once command 0x40_0140 ?0x40_01ff 192 reserved 0x12_ffff 0x12_4000 0x12_1000 memory controller scratch ram (mgramon) 768 bytes d-flash nonvolatile information register (dfifron) 128 bytes d-flash memory 8 kbytes d-flash start = 0x10_0000 0x12_0000 0x12_2000 0x12_e800 d-flash end = 0x10_1fff
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 625 address & name 76543210 0x0000 fclkdiv r fdivld fdiv6 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w 0x0001 fsec r keyen1 keyen0 rnv5 rnv4 rnv3 rnv2 sec1 sec0 w 0x0002 fccobix r0 0 0 0 0 ccobix2 ccobix1 ccobix0 w 0x0003 feccrix r0 0 0 0 0 eccrix2 eccrix1 eccrix0 w 0x0004 fcnfg r ccie 00 ignsf 00 fdfd fsfd w 0x0005 fercnfg r 0 dfdie sfdie w 0x0006 fstat r ccif 0 accerr fpviol mgbusy rsvd mgstat1 mgstat0 w 0x0007 ferstat r0 0 0 0 0 0 dfdif sfdif w 0x0008 fprot r fpopen rnv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 w 0x0009 dfprot r dpopen 00 dps4 dps3 dps2 dps1 dps0 w 0x000a fccobhi r ccob15 ccob14 ccob13 ccob12 ccob11 ccob10 ccob9 ccob8 w 0x000b fccoblo r ccob7 ccob6 ccob5 ccob4 ccob3 ccob2 ccob1 ccob0 w 0x000c frsv0 r00000000 w 0x000d frsv1 r00000000 w figure 19-1. ftmr128k1 register summary
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 626 freescale semiconductor 19.2.1.1 flash clock divider register (fclkdiv) the fclkdiv register is used to control timed events in program and erase algorithms. all bits in the fclkdiv register are readable, bits 6? are write once and bit 7 is not writable. 0x000e feccrhi r eccr15 eccr14 eccr13 eccr12 eccr11 eccr10 eccr9 eccr8 w 0x000f feccrlo r eccr7 eccr6 eccr5 eccr4 eccr3 eccr2 eccr1 eccr0 w 0x0010 fopt r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w 0x0011 frsv2 r00000000 w 0x0012 frsv3 r00000000 w 0x0013 frsv4 r00000000 w = unimplemented or reserved offset module base + 0x0000 76543210 r fdivld fdiv[6:0] w reset 00000000 = unimplemented or reserved figure 19-2. flash clock divider register (fclkdiv) address & name 76543210 figure 19-1. ftmr128k1 register summary (continued)
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 627 caution the fclkdiv register should never be written while a flash command is executing (ccif=0). the fclkdiv register is writable during the flash reset sequence even though ccif is clear. table 19-3. fclkdiv field descriptions field description 7 fdivld clock divider loaded 0 fclkdiv register has not been written 1 fclkdiv register has been written since the last reset 6? fdiv[6:0] clock divider bits ?fdiv[6:0] must be set to effectively divide oscclk down to generate an internal flash clock, fclk, with a target frequency of 1 mhz for use by the flash module to control timed events during program and erase algorithms. table 19-4 shows recommended values for fdiv[6:0] based on oscclk frequency. please refer to section 19.3.1, ?lash command operations , for more information.
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 628 freescale semiconductor table 19-4. fdiv vs oscclk frequency oscclk frequency (mhz) fdiv[6:0] oscclk frequency (mhz) fdiv[6:0] min 1 1 fdiv shown generates an fclk frequency of >0.8 mhz max 2 2 fdiv shown generates an fclk frequency of 1.05 mhz min 1 max 2 1.60 2.10 0x01 33.60 34.65 0x20 2.40 3.15 0x02 34.65 35.70 0x21 3.20 4.20 0x03 35.70 36.75 0x22 4.20 5.25 0x04 36.75 37.80 0x23 5.25 6.30 0x05 37.80 38.85 0x24 6.30 7.35 0x06 38.85 39.90 0x25 7.35 8.40 0x07 39.90 40.95 0x26 8.40 9.45 0x08 40.95 42.00 0x27 9.45 10.50 0x09 42.00 43.05 0x28 10.50 11.55 0x0a 43.05 44.10 0x29 11.55 12.60 0x0b 44.10 45.15 0x2a 12.60 13.65 0x0c 45.15 46.20 0x2b 13.65 14.70 0x0d 46.20 47.25 0x2c 14.70 15.75 0x0e 47.25 48.30 0x2d 15.75 16.80 0x0f 48.30 49.35 0x2e 16.80 17.85 0x10 49.35 50.40 0x2f 17.85 18.90 0x11 18.90 19.95 0x12 19.95 21.00 0x13 21.00 22.05 0x14 22.05 23.10 0x15 23.10 24.15 0x16 24.15 25.20 0x17 25.20 26.25 0x18 26.25 27.30 0x19 27.30 28.35 0x1a 28.35 29.40 0x1b 29.40 30.45 0x1c 30.45 31.50 0x1d 31.50 32.55 0x1e 32.55 33.60 0x1f
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 629 19.2.1.2 flash security register (fsec) the fsec register holds all bits associated with the security of the mcu and flash module. all bits in the fsec register are readable but not writable. during the reset sequence, the fsec register is loaded with the contents of the flash security byte in the flash configuration field at global address 0x7f_ff0f located in p-flash memory (see table 19-1 ) as indicated by reset condition f in figure 19-3 . if a double bit fault is detected while reading the p-flash phrase containing the flash security byte during the reset sequence, all bits in the fsec register will be set to leave the flash module in a secured state with backdoor key access disabled. offset module base + 0x0001 76543210 r keyen[1:0] rnv[5:2] sec[1:0] w reset f f ffffff = unimplemented or reserved figure 19-3. flash security register (fsec) table 19-5. fsec field descriptions field description 7? keyen[1:0] backdoor key security enable bits the keyen[1:0] bits de?e the enabling of backdoor key access to the flash module as shown in table 19-6 . 5? rnv[5:2} reserved nonvolatile bits ?the rnv bits should remain in the erased state for future enhancements. 1? sec[1:0] flash security bits ?the sec[1:0] bits de?e the security state of the mcu as shown in table 19-7 . if the flash module is unsecured using backdoor key access, the sec bits are forced to 10. table 19-6. flash keyen states keyen[1:0] status of backdoor key access 00 disabled 01 disabled 1 1 preferred keyen state to disable backdoor key access. 10 enabled 11 disabled table 19-7. flash security states sec[1:0] status of security 00 secured 01 secured 1 10 unsecured 11 secured
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 630 freescale semiconductor the security function in the flash module is described in section 19.4 . 19.2.1.3 flash ccob index register (fccobix) the fccobix register is used to index the fccob register for flash memory operations. ccobix bits are readable and writable while remaining bits read 0 and are not writable. 19.2.1.4 flash eccr index register (feccrix) the feccrix register is used to index the feccr register for ecc fault reporting. eccrix bits are readable and writable while remaining bits read 0 and are not writable. 1 preferred sec state to set mcu to secured state. offset module base + 0x0002 76543210 r00000 ccobix[2:0] w reset 00000000 = unimplemented or reserved figure 19-4. fccob index register (fccobix) table 19-8. fccobix field descriptions field description 2? ccobix[1:0] common command register index the ccobix bits are used to select which word of the fccob register array is being read or written to. see section 19.2.1.11, ?lash common command object register (fccob) , for more details. offset module base + 0x0003 76543210 r00000 eccrix[2:0] w reset 00000000 = unimplemented or reserved figure 19-5. feccr index register (feccrix) table 19-9. feccrix field descriptions field description 2-0 eccrix[2:0] ecc error register index ?the eccrix bits are used to select which word of the feccr register array is being read. see section 19.2.1.14, ?lash ecc error results register (feccr) , for more details.
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 631 19.2.1.5 flash con?uration register (fcnfg) the fcnfg register enables the flash command complete interrupt and forces ecc faults on flash array read access from the cpu or xgate. ccie, ignsf, fdfd, and fsfd bits are readable and writable while remaining bits read 0 and are not writable. 19.2.1.6 flash error con?uration register (fercnfg) the fercnfg register enables the flash error interrupts for the ferstat flags. offset module base + 0x0004 76543210 r ccie 00 ignsf 00 fdfd fsfd w reset 00000000 = unimplemented or reserved figure 19-6. flash con?uration register (fcnfg) table 19-10. fcnfg field descriptions field description 7 ccie command complete interrupt enable ?the ccie bit controls interrupt generation when a flash command has completed. 0 command complete interrupt disabled 1 an interrupt will be requested whenever the ccif ?g in the fstat register is set (see section 19.2.1.7 ) 4 ignsf ignore single bit fault ?the ignsf controls single bit fault reporting in the ferstat register (see section 19.2.1.8 ). 0 all single bit faults detected during array reads are reported 1 single bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated 1 fdfd force double bit fault detect the fdfd bit allows the user to simulate a double bit fault during flash array read operations and check the associated interrupt routine. the fdfd bit is cleared by writing a 0 to fdfd. the feccr registers will not be updated during the flash array read operation with fdfd set unless an actual double bit fault is detected. 0 flash array read operations will set the dfdif ?g in the ferstat register only if a double bit fault is detected 1 any flash array read operation will force the dfdif ?g in the ferstat register to be set (see section 19.2.1.7 ) and an interrupt will be generated as long as the dfdie interrupt enable in the fercnfg register is set (see section 19.2.1.6 ) 0 fsfd force single bit fault detect the fsfd bit allows the user to simulate a single bit fault during flash array read operations and check the associated interrupt routine. the fsfd bit is cleared by writing a 0 to fsfd. the feccr registers will not be updated during the flash array read operation with fsfd set unless an actual single bit fault is detected. 0 flash array read operations will set the sfdif ?g in the ferstat register only if a single bit fault is detected 1 flash array read operation will force the sfdif ?g in the ferstat register to be set (see section 19.2.1.7 ) and an interrupt will be generated as long as the sfdie interrupt enable in the fercnfg register is set (see section 19.2.1.6 )
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 632 freescale semiconductor all assigned bits in the fercnfg register are readable and writable. 19.2.1.7 flash status register (fstat) the fstat register reports the operational status of the flash module. ccif, accerr, and fpviol bits are readable and writable, mgbusy and mgstat bits are readable but not writable, while remaining bits read 0 and are not writable. offset module base + 0x0005 76543210 r 0 dfdie sfdie w reset 00000000 = unimplemented or reserved figure 19-7. flash error con?uration register (fercnfg) table 19-11. fercnfg field descriptions field description 1 dfdie double bit fault detect interrupt enable the dfdie bit controls interrupt generation when a double bit fault is detected during a flash block read operation. 0 dfdif interrupt disabled 1 an interrupt will be requested whenever the dfdif ?g is set (see section 19.2.1.8 ) 0 sfdie single bit fault detect interrupt enable the sfdie bit controls interrupt generation when a single bit fault is detected during a flash block read operation. 0 sfdif interrupt disabled whenever the sfdif ?g is set (see section 19.2.1.8 ) 1 an interrupt will be requested whenever the sfdif ?g is set (see section 19.2.1.8 ) offset module base + 0x0006 76543210 r ccif 0 accerr fpviol mgbusy rsvd mgstat[1:0] w reset 1000000 1 1 reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see section 19.5 ). 0 1 = unimplemented or reserved figure 19-8. flash status register (fstat)
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 633 19.2.1.8 flash error status register (ferstat) the ferstat register re?cts the error status of internal flash operations. all ?gs in the ferstat register are readable and only writable to clear the ?g. table 19-12. fstat field descriptions field description 7 ccif command complete interrupt flag ?the ccif ?g indicates that a flash command has completed. the ccif ?g is cleared by writing a 1 to ccif to launch a command and ccif will stay low until command completion or command violation. 0 flash command in progress 1 flash command has completed 5 accerr flash access error flag ?the accerr bit indicates an illegal access has occurred to the flash memory caused by either a violation of the command write sequence (see section 19.3.1.2 ) or issuing an illegal flash command. while accerr is set, the ccif ?g cannot be cleared to launch a command. the accerr bit is cleared by writing a 1 to accerr. writing a 0 to the accerr bit has no effect on accerr. 0 no access error detected 1 access error detected 4 fpviol flash protection violation flag ?he fpviol bit indicates an attempt was made to program or erase an address in a protected area of p-flash or d-flash memory during a command write sequence. the fpviol bit is cleared by writing a 1 to fpviol. writing a 0 to the fpviol bit has no effect on fpviol. while fpviol is set, it is not possible to launch a command or start a command write sequence. 0 no protection violation detected 1 protection violation detected 3 mgbusy memory controller busy flag ?the mgbusy ?g re?cts the active state of the memory controller . 0 memory controller is idle 1 memory controller is busy executing a flash command (ccif = 0) 2 rsvd reserved bit ?this bit is reserved and always reads 0 . 1? mgstat[1:0] memory controller command completion status flag one or more mgstat ?g bits are set if an error is detected during execution of a flash command or during the flash reset sequence. see section 19.3.2, ?lash command description , and section 19.5, ?nitialization ?for details. offset module base + 0x0007 76543210 r000000 dfdif sfdif w reset 00000000 = unimplemented or reserved figure 19-9. flash error status register (ferstat)
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 634 freescale semiconductor 19.2.1.9 p-flash protection register (fprot) the fprot register defines which p-flash sectors are protected against program and erase operations. the (unreserved) bits of the fprot register are writable with the restriction that the size of the protected region can only be increased (see section 19.2.1.9.1, ?-flash protection restrictions , and table 19-18 ). during the reset sequence, the fprot register is loaded with the contents of the p-flash protection byte in the flash configuration field at global address 0x7f_ff0c located in p-flash memory (see table 19-1 ) as indicated by reset condition ??in figure 19-10 . to change the p-flash protection that will be loaded during the reset sequence, the upper sector of the p-flash memory must be unprotected, then the p-flash protection byte must be reprogrammed. if a double bit fault is detected while reading the p-flash phrase containing the p-flash protection byte during the reset sequence, the fpopen bit will be cleared and remaining bits in the fprot register will be set to leave the p-flash memory fully protected. trying to alter data in any protected area in the p-flash memory will result in a protection violation error and the fpviol bit will be set in the fstat register. the block erase of a p-flash block is not possible if any of the p-flash sectors contained in the same p-flash block are protected. table 19-13. ferstat field descriptions field description 1 dfdif double bit fault detect interrupt flag ?the setting of the dfdif ?g indicates that a double bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation was attempted on a flash block that was under a flash command operation. the dfdif ?g is cleared by writing a 1 to dfdif. writing a 0 to dfdif has no effect on dfdif. 0 no double bit fault detected 1 double bit fault detected or an invalid flash array read operation attempted 0 sfdif single bit fault detect interrupt flag ?with the ignsf bit in the fcnfg register clear, the sfdif ?g indicates that a single bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation was attempted on a flash block that was under a flash command operation. the sfdif ?g is cleared by writing a 1 to sfdif. writing a 0 to sfdif has no effect on sfdif. 0 no single bit fault detected 1 single bit fault detected and corrected or an invalid flash array read operation attempted offset module base + 0x0008 76543210 r fpopen rnv6 fphdis fphs[1:0] fpldis fpls[1:0] w reset f f ffffff = unimplemented or reserved figure 19-10. flash protection register (fprot)
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 635 table 19-14. fprot field descriptions field description 7 fpopen flash protection operation enable ?the fpopen bit determines the protection function for program or erase operations as shown in table 19-15 for the p-flash block. 0 when fpopen is clear, the fphdis and fpldis bits de?e unprotected address ranges as speci?d by the corresponding fphs and fpls bits 1 when fpopen is set, the fphdis and fpldis bits enable protection for the address range speci?d by the corresponding fphs and fpls bits 6 rnv[6] reserved nonvolatile bit ?the rnv bit should remain in the erased state for future enhancements. 5 fphdis flash protection higher address range disable ?the fphdis bit determines whether there is a protected/unprotected area in a speci? region of the p-flash memory ending with global address 0x7f_ffff. 0 protection/unprotection enabled 1 protection/unprotection disabled 4? fphs[1:0] flash protection higher address size the fphs bits determine the size of the protected/unprotected area in p-flash memory as shown in table 19-16 . the fphs bits can only be written to while the fphdis bit is set. 2 fpldis flash protection lower address range disable ?the fpldis bit determines whether there is a protected/unprotected area in a speci? region of the p-flash memory beginning with global address 0x7f_8000. 0 protection/unprotection enabled 1 protection/unprotection disabled 1? fpls[1:0] flash protection lower address size the fpls bits determine the size of the protected/unprotected area in p-flash memory as shown in table 19-17 . the fpls bits can only be written to while the fpldis bit is set. table 19-15. p-flash protection function fpopen fphdis fpldis function 1 1 for range sizes, refer to table 19-16 and table 19-17 . 1 1 1 no p-flash protection 1 1 0 protected low range 1 0 1 protected high range 1 0 0 protected high and low ranges 0 1 1 full p-flash memory protected 0 1 0 unprotected low range 0 0 1 unprotected high range 0 0 0 unprotected high and low ranges table 19-16. p-flash protection higher address range fphs[1:0] global address range protected size 00 0x7f_f800?x7f_ffff 2 kbytes 01 0x7f_f000?x7f_ffff 4 kbytes 10 0x7f_e000?x7f_ffff 8 kbytes 11 0x7f_c000?x7f_ffff 16 kbytes
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 636 freescale semiconductor all possible p-flash protection scenarios are shown in figure 19-11 . although the protection scheme is loaded from the flash memory at global address 0x7f_ff0c during the reset sequence, it can be changed by the user. the p-flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required. table 19-17. p-flash protection lower address range fpls[1:0] global address range protected size 00 0x7f_8000?x7f_83ff 1 kbyte 01 0x7f_8000?x7f_87ff 2 kbytes 10 0x7f_8000?x7f_8fff 4 kbytes 11 0x7f_8000?x7f_9fff 8 kbytes
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 637 figure 19-11. p-flash protection scenarios 7 6 5 4 fphs[1:0] fpls[1:0] 3 2 1 0 fphs[1:0] fpls[1:0] fphdis = 1 fpldis = 1 fphdis = 1 fpldis = 0 fphdis = 0 fpldis = 1 fphdis = 0 fpldis = 0 scenario scenario unprotected region protected region with size protected region protected region with size defined by fpls defined by fphs not defined by fpls, fphs 0x7f_8000 0x7f_ffff 0x7f_8000 0x7f_ffff flash start flash start fpopen = 1 fpopen = 0
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 638 freescale semiconductor 19.2.1.9.1 p-flash protection restrictions the general guideline is that p-flash protection can only be added and not removed. table 19-18 specifies all valid transitions between p-flash protection scenarios. any attempt to write an invalid scenario to the fprot register will be ignored. the contents of the fprot register reflect the active protection scenario. see the fphs and fpls bit descriptions for additional restrictions. 19.2.1.10 d-flash protection register (dfprot) the dfprot register de?es which d-flash sectors are protected against program and erase operations. the (unreserved) bits of the dfprot register are writable with the restriction that protection can be added but not removed. writes must increase the dps value and the dpoen bit can only be written from 1 (protection disabled) to 0 (protection enabled). if the dpopen bit is set, the state of the dps bits is irrelevant. during the reset sequence, the dfprot register is loaded with the contents of the d-flash protection byte in the flash configuration field at global address 0x7f_ff0d located in p-flash memory (see table 19-1 ) as indicated by reset condition f in figure 19-12 . to change the d-flash protection that will be loaded during the reset sequence, the p-flash sector containing the d-flash protection byte must be unprotected, then the d-flash protection byte must be programmed. if a double bit fault is detected while reading the table 19-18. p-flash protection scenario transitions from protection scenario to protection scenario 1 1 allowed transitions marked with x, see figure 19-11 for a de?ition of the scenarios. 01234567 0 xxxx 1 xx 2 xx 3 x 4 xx 5 xxxx 6 xxxx 7 xxxxxxxx offset module base + 0x0009 76543210 r dpopen 00 dps[4:0] w reset f 0 0 fffff = unimplemented or reserved figure 19-12. d-flash protection register (dfprot)
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 639 p-flash phrase containing the d-flash protection byte during the reset sequence, the dpopen bit will be cleared and dps bits will be set to leave the d-flash memory fully protected. trying to alter data in any protected area in the d-flash memory will result in a protection violation error and the fpviol bit will be set in the fstat register. block erase of the d-flash memory is not possible if any of the d-flash sectors are protected. table 19-19. dfprot field descriptions field description 7 dpopen d-flash protection control 0 enables d-flash memory protection from program and erase with protected address range de?ed by dps bits 1 disables d-flash memory protection from program and erase 4? dps[4:0] d-flash protection size the dps[4:0] bits determine the size of the protected area in the d-flash memory as shown in table 19-20 . table 19-20. d-flash protection address range dps[4:0] global address range protected size 0_0000 0x10_0000 ?0x10_00ff 256 bytes 0_0001 0x10_0000 ?0x10_01ff 512 bytes 0_0010 0x10_0000 ?0x10_02ff 768 bytes 0_0011 0x10_0000 ?0x10_03ff 1024 bytes 0_0100 0x10_0000 ?0x10_04ff 1280 bytes 0_0101 0x10_0000 ?0x10_05ff 1536 bytes 0_0110 0x10_0000 ?0x10_06ff 1792 bytes 0_0111 0x10_0000 ?0x10_07ff 2048 bytes 0_1000 0x10_0000 ?0x10_08ff 2304 bytes 0_1001 0x10_0000 ?0x10_09ff 2560 bytes 0_1010 0x10_0000 ?0x10_0aff 2816 bytes 0_1011 0x10_0000 ?0x10_0bff 3072 bytes 0_1100 0x10_0000 ?0x10_0cff 3328 bytes 0_1101 0x10_0000 ?0x10_0dff 3584 bytes 0_1110 0x10_0000 ?0x10_0eff 3840 bytes 0_1111 0x10_0000 ?0x10_0fff 4096 bytes 1_0000 0x10_0000 ?0x10_10ff 4352 bytes 1_0001 0x10_0000 ?0x10_11ff 4608 bytes 1_0010 0x10_0000 ?0x10_12ff 4864 bytes 1_0011 0x10_0000 ?0x10_13ff 5120 bytes 1_0100 0x10_0000 ?0x10_14ff 5376 bytes 1_0101 0x10_0000 ?0x10_15ff 5632 bytes
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 640 freescale semiconductor 19.2.1.11 flash common command object register (fccob) the fccob is an array of six words addressed via the ccobix index found in the fccobix register. byte wide reads and writes are allowed to the fccob register. 19.2.1.11.1 fccob - nvm command mode nvm command mode uses the indexed fccob register to provide a command code and its relevant parameters to the memory controller. the user first sets up all required fccob fields and then initiates the command? execution by writing a 1 to the ccif bit in the fstat register (a 1 written by the user clears the ccif command completion flag to 0). when the user clears the ccif bit in the fstat register all fccob parameter fields are locked and cannot be changed by the user until the command completes 1_0110 0x10_0000 ?0x10_16ff 5888 bytes 1_0111 0x10_0000 ?0x10_17ff 6144 bytes 1_1000 0x10_0000 ?0x10_18ff 6400 bytes 1_1001 0x10_0000 ?0x10_19ff 6656 bytes 1_1010 0x10_0000 ?0x10_1aff 6912 bytes 1_1011 0x10_0000 ?0x10_1bff 7168 bytes 1_1100 0x10_0000 ?0x10_1cff 7424 bytes 1_1101 0x10_0000 ?0x10_1dff 7680 bytes 1_1110 0x10_0000 ?0x10_1eff 7936 bytes 1_1111 0x10_0000 ?0x10_1fff 8192 bytes offset module base + 0x000a 76543210 r ccob[15:8] w reset 00000000 figure 19-13. flash common command object high register (fccobhi) offset module base + 0x000b 76543210 r ccob[7:0] w reset 00000000 figure 19-14. flash common command object low register (fccoblo) table 19-20. d-flash protection address range dps[4:0] global address range protected size
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 641 (as evidenced by the memory controller returning ccif to 1). some commands return information to the fccob register array. the generic format for the fccob parameter fields in nvm command mode is shown in table 19-21 . the return values are available for reading after the ccif flag in the fstat register has been returned to 1 by the memory controller. writes to the unimplemented parameter fields (ccobix = 110 and ccobix = 111) are ignored with reads from these fields returning 0x0000. table 19-21 shows the generic flash command format. the high byte of the first word in the ccob array contains the command code, followed by the parameters for this specific flash command. for details on the fccob settings required by each command, see the flash command descriptions in section 19.3.2 . 19.2.1.12 flash reserved0 register (frsv0) this flash register is reserved for factory testing. all bits in the frsv0 register read 0 and are not writable. table 19-21. fccob - nvm command mode (typical usage) ccobix[2:0] byte fccob parameter fields (nvm command mode) 000 hi fcmd[7:0] de?ing flash command lo 0, global address [22:16] 001 hi global address [15:8] lo global address [7:0] 010 hi data 0 [15:8] lo data 0 [7:0] 011 hi data 1 [15:8] lo data 1 [7:0] 100 hi data 2 [15:8] lo data 2 [7:0] 101 hi data 3 [15:8] lo data 3 [7:0] offset module base + 0x000c 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 19-15. flash reserved0 register (frsv0)
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 642 freescale semiconductor 19.2.1.13 flash reserved1 register (frsv1) this flash register is reserved for factory testing. all bits in the frsv1 register read 0 and are not writable. 19.2.1.14 flash ecc error results register (feccr) the feccr registers contain the result of a detected ecc fault for both single bit and double bit faults. the feccr register provides access to several ecc related fields as defined by the eccrix index bits in the feccrix register (see section 19.2.1.4 ). once ecc fault information has been stored, no other fault information will be recorded until the specific ecc fault flag has been cleared. in the event of simultaneous ecc faults the priority for fault recording is double bit fault over single bit fault. all feccr bits are readable but not writable. offset module base + 0x000d 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 19-16. flash reserved1 register (frsv1) offset module base + 0x000e 76543210 r eccr[15:8] w reset 00000000 = unimplemented or reserved figure 19-17. flash ecc error results high register (feccrhi) offset module base + 0x000f 76543210 r eccr[7:0] w reset 00000000 = unimplemented or reserved figure 19-18. flash ecc error results low register (feccrlo)
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 643 the p-flash word addressed by eccrix = 001 contains the lower 16 bits of the global address. the following four words addressed by eccrix = 010 to 101 contain the 64-bit wide data phrase. the four data words and the parity byte are the uncorrected data read from the p-flash block. the d-flash word addressed by eccrix = 001 contains the lower 16 bits of the global address. the uncorrected 16-bit data word is addressed by eccrix = 010. 19.2.1.15 flash option register (fopt) the fopt register is the flash option register. all bits in the fopt register are readable but are not writable. table 19-22. feccr index settings eccrix[2:0] feccr register content bits [15:8] bit[7] bits[6:0] 000 parity bits read from flash block 0 global address [22:16] 001 global address [15:0] 010 data 0 [15:0] 011 data 1 [15:0] (p-flash only) 100 data 2 [15:0] (p-flash only) 101 data 3 [15:0] (p-flash only) 110 not used, returns 0x0000 when read 111 not used, returns 0x0000 when read table 19-23. feccr index=000 bit descriptions field description 15:8 par[7:0] ecc parity bits ?contains the 8 parity bits from the 72 bit wide p-flash data word or the 6 parity bits, allocated to par[5:0], from the 22 bit wide d-flash word with par[7:6]=00. 6? gaddr[22:16] global address ?the gaddr[22:16] ?ld contains the upper seven bits of the global address having caused the error. offset module base + 0x0010 76543210 r nv[7:0] w reset f f ffffff = unimplemented or reserved figure 19-19. flash option register (fopt)
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 644 freescale semiconductor during the reset sequence, the fopt register is loaded from the flash nonvolatile byte in the flash configuration field at global address 0x7f_ff0e located in p-flash memory (see table 19-1 ) as indicated by reset condition f in figure 19-19 . if a double bit fault is detected while reading the p-flash phrase containing the flash nonvolatile byte during the reset sequence, all bits in the fopt register will be set. 19.2.1.16 flash reserved2 register (frsv2) this flash register is reserved for factory testing. all bits in the frsv2 register read 0 and are not writable. 19.2.1.17 flash reserved3 register (frsv3) this flash register is reserved for factory testing. all bits in the frsv3 register read 0 and are not writable. 19.2.1.18 flash reserved4 register (frsv4) this flash register is reserved for factory testing. table 19-24. fopt field descriptions field description 7? nv[7:0] nonvolatile bits the nv[7:0] bits are available as nonvolatile bits. refer to the device user guide for proper use of the nv bits. offset module base + 0x0011 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 19-20. flash reserved2 register (frsv2) offset module base + 0x0012 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 19-21. flash reserved3 register (frsv3)
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 645 all bits in the frsv4 register read 0 and are not writable. 19.3 functional description 19.3.1 flash command operations flash command operations are used to modify flash memory contents. the next sections describe: how to write the fclkdiv register that is used to generate a time base (fclk) derived from oscclk for flash program and erase command operations the command write sequence used to set flash command parameters and launch execution valid flash commands available for execution 19.3.1.1 writing the fclkdiv register prior to issuing any flash program or erase command after a reset, the user is required to write the fclkdiv register to divide oscclk down to a target fclk of 1 mhz. table 19-4 shows recommended values for the fdiv ?ld based on oscclk frequency. note programming or erasing the flash memory cannot be performed if the bus clock runs at less than 1 mhz. setting fdiv too high can destroy the flash memory due to overstress. setting fdiv too low can result in incomplete programming or erasure of the flash memory cells. when the fclkdiv register is written, the fdivld bit is set automatically. if the fdivld bit is 0, the fclkdiv register has not been written since the last reset. if the fclkdiv register has not been written, offset module base + 0x0013 76543210 r00000000 w reset 00000000 = unimplemented or reserved figure 19-22. flash reserved4 register (frsv4)
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 646 freescale semiconductor any flash program or erase command loaded during a command write sequence will not execute and the accerr bit in the fstat register will set. 19.3.1.2 command write sequence the memory controller will launch all valid flash commands entered using a command write sequence. before launching a command, the accerr and fpviol bits in the fstat register must be clear (see section 19.2.1.7 ) and the ccif flag should be tested to determine the status of the current command write sequence. if ccif is 0, the previous command write sequence is still active, a new command write sequence cannot be started, and all writes to the fccob register are ignored. caution writes to any flash register must be avoided while a flash command is active (ccif=0) to prevent corruption of flash register contents and memory controller behavior. 19.3.1.2.1 de?e fccob contents the fccob parameter ?lds must be loaded with all required parameters for the flash command being executed. access to the fccob parameter ?lds is controlled via the ccobix bits in the fccobix register (see section 19.2.1.3 ). the contents of the fccob parameter ?lds are transferred to the memory controller when the user clears the ccif command completion ?g in the fstat register (writing 1 clears the ccif to 0). the ccif ?g will remain clear until the flash command has completed. upon completion, the memory controller will return ccif to 1 and the fccob register will be used to communicate any results. the ?w for a generic command write sequence is shown in figure 19-23 .
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 647 figure 19-23. generic flash command write sequence flowchart write to fccobix register write: fstat register (to launch command) clear ccif 0x80 clear accerr/fpviol 0x30 write: fstat register yes no access error and protection violation read: fstat register read: fstat register no start yes check ccif set? fccob accerr/ fpviol set? exit write: fclkdiv register read: fclkdiv register yes no clock register written check fdivld set? no bit polling for command completion check yes ccif set? to identify speci? command parameter to load. write to fccob register to load required command parameter. yes no more parameters? availability check results from previous command note: fclkdiv must be set after each reset
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 648 freescale semiconductor 19.3.1.3 valid flash module commands 19.3.1.4 p-flash commands table 19-26 summarizes the valid p-flash commands along with the effects of the commands on the p-flash block and other resources within the flash module. table 19-25. flash commands by mode fcmd command unsecured secured ns 1 1 unsecured normal single chip mode. nx 2 2 unsecured normal expanded mode. ss 3 3 unsecured special single chip mode. st 4 4 unsecured special mode. ns 5 5 secured normal single chip mode. nx 6 6 secured normal expanded mode. ss 7 7 secured special single chip mode. st 8 8 secured special mode. 0x01 erase verify all blocks ???????? 0x02 erase verify block ???????? 0x03 erase verify p-flash section ????? 0x04 read once ????? 0x06 program p-flash ????? 0x07 program once ????? 0x08 erase all blocks ?? ?? 0x09 erase flash block ????? 0x0a erase p-flash sector ????? 0x0b unsecure flash ?? ?? 0x0c verify backdoor access key ?? 0x0d set user margin level ????? 0x0e set field margin level ?? 0x10 erase verify d-flash section ????? 0x11 program d-flash ????? 0x12 erase d-flash sector ?????
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 649 19.3.1.5 d-flash commands table 19-27 summarizes the valid d-flash commands along with the effects of the commands on the d-flash block. table 19-26. p-flash commands fcmd command function on p-flash memory 0x01 erase verify all blocks verify that all p-flash (and d-flash) blocks are erased. 0x02 erase verify block verify that a p-flash block is erased. 0x03 erase verify p-flash section verify that a given number of words starting at the address provided are erased. 0x04 read once read a dedicated 64 byte ?ld in the nonvolatile information register in p-flash block 0 that was previously programmed using the program once command. 0x06 program p-flash program a phrase in a p-flash block. 0x07 program once program a dedicated 64 byte ?ld in the nonvolatile information register in p-flash block 0 that is allowed to be programmed only once. 0x08 erase all blocks erase all p-flash (and d-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a p-flash (or d-flash) block. an erase of the full p-flash block is only possible when fpldis, fphdis and fpopen bits in the fprot register are set prior to launching the command. 0x0a erase p-flash sector erase all bytes in a p-flash sector. 0x0b unsecure flash supports a method of releasing mcu security by erasing all p-flash (and d-flash) blocks and verifying that all p-flash (and d-flash) blocks are erased. 0x0c verify backdoor access key supports a method of releasing mcu security by verifying a set of security keys. 0x0d set user margin level speci?s a user margin read level for all p-flash blocks. 0x0e set field margin level speci?s a ?ld margin read level for all p-flash blocks (special modes only). table 19-27. d-flash commands fcmd command function on d-flash memory 0x01 erase verify all blocks verify that all d-flash (and p-flash) blocks are erased. 0x02 erase verify block verify that the d-flash block is erased. 0x08 erase all blocks erase all d-flash (and p-flash) blocks. an erase of all flash blocks is only possible when the fpldis, fphdis, and fpopen bits in the fprot register and the dpopen bit in the dfprot register are set prior to launching the command. 0x09 erase flash block erase a d-flash (or p-flash) block. an erase of the full d-flash block is only possible when dpopen bit in the dfprot register is set prior to launching the command.
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 650 freescale semiconductor 19.3.2 flash command description this section provides details of all available flash commands launched by a command write sequence. the accerr bit in the fstat register will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the memory controller: starting any command write sequence that programs or erases flash memory before initializing the fclkdiv register writing an invalid command as part of the command write sequence for additional possible errors, refer to the error handling table provided for each command if a flash block is read during execution of an algorithm (ccif = 0) on that same block, the read operation will return invalid data. if the sfdif or dfdif flags were not previously set when the invalid read operation occurred, both the sfdif and dfdif flags will be set and the feccr registers will be loaded with the global address used in the invalid read operation with the data and parity fields set to all 0. if the accerr or fpviol bits are set in the fstat register, the user must clear these bits before starting any command write sequence (see section 19.2.1.7 ). caution a flash word or phrase must be in the erased state before being programmed. cumulative programming of bits within a flash word or phrase is not allowed. 19.3.2.1 erase verify all blocks command the erase verify all blocks command will verify that all p-flash and d-flash blocks have been erased. 0x0b unsecure flash supports a method of releasing mcu security by erasing all d-flash (and p-flash) blocks and verifying that all d-flash (and p-flash) blocks are erased. 0x0d set user margin level speci?s a user margin read level for the d-flash block. 0x0e set field margin level speci?s a ?ld margin read level for the d-flash block (special modes only). 0x10 erase verify d-flash section verify that a given number of words starting at the address provided are erased. 0x11 program d-flash program up to four words in the d-flash block. 0x12 erase d-flash sector erase all bytes in a sector of the d-flash block. table 19-28. erase verify all blocks command fccob requirements ccobix[2:0] fccob parameters 000 0x01 not required table 19-27. d-flash commands fcmd command function on d-flash memory
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 651 upon clearing ccif to launch the erase verify all blocks command, the memory controller will verify that the entire flash memory space is erased. the ccif ?g will set after the erase verify all blocks operation has completed. 19.3.2.2 erase verify block command the erase verify block command allows the user to verify that an entire p-flash or d-flash block has been erased. the fccob upper global address bits determine which block must be veri?d. upon clearing ccif to launch the erase verify block command, the memory controller will verify that the selected p-flash or d-flash block is erased. the ccif ?g will set after the erase verify block operation has completed. 19.3.2.3 erase verify p-flash section command the erase verify p-flash section command will verify that a section of code in the p-flash memory is erased. the erase verify p-flash section command defines the starting point of the code to be verified and the number of phrases. the section to be verified cannot cross a kbyte boundary in the p-flash memory space. table 19-29. erase verify all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 19-30. erase verify block command fccob requirements ccobix[2:0] fccob parameters 000 0x02 global address [22:16] of the flash block to be veri?d . table 19-31. erase verify block command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if an invalid global address [22:16] is supplied fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 652 freescale semiconductor upon clearing ccif to launch the erase verify p-flash section command, the memory controller will verify the selected section of flash memory is erased. the ccif ?g will set after the erase verify p-flash section operation has completed. 19.3.2.4 read once command the read once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of p-flash block 0. the read once field is programmed using the program once command described in section 19.3.2.6 . the read once command must not be executed from the flash block containing the program once reserved field to avoid code runaway. upon clearing ccif to launch the read once command, a read once phrase is fetched and stored in the fccob indexed register. the ccif ?g will set after the read once operation has completed. valid table 19-32. erase verify p-flash section command fccob requirements ccobix[2:0] fccob parameters 000 0x03 global address [22:16] of a p-flash block 001 global address [15:0] of the ?st phrase to be veri?d 010 number of phrases to be veri?d table 19-33. erase verify p-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 010 at command launch set if command not available in current mode (see table 19-25 ) set if an invalid global address [22:0] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) set if the requested section crosses a kbyte boundary fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 19-34. read once command fccob requirements ccobix[2:0] fccob parameters 000 0x04 not required 001 read once phrase index (0x0000 - 0x0007) 010 read once word 0 value 011 read once word 1 value 100 read once word 2 value 101 read once word 3 value
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 653 phrase index values for the read once command range from 0x0000 to 0x0007. during execution of the read once command, any attempt to read addresses within p-flash block will return invalid data. 19.3.2.5 program p-flash command the program p-flash operation will program a previously erased phrase in the p-flash memory using an embedded algorithm. caution a p-flash phrase must be in the erased state before being programmed. cumulative programming of bits within a flash phrase is not allowed. upon clearing ccif to launch the program p-flash command, the memory controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. the ccif ?g will set after the program p-flash operation has completed. table 19-35. read once command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 19-25 ) set if an invalid phrase index is supplied fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 19-36. program p-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x06 global address [22:16] to identify p-flash block 001 global address [15:0] of phrase location to be programmed 1 1 global address [2:0] must be 000 010 word 0 program value 011 word 1 program value 100 word 2 program value 101 word 3 program value
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 654 freescale semiconductor 19.3.2.6 program once command the program once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in p-flash block 0. the program once reserved field can be read using the read once command as described in section 19.3.2.4 . the program once command must only be issued once since the nonvolatile information register in p-flash block 0 cannot be erased. the program once command must not be executed from the flash block containing the program once reserved field to avoid code runaway. upon clearing ccif to launch the program once command, the memory controller ?st veri?s that the selected phrase is erased. if erased, then the selected phrase will be programmed and then veri?d with read back. the ccif ?g will remain clear, setting only after the program once operation has completed. the reserved nonvolatile information register accessed by the program once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. valid phrase index values for the program once command range from 0x0000 to 0x0007. during execution of the program once command, any attempt to read addresses within p-flash block 0 will return invalid data. table 19-37. program p-flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 101 at command launch set if command not available in current mode (see table 19-25 ) set if an invalid global address [22:0] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) fpviol set if the global address [22:0] points to a protected area mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 19-38. program once command fccob requirements ccobix[2:0] fccob parameters 000 0x07 not required 001 program once phrase index (0x0000 - 0x0007) 010 program once word 0 value 011 program once word 1 value 100 program once word 2 value 101 program once word 3 value
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 655 r, 19.3.2.7 erase all blocks command the erase all blocks operation will erase the entire p-flash and d-flash memory space. upon clearing ccif to launch the erase all blocks command, the memory controller will erase the entire flash memory space and verify that it is erased. if the memory controller veri?s that the entire flash memory space was properly erased, security will be released. during the execution of this command (ccif=0) the user must not write to any flash module register. the ccif ?g will set after the erase all blocks operation has completed. 19.3.2.8 erase flash block command the erase flash block operation will erase all addresses in a p-flash or d-flash block. table 19-39. program once command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 101 at command launch set if command not available in current mode (see table 19-25 ) set if an invalid phrase index is supplied set if the requested phrase has already been programmed 1 1 if a program once phrase is initially programmed to 0xffff_ffff_ffff_ffff, the program once command will be allowed to execute again on that same phrase. fpviol none mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 19-40. erase all blocks command fccob requirements ccobix[2:0] fccob parameters 000 0x08 not required table 19-41. erase all blocks command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if command not available in current mode (see table 19-25 ) fpviol set if any area of the p-flash or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 656 freescale semiconductor upon clearing ccif to launch the erase flash block command, the memory controller will erase the selected flash block and verify that it is erased. the ccif ?g will set after the erase flash block operation has completed. 19.3.2.9 erase p-flash sector command the erase p-flash sector operation will erase all addresses in a p-flash sector. upon clearing ccif to launch the erase p-flash sector command, the memory controller will erase the selected flash sector and then verify that it is erased. the ccif ?g will be set after the erase p-flash sector operation has completed. table 19-42. erase flash block command fccob requirements ccobix[2:0] fccob parameters 000 0x09 global address [22:16] to identify flash block 001 global address [15:0] in flash block to be erased table 19-43. erase flash block command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 19-25 ) set if an invalid global address [22:16] is supplied set if the supplied p-flash address is not phrase-aligned or if the d-flash address is not word-aligned fpviol set if an area of the selected flash block is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 19-44. erase p-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x0a global address [22:16] to identify p-flash block to be erased 001 global address [15:0] anywhere within the sector to be erased. refer to section 19.1.2.1 for the p-flash sector size.
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 657 19.3.2.10 unsecure flash command the unsecure flash command will erase the entire p-flash and d-flash memory space and, if the erase is successful, will release security. upon clearing ccif to launch the unsecure flash command, the memory controller will erase the entire p-flash and d-flash memory space and verify that it is erased. if the memory controller veri?s that the entire flash memory space was properly erased, security will be released. if the erase verify is not successful, the unsecure flash operation sets mgstat1 and terminates without changing the security state. during the execution of this command (ccif=0) the user must not write to any flash module register. the ccif ?g is set after the unsecure flash operation has completed. 19.3.2.11 verify backdoor access key command the verify backdoor access key command will only execute if it is enabled by the keyen bits in the fsec register (see table 19-6 ). the verify backdoor access key command releases security if user-supplied keys match those stored in the flash security bytes of the flash configuration field (see table 19-45. erase p-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 19-25 ) set if an invalid global address [22:16] is supplied set if a misaligned phrase address is supplied (global address [2:0] != 000) fpviol set if the selected p-flash sector is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 19-46. unsecure flash command fccob requirements ccobix[2:0] fccob parameters 000 0x0b not required table 19-47. unsecure flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 000 at command launch set if command not available in current mode (see table 19-25 ) fpviol set if any area of the p-flash or d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 658 freescale semiconductor table 19-1 ). the verify backdoor access key command must not be executed from the flash block containing the backdoor comparison key to avoid code runaway. upon clearing ccif to launch the verify backdoor access key command, the memory controller will check the fsec keyen bits to verify that this command is enabled. if not enabled, the memory controller sets the accerr bit in the fstat register and terminates. if the command is enabled, the memory controller compares the key provided in fccob to the backdoor comparison key in the flash con?uration ?ld with key 0 compared to 0x7f_ff00, etc. if the backdoor keys match, security will be released. if the backdoor keys do not match, security is not released and all future attempts to execute the verify backdoor access key command are aborted (set accerr) until a reset occurs. the ccif flag is set after the verify backdoor access key operation has completed. 19.3.2.12 set user margin level command the set user margin level command causes the memory controller to set the margin level for future read operations of a specific p-flash or d-flash block. table 19-48. verify backdoor access key command fccob requirements ccobix[2:0] fccob parameters 000 0x0c not required 001 key 0 010 key 1 011 key 2 100 key 3 table 19-49. verify backdoor access key command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 100 at command launch set if an incorrect backdoor key is supplied set if backdoor key access has not been enabled (keyen[1:0] != 10, see section 19.2.1.2 ) set if the backdoor key has mismatched since the last reset fpviol none mgstat1 none mgstat0 none table 19-50. set user margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0d global address [22:16] to identify the flash block 001 margin level setting
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 659 upon clearing ccif to launch the set user margin level command, the memory controller will set the user margin level for the targeted block and then set the ccif ?g. valid margin level settings for the set user margin level command are de?ed in table 19-51 . note user margin levels can be used to check that flash memory contents have adequate margin for normal level read operations. if unexpected results are encountered when checking flash memory contents at user margin levels, a potential loss of information has been detected. 19.3.2.13 set field margin level command the set field margin level command, valid in special modes only, causes the memory controller to set the margin level specified for future read operations of a specific p-flash or d-flash block. table 19-51. valid set user margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level 1 1 read margin to the erased state 0x0002 user margin-0 level 2 2 read margin to the programmed state table 19-52. set user margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 19-25 ) set if an invalid global address [22:16] is supplied set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none table 19-53. set field margin level command fccob requirements ccobix[2:0] fccob parameters 000 0x0e global address [22:16] to identify the flash block 001 margin level setting
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 660 freescale semiconductor upon clearing ccif to launch the set field margin level command, the memory controller will set the ?ld margin level for the targeted block and then set the ccif ?g. valid margin level settings for the set field margin level command are de?ed in table 19-54 . caution field margin levels must only be used during verify of the initial factory programming. note field margin levels can be used to check that flash memory contents have adequate margin for data retention at the normal level setting. if unexpected results are encountered when checking flash memory contents at ?ld margin levels, the flash memory contents should be erased and reprogrammed. 19.3.2.14 erase verify d-flash section command the erase verify d-flash section command will verify that a section of code in the d-flash is erased. the erase verify d-flash section command defines the starting point of the data to be verified and the number of words. table 19-54. valid set field margin level settings ccob (ccobix=001) level description 0x0000 return to normal level 0x0001 user margin-1 level 1 1 read margin to the erased state 0x0002 user margin-0 level 2 2 read margin to the programmed state 0x0003 field margin-1 level 1 0x0004 field margin-0 level 2 table 19-55. set field margin level command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 19-25 ) set if an invalid global address [22:16] is supplied set if an invalid margin level setting is supplied fpviol none mgstat1 none mgstat0 none
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 661 upon clearing ccif to launch the erase verify d-flash section command, the memory controller will verify the selected section of d-flash memory is erased. the ccif ?g will set after the erase verify d-flash section operation has completed. 19.3.2.15 program d-flash command the program d-flash operation programs one to four previously erased words in the d-flash block. the program d-flash operation will confirm that the targeted location(s) were successfully programmed upon completion. caution a flash word must be in the erased state before being programmed. cumulative programming of bits within a flash word is not allowed. table 19-56. erase verify d-flash section command fccob requirements ccobix[2:0] fccob parameters 000 0x10 global address [22:16] to identify the d-flash block 001 global address [15:0] of the ?st word to be veri?d 010 number of words to be veri?d table 19-57. erase verify d-flash section command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 010 at command launch set if command not available in current mode (see table 19-25 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) set if the requested section breaches the end of the d-flash block fpviol none mgstat1 set if any errors have been encountered during the read mgstat0 set if any non-correctable errors have been encountered during the read table 19-58. program d-flash command fccob requirements ccobix[2:0] fccob parameters 000 0x11 global address [22:16] to identify the d-flash block 001 global address [15:0] of word to be programmed 010 word 0 program value 011 word 1 program value, if desired 100 word 2 program value, if desired
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 662 freescale semiconductor upon clearing ccif to launch the program d-flash command, the user-supplied words will be transferred to the memory controller and be programmed if the area is unprotected. the ccobix index value at program d-flash command launch determines how many words will be programmed in the d-flash block. the ccif ?g is set when the operation has completed. 19.3.2.16 erase d-flash sector command the erase d-flash sector operation will erase all addresses in a sector of the d-flash block. upon clearing ccif to launch the erase d-flash sector command, the memory controller will erase the selected flash sector and verify that it is erased. the ccif ?g will set after the erase d-flash sector operation has completed. 101 word 3 program value, if desired table 19-59. program d-flash command error handling register error bit error condition fstat accerr set if ccobix[2:0] < 010 at command launch set if ccobix[2:0] > 101 at command launch set if command not available in current mode (see table 19-25 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) set if the requested group of words breaches the end of the d-flash block fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 19-60. erase d-flash sector command fccob requirements ccobix[2:0] fccob parameters 000 0x12 global address [22:16] to identify d-flash block 001 global address [15:0] anywhere within the sector to be erased. see section 19.1.2.2 for d-flash sector size. table 19-58. program d-flash command fccob requirements ccobix[2:0] fccob parameters
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 663 19.3.3 interrupts the flash module can generate an interrupt when a flash command operation has completed or when a flash command operation has detected an ecc fault. note vector addresses and their relative interrupt priority are determined at the mcu level. 19.3.3.1 description of flash interrupt operation the flash module uses the ccif ?g in combination with the ccie interrupt enable bit to generate the flash command interrupt request. the flash module uses the dfdif and sfdif ?gs in combination with the dfdie and sfdie interrupt enable bits to generate the flash error interrupt request. for a detailed description of the register bits involved, refer to section 19.2.1.5, ?lash configuration register (fcnfg) ? section 19.2.1.6, ?lash error configuration register (fercnfg) ? section 19.2.1.7, ?lash status register (fstat) ? and section 19.2.1.8, ?lash error status register (ferstat) ? the logic used for generating the flash module interrupts is shown in figure 19-24 . table 19-61. erase d-flash sector command error handling register error bit error condition fstat accerr set if ccobix[2:0] != 001 at command launch set if command not available in current mode (see table 19-25 ) set if an invalid global address [22:0] is supplied set if a misaligned word address is supplied (global address [0] != 0) fpviol set if the selected area of the d-flash memory is protected mgstat1 set if any errors have been encountered during the verify operation mgstat0 set if any non-correctable errors have been encountered during the verify operation table 19-62. flash interrupt sources interrupt source interrupt flag local enable global (ccr) mask flash command complete ccif (fstat register) ccie (fcnfg register) i bit ecc double bit fault on flash read dfdif (ferstat register) dfdie (fercnfg register) i bit ecc single bit fault on flash read sfdif (ferstat register) sfdie (fercnfg register) i bit
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 664 freescale semiconductor figure 19-24. flash module interrupts implementation 19.3.4 wait mode the flash module is not affected if the mcu enters wait mode. the flash module can recover the mcu from wait via the ccif interrupt (see section 19.3.3, ?nterrupts ). 19.3.5 stop mode if a flash command is active (ccif = 0) when the mcu requests stop mode, the current flash operation will be completed before the cpu is allowed to enter stop mode. 19.4 security the flash module provides security information to the mcu. the flash security state is de?ed by the sec bits of the fsec register (see table 19-7 ). during reset, the flash module initializes the fsec register using data read from the security byte of the flash con?uration ?ld at global address 0x7f_ff0f. the security state out of reset can be permanently changed by programming the security byte of the flash con?uration ?ld. this assumes that you are starting from a mode where the necessary p-flash erase and program commands are available and that the upper region of the p-flash is unprotected. if the flash security byte is successfully programmed, its new value will take affect after the next mcu reset. the following subsections describe these security-related subjects: unsecuring the mcu using backdoor key access unsecuring the mcu in special single chip mode using bdm mode and security effects on flash command availability 19.4.1 unsecuring the mcu using backdoor key access the mcu may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7f_ff00?x7f_ff07). if the keyen[1:0] bits are in the enabled state (see section 19.2.1.2 ), the verify backdoor access key command (see section 19.3.2.11 ) allows the user to present four prospective keys for comparison to the flash error interrupt request ccif ccie dfdif dfdie sfdif sfdie flash command interrupt request
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 665 keys stored in the flash memory via the memory controller. if the keys presented in the verify backdoor access key command match the backdoor keys stored in the flash memory, the sec bits in the fsec register (see table 19-7 ) will be changed to unsecure the mcu. key values of 0x0000 and 0xffff are not permitted as backdoor keys. while the verify backdoor access key command is active, p-flash block 0 will not be available for read access and will return invalid data. the user code stored in the p-flash memory must have a method of receiving the backdoor keys from an external stimulus. this external stimulus would typically be through one of the on-chip serial ports. if the keyen[1:0] bits are in the enabled state (see section 19.2.1.2 ), the mcu can be unsecured by the backdoor key access sequence described below: 1. follow the command sequence for the verify backdoor access key command as explained in section 19.3.2.11 2. if the verify backdoor access key command is successful, the mcu is unsecured and the sec[1:0] bits in the fsec register are forced to the unsecure state of 10 the verify backdoor access key command is monitored by the memory controller and an illegal key will prohibit future use of the verify backdoor access key command. a reset of the mcu is the only method to re-enable the verify backdoor access key command. after the backdoor keys have been correctly matched, the mcu will be unsecured. after the mcu is unsecured, the sector containing the flash security byte can be erased and the flash security byte can be reprogrammed to the unsecure state, if desired. in the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x7f_ff00?x7f_ff07 in the flash con?uration ?ld. the security as de?ed in the flash security byte (0x7f_ff0f) is not changed by using the verify backdoor access key command sequence. the backdoor keys stored in addresses 0x7f_ff00?x7f_ff07 are unaffected by the verify backdoor access key command sequence. after the next reset of the mcu, the security state of the flash module is determined by the flash security byte (0x7f_ff0f). the verify backdoor access key command sequence has no effect on the program and erase protections de?ed in the flash protection register, fprot. 19.4.2 unsecuring the mcu in special single chip mode using bdm the mcu can be unsecured in special single chip mode by erasing the p-flash and d-flash memory by one of the following methods: reset the mcu into special single chip mode, delay while the erase test is performed by the bdm, send bdm commands to disable protection in the p-flash and d-flash memory, and execute the erase all blocks command write sequence to erase the p-flash and d-flash memory. reset the mcu into special expanded wide mode, disable protection in the p-flash and d-flash memory and run code from external memory to execute the erase all blocks command write sequence to erase the p-flash and d-flash memory. after the ccif ?g sets to indicate that the erase all blocks operation has completed, reset the mcu into special single chip mode. the bdm will execute the erase verify all blocks command write sequence to verify that the p-flash and d-flash memory is erased. if the p-flash and d-flash memory are verified as
128 kbyte flash module (s12xftmr128k1v1) mc9s12xhy-family reference manual, rev. 1.01 666 freescale semiconductor erased the mcu will be unsecured. all bdm commands will be enabled and the flash security byte may be programmed to the unsecure state by the following method: send bdm commands to execute a ?rogram p-flash?command sequence to program the flash security byte to the unsecured state and reset the mcu. 19.4.3 mode and security effects on flash command availability the availability of flash module commands depends on the mcu operating mode and security state as shown in table 19-25 . 19.5 initialization on each system reset the flash module executes a reset sequence which establishes initial values for the flash block configuration parameters, the fprot and dfprot protection registers, and the fopt and fsec registers. the flash module reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. if a double bit fault is detected during the reset sequence, both mgstat bits in the fstat register will be set. ccif remains clear throughout the reset sequence. the flash module holds off all cpu access for the initial portion of the reset sequence. while flash reads are possible when the hold is removed, writes to the fccobix, fccobhi, and fccoblo registers are ignored to prevent command activity while the memory controller remains busy. completion of the reset sequence is marked by setting ccif high which enables writes to the fccobix, fccobhi, and fccoblo registers to launch any available flash command. if a reset occurs while any flash command is in progress, that command will be immediately aborted. the state of the word being programmed or the sector/block being erased is not guaranteed.
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 667 chapter 20 motor controller (mc10b8cv1) table 20-1. revision history 20.1 introduction the block mc10b8c is a pwm motor controller suitable to drive instruments in a cluster configuration or any other loads requiring a pwm signal. the motor controller has eight pwm channels associated with two pins each (16 pins in total). 20.1.1 features the mc10b8c includes the following features: 10/11-bit pwm counter 11-bit resolution with selectable pwm dithering function 7-bit resolution mode (fast mode): duty cycle can be changed by accessing only 1 byte/output left, right, or center aligned pwm output slew rate control this module is suited for, but not limited to, driving small stepper and air core motors used in instrumentation applications. this module can be used for other motor control or pwm applications that match the frequency, resolution, and output drive capabilities of the module. 20.1.2 modes of operation 20.1.2.1 functional modes 20.1.2.1.1 pwm resolution the motor controller can be configured to either 11- or 7-bits resolution mode by clearing or setting the fast bit. this bit influences all pwm channels. for details, please refer to section 20.3.2.5, ?otor controller duty cycle registers . version number revision date author description of changes 6-oct-2009 table 20-12 - ?ed 2nd content row : mncyp := pwm - ?ed 4th content row : mncyp := 0
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 668 freescale semiconductor 20.1.2.1.2 dither function dither function can be selected or deselected by setting or clearing the dith bit. this bit influences all pwm channels. for details, please refer to section 20.4.1.3.5, ?ither bit (dith) . 20.1.2.2 pwm channel con?uration modes the eight pwm channels can operate in three functional modes. those modes are, with some restrictions, selectable for each channel independently. 20.1.2.2.1 dual full h-bridge mode this mode is suitable to drive a stepper motor or a 360 o air gauge instrument. for details, please refer to section 20.4.1.1.1, ?ual full h-bridge mode (mcom = 11) . in this mode two adjacent pwm channels are combined, and two pwm channels drive four pins. 20.1.2.2.2 full h-bridge mode this mode is suitable to drive any load requiring a pwm signal in a h-bridge configuration using two pins. for details please refer to section 20.4.1.1.2, ?ull h-bridge mode (mcom = 10) . 20.1.2.2.3 half h-bridge mode this mode is suitable to drive a 90 o instrument driven by one pin. for details, please refer to section 20.4.1.1.3, ?alf h-bridge mode (mcom = 00 or 01) . 20.1.2.3 pwm alignment modes each pwm channel can operate independently in three different alignment modes. for details, please refer to section 20.4.1.3.1, ?wm alignment modes . 20.1.2.4 low-power modes the behavior of the motor controller in low-power modes is programmable. for details, please refer to section 20.4.5, ?peration in wait mode and section 20.4.6, ?peration in stop and pseudo-stop modes .
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 669 20.1.3 block diagram figure 20-1. mc10b8c block diagram period register 11-bit timer/counter duty register 0 comparator m0c0m m0c0p duty register 1 comparator m0c1m m0c1p duty register 2 comparator m1c0m m1c0p duty register 3 comparator m1c1m m1c1p duty register 4 comparator m2c0m m2c0p duty register 5 comparator m2c1m m2c1p duty register 6 comparator m3c0m m3c0p duty register 7 comparator m3c1m m3c1p control registers fast dith 11 pwm channel pair pwm channel
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 670 freescale semiconductor 20.2 external signal description the motor controller is associated with 16 pins. table 20-2 lists the relationship between the pwm channels and signal pins as well as pwm channel pair (motor number), coils, and nodes they are supposed to drive if all channels are set to dual full h-bridge configuration. 20.2.1 m0c0m/m0c0p/m0c1m/m0c1p ?pwm output pins for motor 0 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 0. pwm output on m0c0m results in a positive current flow through coil 0 when m0c0p is driven to a logic high state. pwm output on m0c1m results in a positive current flow through coil 1 when m0c1p is driven to a logic high state. 20.2.2 m1c0m/m1c0p/m1c1m/m1c1p ?pwm output pins for motor 1 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 1. pwm output on m1c0m results in a positive current flow through coil 0 when m1c0p is driven to a logic high state. pwm output on m1c1m results in a positive current flow through coil 1 when m1c1p is driven to a logic high state. 20.2.3 m2c0m/m2c0p/m2c1m/m2c1p ?pwm output pins for motor 2 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 2. pwm output on m2c0m results in a positive current flow through coil 0 when m2c0p is driven table 20-2. pwm channel and pin assignment pin name pwm channel pwm channel pair 1 1 a pwm channel pair always consists of pwm channel x and pwm channel x+1 (x = 2 ? n). the term ?wm channel pair?is equivalent to the term ?otor? e.g. channel pair 0 is equivalent to motor 0 coil node m0c0m 0 0 0 minus m0c0p plus m0c1m 1 1 minus m0c1p plus m1c0m 2 1 0 minus m1c0p plus m1c1m 3 1 minus m1c1p plus m2c0m 4 2 0 minus m2c0p plus m2c1m 5 1 minus m2c1p plus m3c0m 6 3 0 minus m3c0p plus m3c1m 7 1 minus m3c1p plus
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 671 to a logic high state. pwm output on m2c1m results in a positive current flow through coil 1 when m2c1p is driven to a logic high state. 20.2.4 m3c0m/m3c0p/m3c1m/m3c1p ?pwm output pins for motor 3 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 3. pwm output on m3c0m results in a positive current flow through coil 0 when m3c0p is driven to a logic high state. pwm output on m3c1m results in a positive current flow through coil 1 when m3c1p is driven to a logic high state. 20.3 memory map and register de?ition this section provides a detailed description of all registers of the 10-bit 8-channel motor controller module. 20.3.1 module memory map figure 20-2 shows the memory map of the 10-bit 8-channel motor controller module. figure 20-2. mc10b8c memory map offset register access 0x0000 motor controller control register 0 (mcctl0) rw 0x0001 motor controller control register 1 (mcctl1) rw 0x0002 motor controller period register (high byte) rw 0x0003 motor controller period register (low byte) rw 0x0004 reserved 1 0x0005 reserved 0x0006 reserved 0x0007 reserved 0x0008 reserved 0x0009 reserved 0x000a reserved 0x000b reserved 0x000c reserved 0x000d reserved 0x000e reserved 0x000f reserved 0x0010 motor controller channel control register 0 (mccc0) rw 0x0011 motor controller channel control register 1 (mccc1) rw 0x0012 motor controller channel control register 2 (mccc2) rw 0x0013 motor controller channel control register 3 (mccc3) rw 0x0014 motor controller channel control register 4 (mccc4) rw 0x0015 motor controller channel control register 5 (mccc5) rw
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 672 freescale semiconductor 0x0016 motor controller channel control register 6 (mccc6) rw 0x0017 motor controller channel control register 7 (mccc7) rw 0x0018 reserved 0x0019 reserved 0x001a reserved 0x001b reserved 0x001c reserved 0x001d reserved 0x001e reserved 0x001f reserved 0x0020 motor controller duty cycle register 0 (mcdc0) ?high byte rw 0x0021 motor controller duty cycle register 0 (mcdc0) ?low byte rw 0x0022 motor controller duty cycle register 1 (mcdc1) ?high byte rw 0x0023 motor controller duty cycle register 1 (mcdc1) ?low byte rw 0x0024 motor controller duty cycle register 2 (mcdc2) ?high byte rw 0x0025 motor controller duty cycle register 2 (mcdc2) ?low byte rw 0x0026 motor controller duty cycle register 3 (mcdc3) ?high byte rw 0x0027 motor controller duty cycle register 3 (mcdc3) ?low byte rw 0x0028 motor controller duty cycle register 4 (mcdc4) ?high byte rw 0x0029 motor controller duty cycle register 4 (mcdc4) ?low byte rw 0x002a motor controller duty cycle register 5 (mcdc5) ?high byte rw 0x002b motor controller duty cycle register 5 (mcdc5) ?low byte rw 0x002c motor controller duty cycle register 6 (mcdc6) ?high byte rw 0x002d motor controller duty cycle register 6 (mcdc6) ?low byte rw 0x002e motor controller duty cycle register 7 (mcdc7) ?high byte rw 0x002f motor controller duty cycle register 7 (mcdc7) ?low byte rw 0x0030 reserved 0x0031 reserved 0x0032 reserved 0x0033 reserved 0x0034 reserved 0x0035 reserved 0x0036 reserved 0x0037 reserved 0x0038 reserved 0x0039 reserved 0x003a reserved 0x003b reserved 0x003c reserved 0x003d reserved figure 20-2. mc10b8c memory map (continued) offset register access
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 673 20.3.2 register descriptions 20.3.2.1 motor controller control register 0 this register controls the operating mode of the motor controller module. 0x003e reserved 0x003f reserved 1 write accesses to ?eserved addresses have no effect. read accesses to ?eserved addresses provide invalid data (0x0000). offset module base + 0x0000 76543210 r0 mcpre[1:0] mcswai fast dith 0 mctoif w reset 00000000 = unimplemented or reserved figure 20-3. motor controller control register 0 (mcctl0) table 20-3. mcctl0 field descriptions field description 6:5 mcpre[1:0] motor controller prescaler select mcpre1 and mcpre0 determine the prescaler value that sets the motor controller timer counter clock frequency (f tc ). the clock source for the prescaler is the peripheral bus clock (f bus ) as shown in figure 20-22 . writes to mcpre1 or mcpre0 will not affect the timer counter clock frequency f tc until the start of the next pwm period. table 20-4 shows the prescaler values that result from the possible combinations of mcpre1 and mcpre0 4 mcswai motor controller module stop in wait mode 0 entering wait mode has no effect on the motor controller module and the associated port pins maintain the functionality they had prior to entering wait mode both during wait mode and after exiting wait mode. 1 entering wait mode will stop the clock of the module and debias the analog circuitry. the module will release the pins. 3 fast motor controller pwm resolution mode 0 pwm operates in 11-bit resolution mode, duty cycle registers of all channels are switched to word mode. 1 pwm operates in 7-bit resolution (fast) mode, duty cycle registers of all channels are switched to byte mode. 2 dith motor control/driver dither feature enable (refer to section 20.4.1.3.5, ?ither bit (dith) ) 0 dither feature is disabled. 1 dither feature is enabled. 0 mctoif motor controller timer counter over?w interrupt flag ?this bit is set when a motor controller timer counter over?w occurs. the bit is cleared by writing a 1 to the bit. 0 a motor controller timer counter over?w has not occurred since the last reset or since the bit was cleared. 1 a motor controller timer counter over?w has occurred. figure 20-2. mc10b8c memory map (continued) offset register access
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 674 freescale semiconductor . 20.3.2.2 motor controller control register 1 this register controls the behavior of the analog section of the motor controller as well as the interrupt enables. table 20-4. prescaler values mcpre[1:0] f tc 00 f bus 01 f bus /2 10 f bus /4 11 f bus /8 offset module base + 0x0001 76543210 r recirc 000000 mctoie w reset 00000000 = unimplemented or reserved figure 20-4. motor controller control register 1 (mcctl1) table 20-5. mcctl1 field descriptions field description 7 recirc recirculation in (dual) full h-bridge mode (refer to section 20.4.1.3.3, ?ecirc bit ) recirc only affects the outputs in (dual) full h-bridge modes. in half h-bridge mode, the pwm output is always active low. recirc = 1 will also invert the effect of the s bits (refer to section 20.4.1.3.2, ?ign bit (s) ) in (dual) full h-bridge modes. recirc must be changed only while no pwm channel is operating in (dual) full h-bridge mode; otherwise, erroneous output pattern may occur. 0 recirculation on the high side transistors. active state for pwm output is logic low, the static channel will output logic high. 1 recirculation on the low side transistors. active state for pwm output is logic high, the static channel will output logic low. 0 mctoie motor controller timer counter over?w interrupt enable 0 interrupt disabled. 1 interrupt enabled. an interrupt will be generated when the motor controller timer counter over?w interrupt ?g (mctoif) is set.
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 675 20.3.2.3 motor controller period register the period register defines per, the number of motor controller timer counter clocks a pwm period lasts. the motor controller timer counter is clocked with the frequency f tc . if dither mode is enabled (dith = 1, refer to section 20.4.1.3.5, ?ither bit (dith) ), p0 is ignored and reads as a 0. in this case per = 2 * d[10:1]. for example, programming mcper to 0x0022 (per = 34 decimal) will result in 34 counts for each complete pwm period. setting mcper to 0 will shut off all pwm channels as if mcam[1:0] is set to 0 in all channel control registers after the next period timer counter over?w. in this case, the motor controller releases all pins. note programming mcper to 0x0001 and setting the dith bit will be managed as if mcper is programmed to 0x0000. all pwm channels will be shut off after the next period timer counter over?w. offset module base + 0x0002, 0x0003 1514131211109876543210 r00000 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 20-5. motor controller period register (mcper) with dith = 0 offset module base + 0x0002, 0x0003 1514131211109876543210 r00000 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 0 w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 20-6. motor controller period register (mcper) with dith = 1
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 676 freescale semiconductor 20.3.2.4 motor controller channel control registers each pwm channel has one associated control register to control output delay, pwm alignment, and output mode. the registers are named mccc0... mccc7. in the following, mccc0 is described as a reference for all eight registers. offset module base + 0x0010 . . . 0x0017 76543210 r mcom1 mcom0 mcam1 mcam0 00 cd1 cd0 w reset 00000000 = unimplemented or reserved figure 20-7. motor controller control register channel 0? (mccc0?ccc7) table 20-6. mccc0?ccc7 field descriptions field description 7:6 mcom[1:0] output mode mcom1, mcom0 control the pwm channels output mode. see table 20-7 . 5:4 mcam[1:0] pwm channel alignment mode mcam1, mcam0 control the pwm channels pwm alignment mode and operation. see table 20-8 . mcam[1:0] and mcom[1:0] are double buffered. the values used for the generation of the output waveform will be copied to the working registers either at once (if all pwm channels are disabled or mcper is set to 0) or if a timer counter over?w occurs. reads of the register return the most recent written value, which are not necessarily the currently active values. 1:0 cd[1:0] pwm channel delay each pwm channel can be individually delayed by a programmable number of pwm timer counter clocks. the delay will be n/f tc . see table 20-9 . table 20-7. output mode mcom[1:0] output mode 00 half h-bridge mode, pwm on mncxm, mncxp is released 01 half h-bridge mode, pwm on mncxp, mncxm is released 10 full h-bridge mode 11 dual full h-bridge mode table 20-8. pwm alignment mode mcam[1:0] pwm alignment mode 00 channel disabled 01 left aligned 10 right aligned 11 center aligned
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 677 note the pwm motor controller will release the pins after the next pwm timer counter over?w without accommodating any channel delay if a single channel has been disabled or if the period register has been cleared or all channels have been disabled. program one or more inactive pwm frames (duty cycle = 0) before writing a con?uration that disables a single channel or the entire pwm motor controller. 20.3.2.5 motor controller duty cycle registers each duty cycle register sets the sign and duty functionality for the respective pwm channel. the contents of the duty cycle registers define duty, the number of motor controller timer counter clocks the corresponding output is driven low (recirc = 0) or is driven high (recirc = 1). setting all bits to 0 will give a static high output in case of recirc = 0; otherwise, a static low output. values greater than or equal to the contents of the period register will generate a static low output in case of recirc = 0, or a static high output if recirc = 1. the layout of the duty cycle registers differ dependent upon the state of the fast bit in the control register 0. table 20-9. channel delay cd[1:0] n [# of pwm clocks] 00 0 01 1 10 2 11 3 offset module base + 0x0020 . . . 0x002f access: user read/write 1514131211109876543210 r s ssss d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 20-8. motor controller duty cycle register x (mcdcx) with fast = 0
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 678 freescale semiconductor whenever fast = 1, the bits d10, d9, d1, and d0 will be set to 0 if the duty cycle register is written. for example setting mcdcx = 0x0158 with fast = 0 gives the same output waveform as setting mcdcx = 0x5600 with fast = 1 (with fast = 1, the low byte of mcdcx needs not to be written). the state of the fast bit has impact only during write and read operations. a change of the fast bit (set or clear) without writing a new value does not impact the internal interpretation of the duty cycle values. to prevent the output from inconsistent signals, the duty cycle registers are double buffered. the motor controller module will use working registers to generate the output signals. the working registers are copied from the bus accessible registers at the following conditions: mcper is set to 0 (all channels are disabled in this case) mcam[1:0] of the respective channel is set to 0 (channel is disabled) a pwm timer counter over?w occurs while in half h-bridge or full h-bridge mode a pwm channel pair is con?ured to work in dual full h-bridge mode and a pwm timer counter over?w occurs after the odd 6 duty cycle register of the channel pair has been written. in this way, the output of the pwm will always be either the old pwm waveform or the new pwm waveform, not some variation in between. reads of this register return the most recent value written. reads do not necessarily return the value of the currently active sign, duty cycle, and dither functionality due to the double buffering scheme. offset module base + 0x0020 . . . 0x002f access: user read/write 1514131211109876543210 r s d8d7d6d5d4d3d2 00000000 w reset 0 0 0 0 0 0 0 0 0 0000000 = unimplemented or reserved figure 20-9. motor controller duty cycle register x (mcdcx) with fast = 1 table 20-10. mcdcx field descriptions field description 0 s sign the sign bit is used to de?e which output will drive the pwm signal in (dual) full-h-bridge modes. the sign bit has no effect in half-bridge modes. see section 20.4.1.3.2, ?ign bit (s) , and table table 20-12 for detailed information about the impact of recirc and sign bit on the pwm output. 6. odd duty cycle register: mcdcx+1, x = 2 ? n
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 679 20.4 functional description 20.4.1 modes of operation 20.4.1.1 pwm output modes the motor controller is configurable between three output modes. dual full h-bridge mode can be used to control either a stepper motor or a 360 air core instrument. in this case two pwm channels are combined. in full h-bridge mode, each pwm channel is updated independently. in half h-bridge mode, one pin of the pwm channel can generate a pwm signal to control a 90 air core instrument (or other load requiring a pwm signal) and the other pin is unused. the mode of operation for each pwm channel is determined by the corresponding mcom[1:0] bits in channel control registers. after a reset occurs, each pwm channel will be disabled, the corresponding pins are released. each pwm channel consists of two pins. one output pin will generate a pwm signal. the other will operate as logic high or low output depending on the state of the recirc bit (refer to section 20.4.1.3.3, ?ecirc bit ), while in (dual) full h-bridge mode, or will be released, while in half h-bridge mode. the state of the s bit in the duty cycle register determines the pin where the pwm signal is driven in full h-bridge mode. while in half h-bridge mode, the state of the released pin is determined by other modules associated with this pin. associated with each pwm channel pair n are two pwm channels, x and x + 1, where x = 2 * n and n (0, 1, 2, 3) is the pwm channel pair number. duty cycle register x controls the sign of the pwm signal (which pin drives the pwm signal) and the duty cycle of the pwm signal for motor controller channel x. the pins associated with pwm channel x are mnc0p and mnc0m. similarly, duty cycle register x + 1 controls the sign of the pwm signal and the duty cycle of the pwm signal for channel x + 1. the pins associated with pwm channel x + 1 are mnc1p and mnc1m. this is summarized in table 20-11 . table 20-11. corresponding registers and pin names for each pwm channel pair pwm channel pair number pwm channel control register duty cycle register channel number pin names n mcmcx mcdcx pwm channel x, x = 2 ? n mnc0m mnc0p mcmcx + 1 mcdcx + 1 pwm channel x + 1, x = 2 ? n mnc1m mnc1p 0 mcmc0 mcdc0 pwm channel 0 m0c0m m0c0p mcmc1 mcdc1 pwm channel 1 m0c1m m0c1p
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 680 freescale semiconductor 20.4.1.1.1 dual full h-bridge mode (mcom = 11) pwm channel pairs x and x + 1 operate in dual full h-bridge mode if both channels have been enabled (mcam[1:0]=01, 10, or 11) and both of the corresponding output mode bits mcom[1:0] in both pwm channel control registers are set. a typical configuration in dual full h-bridge mode is shown in figure 20-10 . pwm channel x drives the pwm output signal on either mnc0p or mnc0m. if mnc0p drives the pwm signal, mnc0m will be output either high or low depending on the recirc bit. if mnc0m drives the pwm signal, mnc0p will be an output high or low. pwm channel x + 1 drives the pwm output signal on either mnc1p or mnc1m. if mnc1p drives the pwm signal, mnc1m will be an output high or low. if mnc1m drives the pwm signal, mnc1p will be an output high or low. this results in motor recirculation currents on the high side drivers (recirc = 0) while the pwm signal is at a logic high level, or motor recirculation currents on the low side drivers (recirc = 1) while the pwm signal is at a logic low level. the pin driving the pwm signal is determined by the s (sign) bit in the corresponding duty cycle register and the state of the recirc bit. the value of the pwm duty cycle is determined by the value of the d[10:0] or d[8:2] bits respectively in the duty cycle register depending on the state of the fast bit. 1 mcmc2 mcdc2 pwm channel 2 m1c0m m1c0p mcmc3 mcdc3 pwm channel 3 m1c1m m1c1p 2 mcmc4 mcdc4 pwm channel 4 m2c0m m2c0p mcmc5 mcdc5 pwm channel 5 m2c1m m2c1p 3 mcmc6 mcdc6 pwm channel 6 m3c0m m3c0p mcmc7 mcdc7 pwm channel 7 m3c1m m3c1p table 20-11. corresponding registers and pin names for each pwm channel pair (continued) pwm channel pair number pwm channel control register duty cycle register channel number pin names
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 681 figure 20-10. typical dual full h-bridge mode con?uration whenever fast = 0 only 16-bit write accesses to the duty cycle registers are allowed, 8-bit write accesses can lead to unpredictable duty cycles. while fast mode is enabled (fast = 1), 8-bit write accesses to the high byte of the duty cycle registers are allowed, because only the high byte of the duty cycle register is used to determine the duty cycle. the following sequence should be used to update the current magnitude and direction for coil 0 and coil 1 of the motor to achieve consistent pwm output: 1. write to duty cycle register x 2. write to duty cycle register x + 1. at the next timer counter overflow, the duty cycle registers will be copied to the working duty cycle registers. sequential writes to the duty cycle register x will result in the previous data being overwritten. 20.4.1.1.2 full h-bridge mode (mcom = 10) in full h-bridge mode, the pwm channels x and x + 1 operate independently. the duty cycle working registers are updated whenever a timer counter overflow occurs. 20.4.1.1.3 half h-bridge mode (mcom = 00 or 01) in half h-bridge mode, the pwm channels x and x + 1 operate independently. in this mode, each pwm channel can be configured such that one pin is released and the other pin is a pwm output. figure 20-11 shows a typical configuration in half h-bridge mode. the two pins associated with each channel are switchable between released mode and pwm output dependent upon the state of the mcom[1:0] bits in the mcccx (channel control) register. see register description in section 20.3.2.4, ?otor controller channel control registers . in half h-bridge mode, the state of the s bit has no effect. pwm channel x pwm channel x + 1 mnc0p mnc0m mnc1p mnc1m motor n, coil 0 motor n, coil 1
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 682 freescale semiconductor figure 20-11. typical quad half h-bridge mode con?uration 20.4.1.2 relationship between pwm mode and pwm channel enable the pair of motor controller channels cannot be placed into dual full h-bridge mode unless both motor controller channels have been enabled (mcam[1:0] not equal to 00) and dual full h-bridge mode is selected for both pwm channels (mcom[1:0] = 11). if only one channel is set to dual full h-bridge mode, this channel will operate in full h-bridge mode, the other as programmed. 20.4.1.3 relationship between sign, duty, dither, recirc, period, and pwm mode functions 20.4.1.3.1 pwm alignment modes each pwm channel can be programmed individually to three different alignment modes. the mode is determined by the mcam[1:0] bits in the corresponding channel control register. left aligned (mcam[1:0] = 01): the output will start active (low if recirc = 0 or high if recirc = 1) and will turn inactive (high if recirc = 0 or low if recirc = 1) after the number of counts specified by the corresponding duty cycle register. pwm channel x pwm channel x + 1 mnc0p mnc0m mnc1p mnc1m released pwm output v ssm v ddm v ssm v ddm released pwm output
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 683 right aligned (mcam[1:0] = 10): the output will start inactive (high if recirc = 0 and low if recirc = 1) and will turn active after the number of counts specified by the difference of the contents of period register and the corresponding duty cycle register . center aligned (mcam[1:0] = 11): even periods will be output left aligned, odd periods will be output right aligned. pwm operation starts with the even period after the channel has been enabled. pwm operation in center aligned mode might start with the odd period if the channel has not been disabled before changing the alignment mode to center aligned. 0 15 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 1 period 100 counts 15 99 99 dith = 0, mcam[1:0] = 01, mcdcx = 15, mcper = 100, recirc = 0 0 85 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 1 period 100 counts 85 99 99 dith = 0, mcam[1:0] = 10, mcdcx = 15, mcper = 100, recirc = 0 0 85 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 1 period 100 counts 15 99 99 dith = 0, mcam[1:0] = 11, mcdcx = 15, mcper = 100, recirc = 0
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 684 freescale semiconductor 20.4.1.3.2 sign bit (s) assuming recirc = 0 (the active state of the pwm signal is low), when the s bit for the corresponding channel is cleared, mnc0p (if the pwm channel number is even, n = 0, 1, 2, 3, see table 20-11 ) or mnc1p (if the pwm channel number is odd, n = 0, 1, 2, 3, see table 20-11 ), outputs a logic high while in (dual) full h-bridge mode. in half h-bridge mode the state of the s bit has no effect. the pwm output signal is generated on mnc0m (if the pwm channel number is even, n = 0, 1, 2, 3, see table 20-11 ) or mnc1m (if the pwm channel number is odd, n = 0, 1, 2, 3). assuming recirc = 0 (the active state of the pwm signal is low), when the s bit for the corresponding channel is set, mnc0m (if the pwm channel number is even, n = 0, 1, 2, 3, see table 20-11 ) or mnc1m (if the pwm channel number is odd, n = 0, 1, 2, 3, see table 20-11 ), outputs a logic high while in (dual) full h-bridge mode. in half h-bridge mode the state of the s bit has no effect. the pwm output signal is generated on mnc0p (if the pwm channel number is even, n = 0, 1, 2, 3, see table 20-11 ) or mnc1p (if the pwm channel number is odd, n = 0, 1, 2, 3). setting recirc = 1 will also invert the effect of the s bit such that while s = 0, mnc0p or mnc1p will generate the pwm signal and mnc0m or mnc1m will be a static low output. while s = 1, mnc0m or mnc1m will generate the pwm signal and mnc0p or mnc1p will be a static low output. in this case the active state of the pwm signal will be high. see table 20-12 for detailed information about the impact of sign and recirc bit on the pwm output. 20.4.1.3.3 recirc bit the recirc bit controls the flow of the recirculation current of the load. setting recirc = 0 will cause recirculation current to flow through the high side transistors, and recirc = 1 will cause the recirculation current to flow through the low side transistors. the recirc bit is only active in (dual) full h-bridge modes. effectively, recirc = 0 will cause a static high output on the output terminal not driven by the pwm, recirc = 1 will cause a static low output on the output terminals not driven by the pwm. to achieve the same current direction, the s bit behavior is inverted if recirc = 1. figure 20-12 , figure 20-13 , figure 20-14 , and figure 20-15 illustrate the effect of the recirc bit in (dual) full h-bridge modes. table 20-12. impact of recirc and sign bit on the pwm output output mode recirc sign mncym mncyp (dual) full h-bridge 0 0 pwm 1 1 pwm: the pwm signal is low active. e.g., the waveform starts with 0 in left aligned mode. output m generates the pwm signal. output p is static high. 1 (dual) full h-bridge 0 1 1 pwm (dual) full h-bridge 1 0 0 pwm 2 2 pwm: the pwm signal is high active. e.g., the waveform starts with 1 in left aligned mode. output p generates the pwm signal. output m is static low. (dual) full h-bridge 1 1 pwm 0 half h-bridge: pwm on mncym don? care don? care pwm 3 3 the state of the output transistors is not controlled by the motor controller. half h-bridge: pwm on mncyp don? care don? care pwm
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 685 recirc bit must be changed only while no pwm channel is operated in (dual) full h-bridge mode. figure 20-12. pwm active phase, recirc = 0, s = 0 figure 20-13. pwm passive phase, recirc = 0, s = 0 v ddm v ssm mnc0p mnc0m static 0 pwm 1 pwm 1 static 0 v ddm v ssm mnc0p mnc0m static 0 pwm 0 static 0 pwm 0
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 686 freescale semiconductor figure 20-14. pwm active phase, recirc = 1, s = 0 figure 20-15. pwm passive phase, recirc = 1, s = 0 v ssm mnc0p mnc0m v ddm static 1 static 1 pwm 0 pwm 0 v ddm v ssm mnc0p mnc0m static 1 static 1 pwm 1 pwm 1
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 687 20.4.1.3.4 relationship between recirc bit, s bit, mcom bits, pwm state, and output transistors please refer to figure 20-16 for the output transistor assignment. figure 20-16. output transistor assignment table 20-13 illustrates the state of the output transistors in different states of the pwm motor controller module. ?means that the state of the output transistor is not controlled by the motor controller. table 20-13. state of output transistors in various modes mode mcom[1:0] pwm duty recirc s t1 t2 t3 t4 off don? care don? care don? care half h-bridge 00 active don? care don? care off on half h-bridge 00 passive don? care don? care on off half h-bridge 01 active don? care don? care off on half h-bridge 01 passive don? care don? care on off (dual) full 10 or 11 active 0 0 on off off on (dual) full 10 or 11 passive 0 0 on off on off (dual) full 10 or 11 active 0 1 off on on off (dual) full 10 or 11 passive 0 1 on off on off (dual) full 10 or 11 active 1 0 on off off on (dual) full 10 or 11 passive 1 0 off on off on (dual) full 10 or 11 active 1 1 off on on off (dual) full 10 or 11 passive 1 1 off on off on v ddm v ssm mncyp mncym t1 t2 t3 t4
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 688 freescale semiconductor 20.4.1.3.5 dither bit (dith) the purpose of the dither mode is to increase the minimum length of output pulses without decreasing the pwm resolution, in order to limit the pulse distortion introduced by the slew rate control of the outputs. if dither mode is selected the output pattern will repeat after two timer counter overflows. for the same output frequency, the shortest output pulse will have twice the length while dither feature is selected. to achieve the same output frame frequency, the prescaler of the mc10b8c module has to be set to twice the division rate if dither mode is selected; e.g., with the same prescaler division rate the repeat rate of the output pattern is the same as well as the shortest output pulse with or without dither mode selected. the dith bit in control register 0 enables or disables the dither function. dith = 0: dither function is disabled. when dith is cleared and assuming left aligned operation and recirc = 0, the pwm output will start at a logic low level at the beginning of the pwm period (motor controller timer counter = 0x000). the pwm output remains low until the motor controller timer counter matches the 11-bit pwm duty cycle value, duty, contained in d[10:0] in mcdcx. when a match (output compare between motor controller timer counter and duty) occurs, the pwm output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reaches the contents of mcper 1). after the motor controller timer counter resets to 0x000, the pwm output will return to a logic low level. this completes one pwm period. the pwm period repeats every p counts (as defined by the bits p[10:0] in the motor controller period register) of the motor controller timer counter. if duty >= p, the output will be static low. if duty = 0x0000, the output will be continuously at a logic high level. the relationship between the motor controller timer counter clock, motor controller timer counter value, and pwm output while dith = 0 is shown in figure 20-17 . figure 20-17. pwm output: dith = 0, mcam[1:0] = 01, mcdc = 100, mcper = 200, recirc = 0 dith = 1: dither function is enabled please note if dith = 1, the bit p0 in the motor controller period register will be internally forced to 0 and read always as 0. when dith is set and assuming left aligned operation and recirc = 0, the pwm output will start at a logic low level at the beginning of the pwm period (when the motor controller timer counter = 0x000). the pwm output remains low until the motor controller timer counter matches the 10-bit pwm duty cycle 0 100 0 100 0 pwm output 1 period 200 counts 200 counts 1 period motor controller timer counter clock motor controller timer counter 199 199
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 689 value, duty, contained in d[10:1] in mcdcx. when a match (output compare between motor controller timer counter and duty) occurs, the pwm output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reaches the value defined by p[10:1] 1 in mcper). after the motor controller timer counter resets to 0x000, the pwm output will return to a logic low level. this completes the first half of the pwm period. during the second half of the pwm period, the pwm output will remain at a logic low level until either the motor controller timer counter matches the 10-bit pwm duty cycle value, duty, contained in d[10:1] in mcdcx if d0 = 0, or the motor controller timer counter matches the 10-bit pwm duty cycle value + 1 (the value of d[10:1] in mcdcx is increment by 1 and is compared with the motor controller timer counter value) if d0 = 1 in the corresponding duty cycle register. when a match occurs, the pwm output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reaches the value defined by p[10:1] ?1 in mcper). after the motor controller timer counter resets to 0x000, the pwm output will return to a logic low level. this process will repeat every number of counts of the motor controller timer counter defined by the period register contents (p[10:0]). if the output is neither set to 0% nor to 100% there will be four edges on the pwm output per pwm period in this case. therefore, the pwm output compare function will alternate between duty and duty + 1 every half pwm period if d0 in the corresponding duty cycle register is set to 1. the relationship between the motor controller timer counter clock (f tc ), motor controller timer counter value, and left aligned pwm output if dith = 1 is shown in figure 20-18 and figure 20-19 . figure 20-20 and figure 20-21 show right aligned and center aligned pwm operation respectively, with dither feature enabled and d0 = 1. please note: in the following examples, the mcper value is defined by the bits p[10:0], which is, if dith = 1, always an even number. note the dith bit must be changed only if the motor controller is disabled (all channels disabled or period register cleared) to avoid erroneous waveforms. figure 20-18. pwm output: dith = 1, mcam[1:0] = 01, mcdc = 31, mcper = 200, recirc = 0 0 15 pwm output 16 0 100 counts motor controller timer counter motor controller timer counter clock 0 16 1 period 100 counts 15 99 99
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 690 freescale semiconductor figure 20-19. pwm output: dith = 1, mcam[1:0] = 01, mcdc = 30, mcper = 200, recirc = 0 . figure 20-20. pwm output: dith = 1, mcam[1:0] = 10, mcdc = 31, mcper = 200, recirc = 0 figure 20-21. pwm output: dith = 1, mcam[1:0] = 11, mcdc = 31, mcper = 200, recirc = 0 pwm output 1 period 100 counts motor controller timer counter motor controller timer counter clock 100 counts 015 16 0 0 16 15 99 99 0 84 pwm output 85 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 85 100 counts 84 99 99 0 84 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 100 counts 15 99 99
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 691 20.4.2 pwm duty cycle the pwm duty cycle for the motor controller channel x can be determined by dividing the decimal representation of bits d[10:0] in mcdcx by the decimal representation of the bits p[10:0] in mcper and multiplying the result by 100% as shown in the equation below: note x = pwm channel number = 0, 1, 2, 3 ... 8. this equation is only valid if duty <= mcper and mcper is not equal to 0. whenever d[10:0] >= p[10:0], a constant low level (recirc = 0) or high level (recirc = 1) will be output. 20.4.3 motor controller counter clock source figure 20-22 shows how the pwm motor controller timer counter clock source is selected. figure 20-22. motor controller counter clock selection the peripheral bus clock is the source for the motor controller counter prescaler. the motor controller counter clock rate, f tc , is set by selecting the appropriate prescaler value. the prescaler is selected with the mcpre[1:0] bits in motor controller control register 0 (mcctl0). the motor controller channel frequency of operation can be calculated using the following formula if dith = 0: effective pwm channel x % duty cycle duty mcper -------------------- - 100% ? = 1 1/2 1/4 1/8 motor controller timer counter prescaler motor controller timer counter clock prescaler select mppre0, mppre1 11-bit motor controller timer counter peripheral bus clock f bus clock generator clk clocks and reset generator module motor controller timer counter clock f tc motor channel frequency (hz) f tc mcper m ? ------------------------------ - =
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 692 freescale semiconductor the motor controller channel frequency of operation can be calculated using the following formula if dith = 1: note both equations are only valid if mcper is not equal to 0. m = 1 for left or right aligned mode, m = 2 for center aligned mode. table 20-14 shows examples of the motor controller channel frequencies that can be generated based on different peripheral bus clock frequencies and the prescaler value. note due to the selectable slew rate control of the outputs, clipping may occur on short output pulses. 20.4.4 output switching delay in order to prevent large peak current draw from the motor power supply, selectable delays can be used to stagger the high logic level to low logic level transitions on the motor controller outputs. the timing delay, t d , is determined by the cd[1:0] bits in the corresponding channel control register (mcmcx) and is selectable between 0, 1, 2, or 3 motor controller timer counter clock cycles. note a pwm channel gets disabled at the next timer counter over?w without notice of the switching delay. table 20-14. motor controller channel frequencies (hz), mcper = 256, dith = 0, mcam = 10, 01 prescaler peripheral bus clock frequency 16 mhz 10 mhz 8 mhz 5 mhz 4 mhz 1 62500 39063 31250 19531 15625 1/2 31250 19531 15625 9766 7813 1/4 15625 9766 7813 4883 3906 1/8 7813 4883 3906 2441 1953 motor channel frequency (hz) f tc mcper m 2 ? ? ------------------------------------- - =
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 693 20.4.5 operation in wait mode during wait mode, the operation of the motor controller pins are selectable between the following two options: 1. mcswai = 1: all module clocks are stopped and the associated port pins are set to their inactive state, which is defined by the state of the recirc bit during wait mode. the motor controller module registers stay the same as they were prior to entering wait mode. therefore, after exiting from wait mode, the associated port pins will resume to the same functionality they had prior to entering wait mode. 2. mcswai = 0: the pwm clocks continue to run and the associated port pins maintain the functionality they had prior to entering wait mode both during wait mode and after exiting wait mode. 20.4.6 operation in stop and pseudo-stop modes all module clocks are stopped and the associated port pins are set to their inactive state, which is defined by the state of the recirc bit. the motor controller module registers stay the same as they were prior to entering stop or pseudo-stop modes. therefore, after exiting from stop or pseudo-stop modes, the associated port pins will resume to the same functionality they had prior to entering stop or pseudo-stop modes. 20.5 reset the motor controller is reset by system reset. all associated ports are released, all registers of the motor controller module will switch to their reset state as defined in section 20.3.2, ?egister descriptions . 20.6 interrupts the motor controller has one interrupt source. 20.6.1 timer counter over?w interrupt an interrupt will be requested when the mctoie bit in the motor controller control register 1 is set and the running pwm frame is finished. the interrupt is cleared by either setting the mctoie bit to 0 or to write a 1 to the mctoif bit in the motor controller control register 0.
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 694 freescale semiconductor 20.7 initialization/application information this section provides an example of how the pwm motor controller can be initialized and used by application software. the con?uration parameters (e.g., timer settings, duty cycle values, etc.) are not guaranteed to be adequate for any real application. the example software is implemented in assembly language. 20.7.1 code example one way to use the motor controller is: 1. perform global initialization a) set the motor controller control registers mcctl0 and mcctl1 to appropriate values. i) prescaler disabled (mcpre1 = 0, mcpre0 = 0). ii) fast mode and dither disabled (fast = 0, dith = 0). iii) recirculation feature in dual full h-bridge mode disabled (recirc = 0). all other bits in mcctl0 and mcctl1 are set to 0. b) con?ure the channel control registers for the desired mode. i) dual full h-bridge mode (mcom[1:0] = 11). ii) left aligned pwm (mcam[1:0] = 01). iii) no channel delay (mccd[1:0] = 00). 2. perform the startup phase a) clear the duty cycle registers mcdc0 and mcdc1 b) initialize the period register mcper, which is equivalent to enabling the motor controller. c) enable the timer which generates the timebase for the updates of the duty cycle registers. 3. main program a) check if pin pb0 is set to ??and execute the sub program if a timer interrupt is pending. b) initiate the shutdown procedure if pin pb0 is set to ?? 4. sub program a) update the duty cycle registers load the duty cycle registers mcdc0 and mcdc1 with new values from the table and clear the timer interrupt ?g. the sub program will initiate the shutdown procedure if pin pb0 is set to ?? b) shutdown procedure the timer is disabled and the duty cycle registers are cleared to drive an inactive value on the pwm output as long as the motor controller is enabled. the period register is cleared after a certain time, which disables the motor controller. the table address is restored and the timer interrupt ?g is cleared.
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 695 ;------------------------------------------------------------------------------------------ ; motor controller (mc10b8c) setup example ;------------------------------------------------------------------------------------------ ; timer defines ;------------------------------------------------------------------------------------------ t_start equ $0040 tscr1 equ t_start+$06 tflg2 equ t_start+$0f ;------------------------------------------------------------------------------------------ ; motor controller defines ;------------------------------------------------------------------------------------------ mc_start equ $0200 mcctl0 equ mc_start+$00 mcctl1 equ mc_start+$01 mcper_hi equ mc_start+$02 mcper_lo equ mc_start+$03 mccc0 equ mc_start+$10 mccc1 equ mc_start+$11 mccc2 equ mc_start+$12 mccc3 equ mc_start+$13 mcdc0_hi equ mc_start+$20 mcdc0_lo equ mc_start+$21 mcdc1_hi equ mc_start+$22 mcdc1_lo equ mc_start+$23 mcdc2_hi equ mc_start+$24 mcdc2_lo equ mc_start+$25 mcdc3_hi equ mc_start+$26 mcdc3_lo equ mc_start+$27 ;------------------------------------------------------------------------------------------ ; port defines ;------------------------------------------------------------------------------------------ ddrb equ $0003 portb equ $0001 ;------------------------------------------------------------------------------------------ ; flash defines ;------------------------------------------------------------------------------------------ flash_start equ $0100 fcmd equ flash_start+$06 fclkdiv equ flash_start+$00 fstat equ flash_start+$05 ftstmod equ flash_start+$02 ; variables code_start equ $1000 ; start of program code dtydat equ $1500 ; start of motor controller duty cycle data temp_x equ $1700 ; save location for ix reg in isr tablesize equ $1704 ; number of config entries in the table mcperiod equ $0250 ; motor controller period ;------------------------------------------------------------------------------------------ ;------------------------------------------------------------------------------------------ org code_start ; start of code lds #$1fff ; set stack pointer movw #$000a,tablesize ; number of configurations in the table movw tablesize,temp_x
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 696 freescale semiconductor ;------------------------------------------------------------------------------------------ ;global motor controller init ;------------------------------------------------------------------------------------------ glb_init: movb #$0000,mcctl0 ; fmc = fbus, fast=0, dith=0 movb #$0000,mcctl1 ; recirc=0, mctoie=0 movw #$d0d0,mccc0 ; dual full h-bridge mode, left aligned, ; no channel delay movw #$0000,mcper_hi ; disable motor controller ;------------------------------------------------------------------------------------------ ;motor controller startup ;------------------------------------------------------------------------------------------ startup: movw #$0000,mcdc0_hi ; define startup duty cycles movw #$0000,mcdc1_hi movw #mcperiod,mcper_hi ; define pwm period movb #$80,tscr1 ; enable timer main: ldaa portb ; if pb=0, activate shutdown anda #$01 beq mn0 jsr tim_sr mn0: tst tflg2 ; poll for timer counter overflow flag beq main ; tof set? jsr tim_sr ; yes, go to tim_sr bra main tim_sr: ldx temp_x ; restore index register x ldaa portb ; if pb=0, enter shutdown routine anda #$01 bne shutdown ldx temp_x ; restore index register x beq new_seq ; all mc configurations done? new_cfg: ldd dtydat,x ; load new config? std mcdc0_hi dex dex ldd dtydat,x std mcdc1_hi bra end_sr ; leave sub-routine shutdown: movb #$00,tscr1 ; disable timer movw #$0000,mcdc0_hi ; define startup duty cycle movw #$0000,mcdc1_hi ; define startup duty cycle ldaa #$0000 ; ensure that duty cycle registers are ; cleared for some time before disabling ; the motor controller loop deca bne loop movw #$0000,mcper_hi ; define pwm period new_seq: movw tablesize,temp_x ; start new tx loop ldx temp_x end_sr: stx temp_x ; save byte counter movb #$80,tflg2 ; clear tof rts ; wait for new timer overflow
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 697 ;------------------------------------------------------------------------------------------ ; motor controller duty cycles ;------------------------------------------------------------------------------------------ org dtydat dc.b $02, $ff 7 ; mcdc1_hi, mcdc1_lo dc.b $02, $d0 ; mcdc0_hi, mcdc0_lo dc.b $02, $a0 ; mcdc1_hi, mcdc1_lo dc.b $02, $90 ; mcdc0_hi, mcdc0_lo dc.b $02, $60 ; mcdc1_hi, mcdc1_lo dc.b $02, $25 ; mcdc0_hi, mcdc0_lo 7. the values for the duty cycle table have to be de?ed for the needs of the target application.
motor controller (mc10b8cv1) mc9s12xhy-family reference manual, rev. 1.01 698 freescale semiconductor
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 699 chapter 21 stepper stall detector (ssdv1) block description 21.1 introduction the stepper stall detector (ssd) block provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (rtz). during the rtz event, the pointer is returned to zero using full steps in either clockwise or counter clockwise direction, where only one coil is driven at any point in time. the back electromotive force (emf) signal present on the non-driven coil is integrated after a blanking time, and its results stored in a 16-bit accumulator. the 16-bit modulus down counter can be used to monitor the blanking time and the integration time. the value in the accumulator represents the change in linked ?x (magnetic ?x times the number of turns in the coil) and can be compared to a stored threshold. values above the threshold indicate a moving motor, in which case the pointer can be advanced another full step in the same direction and integration be repeated. values below the threshold indicate a stalled motor, thereby marking the cessation of the rtz event. the ssd is capable of multiplexing two stepper motors. 21.1.1 modes of operation return to zero modes blanking with no drive blanking with drive conversion integration low-power modes 21.1.2 features programmable full step state programmable integration polarity blanking (recirculation) state 16-bit integration accumulator register 16-bit modulus down counter with interrupt multiplex two stepper motors
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 700 freescale semiconductor 21.1.3 block diagram figure 21-1. ssd block diagram coil sinx coil cosx bus clock vddm cosxp cosxm t1 t2 t3 vssm 1/2 1/2 1/2 1/8 4:1 mux vddm t4 vssm s1 s3 s2 s4 vddm sinxp sinxm t5 t6 t7 vssm vddm t8 vssm s5 s7 s6 s8 16-bit accumulator register vddm vssm r2 r2 dff 16-bit modulus down counter r1 c1 + + 16-bit load register sigma-delta converter p a d p a d p a d p a d integrator reference 1/8 2:1 mux x = a or b dac (analog)
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 701 21.2 external signal description each ssd signal is the output pin of a half bridge, designed to source or sink current. the h-bridge pins drive the sine and cosine coils of a stepper motor to provide four-quadrant operation. the ssd is capable of multiplexing between stepper motor a and stepper motor b if two motors are connected. 21.2.1 cosxm/cosxp ?cosine coil pins for motor x these pins interface to the cosine coils of a stepper motor to measure the back emf for calibration of the pointer reset position. 21.2.2 sinxm/sinxp ?sine coil pins for motor x these pins interface to the sine coils of a stepper motor to measure the back emf for calibration of the pointer reset position. table 21-1. pin table 1 1 x = a or b indicating motor a or motor b pin name node coil cosxm minus cosx cosxp plus sinxm minus sinx sinxp plus
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 702 freescale semiconductor 21.3 memory map and register de?ition this section provides a detailed description of all registers of the stepper stall detector (ssd) block. 21.3.1 module memory map table 21-2 gives an overview of all registers in the ssdv1 memory map. the ssdv1 occupies eight bytes in the memory space. the register address results from the addition of base address and address offset. the base address is determined at the mcu level and is given in the device overview chapter. the address offset is de?ed at the block level and is given here. 21.3.2 register descriptions this section describes in detail all the registers and register bits in the ssdv1 block. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. table 21-2. ssdv1 memory map address offset use access 0x0000 rtzctl r/w 0x0001 mdcctl r/w 0x0002 ssdctl r/w 0x0003 ssdflg r/w 0x0004 mdccnt (high) r/w 0x0005 mdccnt (low) r/w 0x0006 itgacc (high) r 0x0007 itgacc (low) r
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 703 21.3.2.1 return-to-zero control register (rtzctl) read: anytime write: anytime module base + 0x0000 76543210 r itg dcoil rcir pol 0 sms step w reset 0 0 0 00000 = unimplemented or reserved figure 21-2. return-to-zero control register (rtzctl) table 21-3. rtzctl field descriptions field description 7 itg integration during return to zero (rtze = 1), one of the coils must be recirculated or non-driven determined by the step ?ld. if the itg bit is set, the coil is non-driven, and if the itg bit is clear, the coil is being recirculated. table 21-4 shows the condition state of each transistor from figure 21-1 based on the step, itg, dcoil and rcir bits. regardless of the rtze bit value, if the itg bit is set, one end of the non-driven coil connects to the (non-zero) reference input and the other end connects to the integrator input of the sigma-delta converter. regardless of the rtze bit value, if the itg bit is clear, the non-driven coil is in a blanking state, the converter is in a reset state, and the accumulator is initialized to zero. table 21-5 shows the condition state of each switch from figure 21-1 based on the itg, step and pol bits. 0 blanking 1 integration 6 dcoil drive coil ?during return to zero (rtze=1), one of the coils must be driven determined by the step ?ld. if the dcoil bit is set, this coil is driven. if the dcoil bit is clear, this coil is disconnected or drivers turned off. table 21-4 shows the condition state of each transistor from figure 21-1 based on the step, itg, dcoil and rcir bits. 0 disconnect coil 1 drive coil 5 rcir recirculation in blanking mode ?during return to zero (rtze = 1), one of the coils is recirculated prior to integration during the blanking period. this bit determines if the coil is recirculated via vddm or via vssm. table 21-4 shows the condition state of each transistor from figure 21-1 based on the step, itg, dcoil and rcir bits. 0 recirculation on the high side transistors 1 recirculation on the low side transistors 4 pol polarity ?this bit determines which end of the non-driven coil is routed to the sigma-delta converter during conversion or integration mode. table 21-5 shows the condition state of each switch from figure 21-1 based on the itg, step and pol bits.
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 704 freescale semiconductor 2 sms stepper motor select this bit selects one of two possible stepper motors to be used for stall detection. see top level chip description for the stepper motor assignments to the ssd. 0 stepper motor a is selected for stall detection 1 stepper motor b is selected for stall detection 1:0 step full step state this ?ld indicates one of the four possible full step states. step 0 is considered the east pole or 0 angle, step 1 is the north pole or 90 angle, step 2 is the west pole or 180 angle, and step 3 is the south pole or 270 angle. for each full step state, table 21-6 shows the current through each of the two coils, and the coil nodes that are multiplexed to the sigma-delta converter during conversion or integration mode. table 21-4. transistor condition states (rtze = 1) step itg dcoil rcir t1 t2 t3 t4 t5 t6 t7 t8 xx 1 0 x off off off off off off off off 00 0 0 0 off off off off on off on off 00 0 0 1 off off off off off on off on 00 0 1 0 on off off on on off on off 00 0 1 1 on off off on off on off on 00 1 1 x on off off on off off off off 01 0 0 0 on off on off off off off off 01 0 0 1 off on off on off off off off 01 0 1 0 on off on off on off off on 01 0 1 1 off on off on on off off on 01 1 1 x off off off off on off off on 10 0 0 0 off off off off on off on off 10 0 0 1 off off off off off on off on 10 0 1 0 off on on off on off on off 10 0 1 1 off on on off off on off on 10 1 1 x off on on off off off off off 11 0 0 0 on off on off off off off off 11 0 0 1 off on off on off off off off 11 0 1 0 on off on off off on on off 11 0 1 1 off on off on off on on off 11 1 1 x off off off off off on on off table 21-3. rtzctl field descriptions (continued) field description
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 705 21.3.2.2 modulus down counter control register (mdcctl) read: anytime write: anytime. table 21-5. switch condition states (rtze = 1 or 0) itg step pol s1 s2 s3 s4 s5 s6 s7 s8 0 xx x open open open open open open open open 1 00 0 open open open open close open open close 1 00 1 open open open open open close close open 1 01 0 open close close open open open open open 1 01 1 close open open close open open open open 1 10 0 open open open open open close close open 1 10 1 open open open open close open open close 1 11 0 close open open close open open open open 1 11 1 open close close open open open open open table 21-6. full step states step pole angle cosine coil current sine coil current coil node to integrator input (close switch) coil node to reference input (close switch) dcoil = 0 dcoil = 1 dcoil = 0 dcoil = 1 itg = 1 pol = 0 itg = 1 pol = 1 itg = 1 pol = 0 itg = 1 pol = 1 0 east 0 0 + i max 0 0 sinxm (s8) sinxp (s6) sinxp (s5) sinxm (s7) 1 north 90 0 0 0 + i max cosxp (s2) cosxm (s4) cosxm (s3) cosxp (s1) 2 west 180 0 i max 0 0 sinxp (s6) sinxm (s8) sinxm (s7) sinxp (s5) 3 south 270 0 0 0 i max cosxm (s4) cosxp (s2) cosxp (s1) cosxm (s3) module base + 0x0001 76543210 r mczie modmc rdmcl pre 0 mcen 0 aovie w flmc reset 0 0 0 00000 = unimplemented or reserved figure 21-3. modulus down counter control register (mdcctl)
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 706 freescale semiconductor l 21.3.2.3 stepper stall detector control register (ssdctl) read: anytime write: anytime table 21-7. mdcctl field descriptions field description 7 mczie modulus counter under?w interrupt enable 0 interrupt disabled. 1 interrupt enabled. an interrupt will be generated when the modulus counter under?w interrupt ?g (mczif) is set. 6 modmc modulus mode enable 0 the modulus counter counts down from the value in the counter register and will stop at 0x0000. 1 modulus mode is enabled. when the counter reaches 0x0000, the counter is loaded with the latest value written to the modulus counter register. note: for proper operation, the mcen bit should be cleared before modifying the modmc bit in order to reset the modulus counter to 0xffff. 5 rdmcl read modulus down-counter load 0 reads of the modulus count register (mdccnt) will return the present value of the count register. 1 reads of the modulus count register (mdccnt) will return the contents of the load register. 4 pre prescaler 0 the modulus down counter clock frequency is the bus frequency divided by 64. 1 the modulus down counter clock frequency is the bus frequency divided by 512. note: a change in the prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs. 3 flmc force load register into the modulus counter count register ?this bit always reads zero. 0 write zero to this bit has no effect. 1 write one into this bit loads the load register into the modulus counter count register. 2 mcen modulus down-counter enable 0 modulus down-counter is disabled. the modulus counter (mdccnt) is preset to 0xffff. this will prevent an early interrupt ?g when the modulus down-counter is enabled. 1 modulus down-counter is enabled. 0 aovie accumulator over?w interrupt enable 0 interrupt disabled. 1 interrupt enabled. an interrupt will be generated when the accumulator over?w interrupt ?g (aovif) is set. module base + 0x0002 76543210 r rtze sdcpu ssdwai ftst 00 aclks w reset 0 0 0 00000 = unimplemented or reserved figure 21-4. stepper stall detector control register (ssdctl)
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 707 l note a change in the accumulator sample frequency will not be effective until the itg bit is cleared. table 21-8. ssdctl field descriptions field description 7 rtze return to zero enable if this bit is set, the coils are controlled by the ssd and are con?ured into one of the four full step states as shown in table 21-6 . if this bit is cleared, the coils are not controlled by the ssd. 0 rtz is disabled. 1 rtz is enabled. 6 sdcpu sigma-delta converter power up ?this bit provides on/off control for the sigma-delta converter allowing reduced mcu power consumption. because the analog circuit is turned off when powered down, the sigma-delta converter requires a recovery time after it is powered up. 0 sigma-delta converter is powered down. 1 sigma-delta converter is powered up. 5 ssdwai ssd disabled during wait mode ?when entering wait mode, this bit provides on/off control over the ssd allowing reduced mcu power consumption. because the analog circuit is turned off when powered down, the sigma-delta converter requires a recovery time after exit from wait mode. 0 ssd continues to run in wait mode. 1 entering wait mode freezes the clock to the prescaler divider, powers down the sigma-delta converter, and if rtze bit is set, the sine and cosine coils are recirculated via vssm. 4 ftst factory test ?this bit is reserved for factory test and reads zero in user mode. 1:0 aclks accumulator sample frequency select ?this ?ld sets the accumulator sample frequency by pre-scaling the bus frequency by a factor of 8, 16, 32, or 64. a faster sample frequency can provide more accurate results but cause the accumulator to over?w. best results are achieved with a frequency between 500 khz and 2 mhz. accumulator sample frequency = f bus / (8 x 2 aclks ) table 21-9. accumulator sample frequency aclks frequency f bus = 40 mhz f bus = 25 mhz f bus = 16 mhz 0f bus / 8 5.00 mhz 3.12 mhz 2.00 mhz 1f bus / 16 2.50 mhz 1.56 mhz 1.00 mhz 2f bus / 32 1.25 mhz 781 khz 500 khz 3f bus / 64 625 khz 391 khz 250 khz
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 708 freescale semiconductor 21.3.2.4 stepper stall detector flag register (ssdflg) read: anytime write: anytime. l 21.3.2.5 modulus down-counter count register (mdccnt) read: anytime write: anytime. module base + 0x0003 76543210 r mczif 000000 aovif w reset 0 0 0 00000 = unimplemented or reserved figure 21-5. stepper stall detector flag register (ssdflg) table 21-10. ssdflg field descriptions field description 7 mczif modulus counter under?w interrupt flag ?this ?g is set when the modulus down-counter reaches 0x0000. if not masked (mczie = 1), a modulus counter under?w interrupt is pending while this ?g is set. this ?g is cleared by writing a ??to the bit. a write of ??has no effect. 0 aovif accumulator over?w interrupt flag ?this ?g is set when the integration accumulator has a positive or negative over?w. if not masked (aovie = 1), an accumulator over?w interrupt is pending while this ?g is set. this ?g is cleared by writing a ??to the bit. a write of ??has no effect. module base + 0x0004 15 14 13 12 11 10 9 8 r mdccnt w reset 1 1 1 11111 figure 21-6. modulus down-counter count register high (mdccnt) module base + 0x0005 76543210 r mdccnt w reset 1 1 1 11111 figure 21-7. modulus down-counter count register low (mdccnt)
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 709 note a separate read/write for high byte and low byte gives a different result than accessing the register as a word. if the rdmcl bit in the mdcctl register is cleared, reads of the mdccnt register will return the present value of the count register. if the rdmcl bit is set, reads of the mdccnt register will return the contents of the load register. with a 0x0000 write to the mdccnt register, the modulus counter stays at zero and does not set the mczif ?g in the ssdflg register. if modulus mode is not enabled (modmc = 0), a write to the mdccnt register immediately updates the load register and the counter register with the value written to it. the modulus counter will count down from this value and will stop at 0x0000. if modulus mode is enabled (modmc = 1), a write to the mdccnt register updates the load register with the value written to it. the count register will not be updated with the new value until the next counter under?w. the flmc bit in the mdcctl register can be used to immediately update the count register with the new value if an immediate load is desired. the modulus down counter clock frequency is the bus frequency divided by 64 or 512. 21.3.2.6 integration accumulator register (itgacc) read: anytime. write: never. note a separate read for high byte and low byte gives a different result than accessing the register as a word. module base + 0x0006 15 14 13 12 11 10 9 8 r itgacc w reset 0 0 0 00000 figure 21-8. integration accumulator register high (itgacc) module base + 0x0007 76543210 r itgacc w reset 0 0 0 00000 figure 21-9. integration accumulator register low (itgacc)
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 710 freescale semiconductor this 16-bit ?ld is signed and is represented in twos complement. it indicates the change in ?x while integrating the back emf present in the non-driven coil during a return to zero event. when itg is zero, the accumulator is initialized to 0x0000 and the sigma-delta converter is in a reset state. when itg is one, the accumulator increments or decrements depending on the sigma-delta conversion sample. the accumulator sample frequency is determined by the aclks ?ld. the accumulator freezes at 0x7fff on a positive over?w and freezes at 0x8000 on a negative over?w. 21.4 functional description the stepper stall detector (ssd) has a simple control block to con?ure the h-bridge drivers of a stepper motor in four different full step states with four available modes during a return to zero event. the ssd has a detect circuit using a sigma-delta converter to measure and integrate changes in ?x of the de-energized winding in the stepping motor and the conversion result is accumulated in a 16-bit signed register. the ssd also has a 16-bit modulus down counter to monitor blanking and integration times. dc offset compensation is implemented when using the modulus down counter to monitor integration times. 21.4.1 return to zero modes there are four return to zero modes as shown in table 21-11 . 21.4.1.1 blanking with no drive in blanking mode with no drive, one of the coils is masked from the sigma-delta converter, and if rtz is enabled (rtze = 1), it is set up to recirculate its current. if rtz is enabled (rtze = 1), the other coil is disconnected to prevent any loss of ?x change that would occur when the motor starts moving before the end of recirculation and start of integration. in blanking mode with no drive, the accumulator is initialized to 0x0000 and the converter is in a reset state. 21.4.1.2 blanking with drive in blanking mode with drive, one of the coils is masked from the sigma-delta converter, and if rtz is enabled (rtze = 1), it is set up to recirculate its current. if rtz is enabled (rtze = 1), the other coil is driven. in blanking mode with drive, the accumulator is initialized to 0x0000 and the converter is in a reset state. table 21-11. return to zero modes itg dcoil mode 0 0 blanking with no drive 0 1 blanking with drive 1 0 conversion 1 1 integration
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 711 21.4.1.3 conversion in conversion mode, one of the coils is routed for integration with one end connected to the (non-zero) reference input and the other end connected to the integrator input of the sigma-delta converter. if rtz is enabled (rtze=1), both coils are disconnected. this mode is not useful for stall detection. 21.4.1.4 integration in integration mode, one of the coils is routed for integration with one end connected to the (non-zero) reference input and the other end connected to the integrator input of the sigma-delta converter. if rtz is enabled (rtze = 1), the other coil is driven. this mode is used to rectify and integrate the back emf produced by the coils to detect stepped rotary motion. dc offset compensation is implemented when using the modulus down counter to monitor integration time. 21.4.2 full step states during a return to zero (rtz) event, the stepper motor pointer requires a 90 full motor electrical step with full amplitude pulses applied to each phase in turn. for counter clockwise rotation (ccw), the step value is incremented 0, 1, 2, 3, 0 and so on, and for a clockwise rotation the step value is decremented 3, 2, 1, 0 and so on. figure 21-10 shows the current level through each coil for each full step in ccw rotation when dcoil is set. figure 21-10. full steps (ccw) figure 21-11 shows the current ?w in the sinx and cosx h-bridges when step = 0, dcoil = 1, itg = 0 and rcir = 0. 0 1 2 3 0 imax + _ imax 0 imax + _ imax sine coil current cosine coil current recirculation
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 712 freescale semiconductor figure 21-11. current flow when step = 0, dcoil = 1, itg = 0, rcir = 0 figure 21-12 shows the current ?w in the sinx and cosx h-bridges when step = 1, dcoil = 1, itg = 0 and rcir = 1. figure 21-12. current flow when step = 1, dcoil = 1, itg = 0, rcir = 1 figure 21-13 shows the current ?w in the sinx and cosx h-bridges when step = 2, dcoil = 1 and itg = 1. vddm cosxp cosxm t1 t2 t3 t4 vssm vddm sinxp sinxm t5 t6 t7 t8 vssm vddm cosxp cosxm t1 t2 t3 t4 vssm vddm sinxp sinxm t5 t6 t7 t8 vssm
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 713 figure 21-13. current ?w when step = 2, dcoil = 1, itg = 1 figure 21-14 shows the current ?w in the sinx and cosx h-bridges when step = 3, dcoil = 1 and itg = 1. figure 21-14. current ?w when step = 3, dcoil = 1, itg = 1 vddm cosxp cosxm t1 t2 t3 t4 vssm vddm sinxp sinxm t5 t6 t7 t8 vssm vddm cosxp cosxm t1 t2 t3 t4 vssm vddm sinxp sinxm t5 t6 t7 t8 vssm
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 714 freescale semiconductor 21.4.3 operation in low power modes the ssd block can be con?ured for lower mcu power consumption in three different ways. stop mode powers down the sigma-delta converter and halts clock to the modulus counter. exit from stop enables the sigma-delta converter and the clock to the modulus counter but due to the converter recovery time, the integration result should be ignored. wait mode with ssdwai bit set powers down the sigma-delta converter and halts the clock to the modulus counter. exit from wait enables the sigma-delta converter and clock to the modulus counter but due to the converter recovery time, the integration result should be ignored. clearing sdcpu bit powers down the sigma-delta converter. 21.4.4 stall detection flow figure 21-15 shows a ?wchart and software setup for stall detection of a stepper motor. to control a second stepper motor, the sms bit must be toggled during the ssd initialization.
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 715 figure 21-15. return-to-zero flowchart advance pointer initialize ssd start blanking start integration disable ssd end of blanking? end of integration? stall detection? using motor control module, drive pointer to within 3 full steps of calibrated zero position. 1. clear (or set) rcir; clear (or set) pol; clear (or set) sms; 2. set mczie; clear modmc; clear (or set) pre; set mcen. 3. set rtze; set sdcpu; write aclks (select sample frequency). 4. store threshold value in ram. 1. clear mczif. 2. write mdccnt with blanking time value. 3. clear itg; clear (or set) dcoil; increment (or decrement) step for ccw (or cw) motion. mdccnt = 0x0000? or mczif = 1? 1. clear mczif. 2. write mdccnt with integration time value. 3. set itg; set dcoil. mdccnt = 0x0000? or mczif = 1? yes no yes no itgacc < threshold (ram value)? 1. clear mczif. 2. clear mcen. 3. clear itg. 4. clear rtze; clear sdcpu. yes no
stepper stall detector (ssdv1) block description mc9s12xhy-family reference manual, rev. 1.01 716 freescale semiconductor
mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 717 appendix a electrical characteristics a.1 general note the electrical characteristics given in this section should be used as a guide only. values cannot be guaranteed by freescale and are subject to change without notice. data are currently based on characterization data of mc9s12xhymaterial only unless marked differently. this supplement contains the most accurate electrical information for the 9s12xhy family microcontroller available at the time of publication. this introduction is intended to give an overview on several common topics like power supply, current injection etc. a.1.1 parameter classi?ation the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following classi?ation is used and the parameters are tagged accordingly in the tables where appropriate. note this classi?ation is shown in the column labeled ??in the parameter tables where appropriate. p: those parameters are guaranteed during production testing on each individual device. c: those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t: those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d: those parameters are derived mainly from simulations. a.1.2 power supply the 9s12xhy family utilizes several pins to supply power to the i/o ports, a/d converter, oscillator, and pll as well as the digital core. the vdda, vssa pin pairs supply the a/d converter and parts of the internal voltage regulator.
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 718 freescale semiconductor the vddx, vssx pin pairs [2:1] supply the i/o pins. the vddm, vssm pin pairs [2:1] supply the pu/pv i/o pins. vddr supplies the internal voltage regulator. vddpll, vsspll pin pair supply the oscillator and the pll. vss1, vss2 and vss3 are internally connected by metal. all vddx pins are internally connected by metal. all vssx pins are internally connected by metal. vdda is connected to all vddx pins by diodes for esd protection. vddx must not exceed vdda by more than a diode voltage drop. vdda must not exceed vddx by more than a diode drop. vssa and vssx are connected by anti-parallel diodes for esd protection. note in the following context v dd35 is used for either vdda, vddr, and vddx; v ss35 is used for either vssa and vssx unless otherwise noted. i dd35 denotes the sum of the currents ?wing into the vdda and vddr pins. the run mode current in the vddx domain is external load dependent. v dd is used for vdd, v ss is used for vss1, vss2 and vss3. v ddpll is used for vddpll, v sspll is used for vsspll i dd is used for the sum of the currents ?wing into vdd, vddf and vddpll. a.1.3 pins there are four groups of functional pins. a.1.3.1 i/o pins the i/o pins have a level in the range of 4.5v to 5.5v. this class of pins is comprised of all port i/o pins, the analog inputs, bkgd and the reset pins. some functionality may be disabled. for example the bkgd pin pull up is always enabled. a.1.3.2 analog reference this group is made up by the vdda/v rh and vssa/v rl pins. a.1.3.3 oscillator the pins extal, xtal dedicated to the oscillator have a nominal 1.8v level. they are supplied by vddpll.
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 719 a.1.3.4 test this pin is used for production testing only. the test pin must be tied to v ss in all applications. a.1.4 current injection power supply must maintain regulation within operating v dd35 or v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd35 ) is greater than i dd35 , the injection current may ?w out of v dd35 and could result in external power supply going out of regulation. ensure external v dd35 load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power; e.g., if no system clock is present, or if clock rate is very low which would reduce overall power consumption. a.1.5 absolute maximum ratings absolute maximum ratings are stress ratings only. a functional operation under or outside those maxima is not guaranteed. stress beyond those limits may affect the reliability or cause permanent damage of the device. this device contains circuitry protecting against damage due to high static voltage or electrical ?lds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss35 or v dd35 ).
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 720 freescale semiconductor a.1.6 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test quali?ation for automotive grade integrated circuits. during the device quali?ation esd stresses were performed for the human body model (hbm) and the charge device model. a device will be de?ed as a failure if after exposure to esd pulses the device no longer meets the device speci?ation. complete dc parametric and functional testing is performed per the applicable device speci?ation at room temperature followed by hot temperature, unless speci?d otherwise in the device speci?ation. table a-1. absolute maximum ratings 1 1 beyond absolute maximum ratings device might be damaged. num rating symbol min max unit 1 i/o, regulator and analog supply voltage v dd35 ?.3 6.0 v 2 digital logic supply voltage 2 2 the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. v dd ?.3 2.16 v 3 pll supply voltage 2 v ddpll ?.3 2.16 v 4 nvm supply voltage 2 v ddf ?.3 3.6 v 5 voltage difference v ddx to v dda ? vddx -0.3 0.3 v 6 voltage difference v ssx to v ssa ? vssx ?.3 0.3 v 5 voltage difference v ddm1,2 to v dda ? vddma ?.3 0.3 v 6 voltage difference v ssm1,2 to v ssa ? vssma ?.3 0.3 v 7 digital i/o input voltage v in ?.3 6.0 v 8 analog reference v rh, v rl ?.3 6.0 v 9 extal, xtal v ilv ?.3 2.16 v 11 instantaneous maximum current single pin limit for all digital i/o pins 3 3 all digital i/o pins are internally clamped to v ssx and v ddx , or v ssa and v dda . i d ?5 +25 ma 12 instantaneous maximum current single pin limit for extal, xtal 4 4 those pins are internally clamped to v sspll and v ddpll . i dl ?5 +25 ma 14 maximum current single pin limit for power supply pins i dv ?00 +100 ma 15 storage temperature range t stg ?5 155 c
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 721 a.1.7 operating conditions this section describes the operating conditions of the device. unless otherwise noted those conditions apply to all the following data. note please refer to the temperature rating of the device (c, v, m) with regards to the ambient temperature t a and the junction temperature t j . for power dissipation calculations refer to section a.1.8, ?ower dissipation and thermal characteristics . table a-2. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ohm storage capacitance c 100 pf number of pulse per pin positive negative 1 1 charged device number of pulse per pin positive negative 3 3 latch-up minimum input voltage limit ?.5 v maximum input voltage limit 7.5 v table a-3. esd and latch-up protection characteristics num c rating symbol min max unit 1 c human body model (hbm) v hbm 2000 v 2 c charge device model (cdm) corner pins charge device model (cdm) edge pins v cdm 750 500 v 3 c latch-up current at t a = 125 c positive negative i lat +100 ?00 ma 4 c latch-up current at t a = 27 c positive negative i lat +200 ?00 ma table a-4. operating conditions rating symbol min typ max unit i/o, regulator and analog supply voltage v dd35 3.13 1 5 5.5 v nvm logic supply voltage 2 v ddf 2.7 2.8 2.9 v voltage difference v ddx to v dda to v ddm ? vddx refer to table a-12
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 722 freescale semiconductor note using the internal voltage regulator, operation is guaranteed in a power down until a low voltage reset assertion. a.1.8 power dissipation and thermal characteristics power dissipation and thermal characteristics are closely related. the user must assure that the maximum operating junction temperature is not exceeded. the average chip-junction temperature (t j ) in c can be obtained from: voltage difference v ddr to v ddx ? vddr -0.1 0 0.1 v voltage difference v lcd to v ddx ? vlcdvddr - - 0.25 v voltage difference v lcd to v ssx ? vlcdvssx -0.25 - - v voltage difference v ssx to v ssa ? vssx refer to table a-12 voltage difference v ss1 , v ss2 , v ss3 , v sspll to v ssx ? vss -0.1 0 0.1 v digital logic supply voltage 2 v dd 1.72 1.8 1.98 v pll supply voltage v ddpll 1.72 1.8 1.98 v oscillator 3 (loop controlled pierce) f osc 4 16 mhz bus frequency 4 f bus 0.5 40 mhz temperature option c operating junction temperature range operating ambient temperature range 5 t j t a ?0 ?0 27 85 c temperature option v operating junction temperature range operating ambient temperature range 5 t j t a ?0 ?0 27 105 c temperature option m operating junction temperature range operating ambient temperature range 5 t j t a ?0 ?0 27 150 125 c 1 lcd/motor driver pad can only be work under >4.5v 2 the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. 3 this refers to the oscillator base frequency. typical crystal & resonator tolerances are supported. 4 please refer to table a-22 for maximum bus frequency limits with frequency modulation enabled 5 please refer to section a.1.8, ?ower dissipation and thermal characteristics for more details about the relation between ambient temperature t a and device junction temperature t j . table a-4. operating conditions t j t a p d ja ? () + = t j junction temperature, [ c ] = t a ambient temperature, [ c ] = p d total chip power dissipation, [w] = ja package thermal resistance, [ c/w] =
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 723 the total power dissipation can be calculated from: p io is the sum of all output currents on i/o ports associated with v ddx , whereby two cases with internal voltage regulator enabled and disabled must be considered: 1. internal voltage regulator disabled 2. internal voltage regulator enabled p d p int p io + = p int chip internal power dissipation, [w] = p io r dson i i io i 2 ? = r dson v ol i ol ------------ for outputs driven low ; = r dson v dd 35 v oh i oh -------------------------------------- for outputs driven high ; = p int i dd v dd ? i ddpll v ddpll ? i dda +v dda ? + = p int i ddr v ddr ? i dda v dda ? + =
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 724 freescale semiconductor a.1.9 i/o characteristics this section describes the characteristics of all i/o pins except extal, xtal, test and supply pins. table a-5. thermal package characteristics (mc9s12xhy) 1 1 the values for thermal resistance are achieved by package simulations num c rating symbol min typ max unit lqfp 112 1 d junction to ambient 2 , natural convection single layer board(1s) 2 junction-to-ambient thermal resistance determined per jedec jesd51-2 and jesd51-6. thermal test board meets jedec speci?ation for this package. ja 59 c/w 2 d junction to ambient, natural convection four layer board (2s2p) ja 49 c/w 3 d junction to ambient,(@200 ft/min) single layer board(1s) jma 50 c/w 4 d junction to ambient, (@200 ft/min) four layer board (2s2p) jma 43 c/w 5 d junction to board 3 3 junction-to-board thermal resistance determined per jedec jesd51-8. thermal test board meets jedec speci?ation for the speci?d package. jb 37 c/w 6 d junction to case 4 4 junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer jctop 14 c/w 7 d junction to package top 5 5 thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt jt 2 c/w lqfp 100 8 d junction to ambient, natural convection single layer board(1s) ja 60 c/w 9 d junction to ambient, natural convection four layer board (2s2p) ja 47 c/w 10 d junction to ambient,(@200 ft/min) single layer board(1s) jma 50 c/w 11 d junction to ambient, (@200 ft/min) four layer board (2s2p) jma 41 c/w 12 d junction to board jb 33 c/w 13 d junction to case jctop 14 c/w 14 d junction to package top jt 2 c/w
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 725 table a-6. 5-v i/o characteristics conditions are 4.5 v < v dd35 < 5.5 v junction temperature from ?0 c to +150 c, unless otherwise noted i/o characteristics for all i/o pins except extal, xtal,test and supply pins. num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd35 v t input high voltage v ih v dd35 + 0.3 v 2 p input low voltage v il 0.35*v dd35 v t input low voltage v il v ss35 ?0.3 v 3 t input hysteresis v hys 250 mv 4a p input leakage current (pins in high impedance input mode) 1 all except pu/pv v in = v dd35 or v ss35 m temperature range -40 c to 150 c i in -1 1 a p input leakage current (pins in high impedance input mode) 2 . pu/pv v in = v dd35 or v ss35 m temperature range -40 c to 150 c i in -1 1 a 4b c input leakage current (pins in high impedance input mode) all except pu/pv v in = v dd35 or v ss35 25 c 150 c i in 1 26 ?a c input leakage current (pins in high impedance input mode) pu/pv v in = v dd35 or v ss35 25 c 150 c i in 1 270 ?a 6 p output high voltage (pins in output mode) all except pu/pv full drive i oh = -4ma v oh v dd35 ?0.8 v p output high voltage (pins in output mode) pu/pv full drive i oh = ?0 ma v oh v ddm ?0.4 v 8 p output low voltage (pins in output mode) all except pu/pv full drive i ol = +4 ma v ol 0.8 v p output low voltage (pins in output mode) pu/pv full drive i ol = +20 ma v ol 0.4 v 9 c port u, v output rise time v dd5 =5v, 10% to 90% of v oh cload 4.7nf connected to gnd, slew disabled rload=1k ? connected to gnd, slew enabled rload=1k ? connected to vdd, slew enabled t r 126 149 134 ns 10 c port u, v output fall time v dd5 =5v, 10% to 90% of v oh cload 4.7nf connected to gnd, slew disabled rload=1k ? connected to gnd, slew enabled rload=1k ? connected to vdd,, slew enabled t f 102 131 146 ?s ns
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 726 freescale semiconductor a.1.10 supply currents this section describes the current consumption characteristics of the device as well as the conditions for the measurements. a.1.10.1 typical run current measurement conditions run current is measured on vddr and vdda pin. it does not include the current to drive external loads.since the current consumption of the output drivers is load dependent, all measurements are without output loads and with minimum i/o activity. the currents are measured in single chip mode, s12xcpu code is executed from flash. v dd35 =5v, internal voltage regulator is enabled and the bus frequency is 40mhz using a 4mhz oscillator in loop controlled pierce mode. since the dbg and bdm modules are typically not used in the end application, the supply current values for these modules is not speci?d. an overhead of current consumption exists independent of the listed modules, due to voltage regulation and clock logic that is not dedicated to a speci? module. this is listed in the table row named ?verhead? 11 p internal pull up device resistance all except pu/pv v ih min > input voltage > v il max r pul 25 90 k ? p internal pull up device current pu/pv v ih min > input voltage > v il max i pul -10 -130 a 12 p internal pull down device resistance all except pu/pv v ih min > input voltage > v il max r pdh 25 90 k ? p internal pull down device current pu/pv v ih min > input voltage > v il max i pdh 10 130 a 13 d input capacitance c in ?pf 14 t injection current 3 single pin limit total device limit, sum of all injected currents i ics i icp ?.5 ?5 2.5 25 ma 15 p port t, s, r,ad interrupt input pulse ?tered (stop) 4 t pulse 3 s 16 p port t, s, adinterrupt input pulse passed (stop) 3 t pulse 10 s 17 p port t, s, r,ad interrupt input pulse ?tered (stop) 5 t pulse 3 tcyc 18 p port t, s, adinterrupt input pulse passed (stop) 3 t pulse 4 tcyc 19 d irq pulse width, edge-sensitive mode ( st op) pw irq 1 tcyc 20 d xirq pulse width with x-bit set (stop) pw xirq 4 tosc 1 maximum leakage current occurs at maximum operating temperature. 2 maximum leakage current occurs at maximum operating temperature. 3 refer to section a.1.4, ?urrent injection for more details 4 parameter only applies in stop or pseudo stop mode. 5 parameter only applies in stop or pseudo stop mode. table a-6. 5-v i/o characteristics conditions are 4.5 v < v dd35 < 5.5 v junction temperature from ?0 c to +150 c, unless otherwise noted i/o characteristics for all i/o pins except extal, xtal,test and supply pins.
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 727 table a-7 shows the con?uration of the peripherals for typical run current. a.1.10.2 maximum run current measurement conditions run current is measured on vddr and vdda pin. it does not include the current to drive external loads.currents are measured in single chip mode, s12xcpu with v dd35 =5.5v, internal voltage regulator enabled and a 40mhz bus frequency from a 4mhz input. characterized parameters are derived using a 4mhz loop controlled pierce oscillator. production test parameters are tested with a 4mhz square wave oscillator. table a-7. module con?urations for typical run supply (vddr+vdda) current v dd35 =5v peripheral con?uration s12xcpu 420 cycle loop: 384 dbne cycles plus subroutine entry to stimulate stacking (ram access) cop & rti enabled. cop running at the rate 224, rti control register(rtictl) set to $7f pll enabled and con?ured to supply the part with the maximum speci?d bus frequency (80 mhz). dbg the module is enabled and the comparators are con?ured to trigger in outside range.the range covers all the code executed by the core,the tracing is disabled.. can0,can1 con?ured to loop-back mode using a bit rate of 500kbit/s spi con?ured to master mode, continuously transmit data (0x55 or 0xaa) at 1mbit/s sci0,sci1 con?ured into loop mode, with the break detection and collision detection features enabled, continuously transmit data (0x55) at speed of 19200 baud pwm con?ured to toggle its pins at the rate of 1khz iic operate in master mode and continuously transimit data(0x55 or 0xaa) at 100kbits/s lcd con?ured to 244hz frame frequency, 1/4 duty, 1/3 bias with all fp/bp enabled and all segment on mc con?ured to full h-bridge mode mcper=0x3ff, 1/2fbus motor controller timer counter clock, mcdc=0x20 ssd disabled tim0,tim1 the peripheral shall be con?ured in output compare mode. pulse accumulator and modulus counter enabled. atd the peripheral is con?ured to operate at its maximum speci?d frequency and to continuously convert voltages on all input channels in sequence. overhead vreg supplying 1.8v from a 5v input voltage, pll on
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 728 freescale semiconductor table a-8 shows the con?uration of the peripherals for maximum run current a.1.10.3 stop current conditions unbonded ports must be correctly initialized to prevent current consumption due to ?ating inputs. typical stop current is measured with v dd35 =5v, maximum stop current is measured with v dd35 =5.5v. pseudo stop currents are measured with the oscillator con?ured for 4mhz lcp mode. production test parameters are tested with a 4mhz square wave oscillator. a.1.10.4 measurement results table a-8. module con?urations for maximum run supply (vddr+vdda) current v dd35 =5.5v peripheral con?uration s12xcpu 420 cycle loop: 384 dbne cycles plus subroutine entry to stimulate stacking (ram access) cop & rti enabled. cop running at the rate 224, rti control register(rtictl) set to $7f pll enabled and con?ured to supply the part with the maximum speci?d bus frequency (80 mhz). dbg the module is enabled and the comparators are con?ured to trigger in outside range.the range covers all the code executed by the core,the tracing is disabled.. can0,can1 con?ured to loop-back mode using a bit rate of 1mbit/s spi con?ured to master mode, continuously transmit data (0x55 or 0xaa) at 1mbit/s sci0,sci1 con?ured into loop mode, with the break detection and collision detection features enabled, continuously transmit data (0x55) at speed of 57600 baud pwm con?ured to toggle its pins at the rate of 40khz iic operate in master mode and continuously transimit data(0x55 or 0xaa) at 100kbits/s lcd con?ured to 976hz frame frequency, 1/4 duty, 1/3 bias with all fp/bp enabled and all segment on mc con?ured to full h-bridge mode mcper=0x3ff, 1/2fbus motor controller timer counter clock, mcdc=0x20 ssd disabled tim0,tim1 the peripheral shall be con?ured in output compare mode. pulse accumulator and modulus counter enabled. atd the peripheral is con?ured to operate at its maximum speci?d frequency and to continuously convert voltages on all input channels in sequence. overhead vreg supplying 1.8v from a 5v input voltage, pll on
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 729 table a-9. module run supply currents table a-10. run and wait current characteristics conditions are shown in table a-7 at ambient temperature unless otherwise noted num c rating min typ max unit 1 t s12xcpu 5.9 ma 2 t mscan 0.7 3 t spi 0.3 4 t sci 0.1 5 t pwm 0.4 6 t iic 0.2 7 t lcd 0.3 8 t mc 0.4 9 t ssd 0.7 10 t tim 0.3 11 t atd 0.7 12 t overhead 10.7 conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit run supply current (no external load, peripheral con?uration see table a-8.) 1 p peripheral set 1 f osc =4mhz, f bus =40mhz i dd35 24.9 31.9 ma wait supply current 2 p peripheral set 1 ,pll on i ddw 16.35 19.9 ma
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 730 freescale semiconductor table a-11. pseudo stop and full stop current conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit pseudo stop current (api, rti, cop, and lcd disabled) pll off, lcp mode 10a c c c ?0 c 25 c 150 c i ddps 170 200 460 a pseudo stop current (api, rti, cop, and lcd disabled) pll off, fsp mode 10b p p p ?0 c 25 c 150 c i ddps 32 35 287 50 62 480 a pseudo stop current (api, rti, and cop enabled , lcd disabled) pll off, lcp mode 11a c c c -40 c 25 c 150 c i ddps 180 220 500 a pseudo stop current (api, rti, and cop enabled , lcd disabled) pll off, fsp mode 11b c c c -40 c 25 c 150 c i ddps 460 530 910 a pseudo stop current (api, rti, and cop enabled, lcd enabled) pll off, lcp mode 12a c c c -40 c 25 c 150 c i ddps 210 240 530 a pseudo stop current (api, rti, and cop enabled, lcd enabled) pll off, fsp mode 12b p p p -40 c 25 c 150 c i ddps 74 83 349 110 115 550 a stop current 13 p p p ?0 c 25 c 150 c i dds 16 19 205 30 32 360 a stop current (api active) 14 t t t ?0 c 25 c 150 c i dds 17 22 250 a stop current (atd active) 15 t t t -40 c 25 c 150 c i dds 230 256 520 a
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 731 a.2 atd characteristics this section describes the characteristics of the analog-to-digital converter. a.2.1 atd operating characteristics the table a-12 and table a-13 show conditions under which the atd operates. the following constraints exist to obtain full-scale, full range results: v ssa v rl v in v rh v dda . this constraint exists since the sample buffer ampli?r can not drive beyond the power supply levels that it ties to. if the input level goes outside of this range it will effectively be clipped. table a-12. atd operating characteristics a.2.2 factors in?encing accuracy source resistance, source capacitance and current injection have an in?ence on the accuracy of the atd. a further factor is that portad pins that are con?ured as output drivers switching. a.2.2.1 port ad output drivers switching portad output drivers switching can adversely affect the atd accuracy whilst converting the analog voltage on other portad pins because the output drivers are supplied from the vdda/vssa atd supply pins. although internal design measures are implemented to minimize the affect of output driver noise, it conditions are shown in table a-4 unless otherwise noted, supply voltage 3.13 v < v dda < 5.5 v num c rating symbol min typ max unit 1 d reference potential low high v rl v rh v ssa v dda /2 v dda /2 v dda v v 2 d voltage difference v ddx to v dda ? vddx ?.35 0 0.1 v 3 d voltage difference v ssx to v ssa ? vssx ?.1 0 0.1 v 4 c differential reference voltage 1 1 full accuracy is not guaranteed when differential voltage is less than 4.50 v v rh -v rl 3.13 5.0 5.5 v 5 c atd clock frequency (derived from bus clock via the prescaler bus) f atdclk 0.25 8.3 mhz 6 p atd clock frequency in stop mode (internal generated temperature and voltage dependent clock, iclk) 0.6 1 1.7 mhz 7 d adc conversion in stop, recovery time 2 2 when converting in stop mode (iclkstp=1) an atd stop recovery time tatdstprcv is required to switch back to bus clock based atdclk when leaving stop mode. do not access atd registers during this time. t atdstprcv 1.5 s 8d atd conversion period 3 10 bit resolution: 8 bit resolution: 3 the minimum time assumes a sample time of 4 atd clock cycles. the maximum time assumes a sample time of 24 atd clock cycles and the discharge feature (smp_dis) enabled, which adds 2 atd clock cycles. n conv10 n conv8 19 17 41 39 at d clock cycles
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 732 freescale semiconductor is recommended to con?ure portad pins as outputs only for low frequency, low load outputs. the impact on atd accuracy is load dependent and not speci?d. the values speci?d are valid under condition that no portad output drivers switch during conversion. a.2.2.2 source resistance due to the input pin leakage current as speci?d in table a-7 and table a-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the atd input. the maximum source resistance r s speci?s results in an error (10-bit resolution) of less than 1/2 lsb (2.5 mv) at the maximum leakage current. if device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance of up to 10kohm are allowed. a.2.2.3 source capacitance when sampling an additional internal capacitor is switched to the input. this can cause a voltage drop due to charge sharing with the external and the pin capacitance. for a maximum sampling error of the input voltage 1lsb (10-bit resilution), then the external ?ter capacitor, c f 1024 * (c ins ? inn ). a.2.2.4 current injection there are two cases to consider. 1. a current is injected into the channel being converted. the channel being stressed has conversion values of $3ff (in 10-bit mode) for analog inputs greater than v rh and $000 for values less than v rl unless the current is higher than speci?d as disruptive condition. 2. current is injected into pins in the neighborhood of the channel being converted. a portion of this current is picked up by the channel (coupling ratio k), this additional current impacts the accuracy of the conversion depending on the source resistance. the additional input voltage error on the converted channel can be calculated as: v err = k * r s * i inj with i inj being the sum of the currents injected into the two pins adjacent to the converted channel.
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 733 a.2.3 atd accuracy table a-14 and table a-15 specifies the atd conversion performance excluding any errors due to current injection, input capacitance and source resistance. table a-13. atd electrical characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 c max input source resistance 1 1 refer to a.2.2.2 for further information concerning source resistance r s 1k ? 2 d total input capacitance non sampling total input capacitance sampling c inn c ins 10 16 pf 3 d input internal resistance r ina 5 15 k ? 4 c disruptive analog input current i na ?.5 2.5 ma 5 c coupling ratio positive current injection k p 1e-4 a/a 6 c coupling ratio negative current injection k n 3e-3 a/a
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 734 freescale semiconductor a.2.3.1 atd accuracy de?itions for the following de?itions see also figure a-1 . differential non-linearity (dnl) is de?ed as the difference between two adjacent switching steps. the integral non-linearity (inl) is de?ed as the sum of all dnls: dnl i () v i v i1 1lsb -------------------------- - 1 = inl n () dnl i () i1 = n v n v 0 1lsb -------------------- - n ==
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 735 figure a-1. atd accuracy de?itions note figure a-1 shows only de?itions, for speci?ation values refer to table a- 14 and table a-15 . 1 5 vin mv 10 15 20 25 30 35 40 85 90 95 100 105 110 115 120 65 70 75 80 60 0 3 2 5 4 7 6 45 $3f7 $3f9 $3f8 $3fb $3fa $3fd $3fc $3fe $3ff $3f4 $3f6 $3f5 8 9 1 2 $ff $fe $fd $3f3 10-bit resolution 8-bit resolution ideal transfer curve 10-bit transfer curve 8-bit transfer curve 55 10-bit absolute error boundary 8-bit absolute error boundary lsb vi-1 vi dnl 5000 +
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 736 freescale semiconductor table a-14. atd conversion performance 5v range table a-15. atd conversion performance 3.3v range a.3 nvm, flash a.3.1 timing parameters the time base for all nvm program or erase operations is derived from the oscillator. a minimum oscillator frequency f nvmosc is required for performing program or erase operations. the nvm modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the speci?d minimum. when attempting to program or erase the nvm modules at a lower frequency, a full program or erase transition is not assured. the program and erase operations are timed using a clock derived from the oscillator using the fclkdiv register. the frequency of this clock must be set within the limits speci?d as f nvmop . conditions are shown in table a-4. unless otherwise noted. v ref = v rh - v rl = 5.12v. f atdclk = 8.0mhz the values are tested to be valid with no portad output drivers switching simultaneous with conversions. num c rating 1 , 2 1 the 8-bit and 10-bit mode operation is structurally tested in production test. absolute values are tested in 12-bit mode. 2 better performance is possible using specially designed multi-layer pcbs or averaging techniques. symbol min typ max unit 1 p resolution 10-bit lsb 5 mv 2 p differential nonlinearity 10-bit dnl -1 0.5 1 counts 3 p integral nonlinearity 10-bit inl -2 1 2 counts 4 p absolute error 3 10-bit ae -3 2 3 counts 5 c resolution 8-bit lsb 20 mv 6 c differential nonlinearity 8-bit dnl -0.5 0.3 0.5 counts 7 c integral nonlinearity 8-bit inl -1 0.5 1 counts 8 c absolute error 3 8-bit ae -1.5 1 1.5 counts conditions are shown in table a-4. unless otherwise noted. v ref = v rh - v rl = 3.3v. f atdclk = 8.0mhz the values are tested to be valid with no portad output drivers switching simultaneous with conversions. num c rating 1 , 2 1 the 8-bit and 10-bit mode operation is structurally tested in production test. absolute values are tested in 12-bit mode. 2 better performance is possible using specially designed multi-layer pcbs or averaging techniques. symbol min typ max unit 1 p resolution 10-bit lsb 3.22 mv 2 p differential nonlinearity 10-bit dnl -1.5 1 1.5 counts 3 p integral nonlinearity 10-bit inl -2 1 2 counts 4 p absolute error 3 10-bit ae -3 2 3 counts 5 c resolution 8-bit lsb 12.89 mv 6 c differential nonlinearity 8-bit dnl -0.5 0.3 0.5 counts 7 c integral nonlinearity 8-bit inl -1 0.5 1 counts 8 c absolute error 3 8-bit ae -1.5 1 1.5 counts
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 737 the minimum program and erase times shown in table a-16 are calculated for maximum f nvmop and maximum f nvmbus unless otherwise shown. the maximum times are calculated for minimum f nvmop a.3.1.1 erase verify all blocks (blank check) (fcmd=0x01) the time it takes to perform a blank check is dependant on the location of the ?st non-blank word starting at relative address zero. it takes one bus cycle per phrase to verify plus a setup of the command. assuming that no non blank location is found, then the erase verify all blocks is given by. a.3.1.2 erase verify block (blank check) (fcmd=0x02) the time it takes to perform a blank check is dependant on the location of the ?st non-blank word starting at relative address zero. it takes one bus cycle per phrase to verify plus a setup of the command. assuming that no non blank location is found, then the erase verify time for a single 256k nvm array is given by for a 128k nvm or d-flash array the erase verify time is given by a.3.1.3 erase verify p-flash section (fcmd=0x03) the maximum time depends on the number of phrases being veri?d (n vp ) a.3.1.4 read once (fcmd=0x04) the maximum read once time is given by a.3.1.5 program p-flash (fcmd=0x06) the programming time for a single phrase of four p-flash words + associated eight ecc bits is dependant on the bus frequency as a well as on the frequency f nvmop and can be calculated according to the following formulas. t check 33500 1 f nvmbus --------------------- ? = t check 33500 1 f nvmbus --------------------- ? = t check 17200 1 f nvmbus --------------------- ? = t check 752 n vp + () 1 f nvmbus --------------------- ? = t 400 () 1 f nvmbus --------------------- ? =
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 738 freescale semiconductor the typical phrase programming time can be calculated using the following equation the maximum phrase programming time can be calculated using the following equation a.3.1.6 p-flash program once (fcmd=0x07) the maximum p-flash program once time is given by a.3.1.7 erase all blocks (fcmd=0x08) erasing all blocks takes: t bwpgm 128 1 f nvmop ------------------------- 1725 1 f nvmbus ---------------------------- - ? + ? = t bwpgm 130 1 f nvmop ------------------------- 2125 1 f nvmbus ---------------------------- - ? + ? = t bwpgm 162 1 f nvmop ------------------------ - 2400 1 f nvmbus ---------------------------- ? + ? t mass 100100 1 f nvmop ------------------------ - 35000 1 f nvmbus ---------------------------- ? + ?
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 739 a.3.1.8 erase p-flash block (fcmd=0x09) erasing a 256k nvm block takes erasing a 128k nvm block takes a.3.1.9 erase p-flash sector (fcmd=0x0a) the typical time to erase a1024-byte p-flash sector can be calculated using the maximum time to erase a1024-byte p-flash sector can be calculated using a.3.1.10 unsecure flash (fcmd=0x0b) the maximum time for unsecuring the ?sh is given by a.3.1.11 verify backdoor access key (fcmd=0x0c) the maximum verify backdoor access key time is given by a.3.1.12 set user margin level (fcmd=0x0d) the maximum set user margin level time is given by a.3.1.13 set field margin level (fcmd=0x0e) the maximum set ?ld margin level time is given by t mass 100100 1 f nvmop ------------------------ - 70000 1 f nvmbus ---------------------------- ? + ? t mass 100100 1 f nvmop ------------------------ - 35000 1 f nvmbus ---------------------------- ? + ? t era 20020 1 f nvmop ------------------ - ? ?? ?? 700 1 f nvmbus --------------------- ? ?? ?? + = t era 20020 1 f nvmop ------------------ - ? ?? ?? 1100 1 f nvmbus --------------------- ? ?? ?? + = t uns 100100 1 f nvmop ------------------------ - 70000 1 f nvmbus ---------------------------- ? + ? ?? ?? = t 400 1 f nvmbus ---------------------------- ? = t 350 1 f nvmbus ---------------------------- ? =
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 740 freescale semiconductor a.3.1.14 erase verify d-flash section (fcmd=0x10) erase verify d-flash for a given number of words n w is given by . a.3.1.15 d-flash programming (fcmd=0x11) d-flash programming time is dependent on the number of words being programmed and their location with respect to a row boundary, because programming across a row boundary requires extra steps. the d- flash programming time is speci?d for different cases (1,2,3,4 words and 4 words across a row boundary) at a 40mhz bus frequency. the typical programming time can be calculated using the following equation, whereby n w denotes the number of words; bc=0 if no boundary is crossed and bc=1 if a boundary is crossed. the maximum programming time can be calculated using the following equation a.3.1.16 erase d-flash sector (fcmd=0x12) typical d-flash sector erase times are those expected on a new device, where no margin verify fails occur. they can be calculated using the following equation. maximum d-fash sector erase times can be calculated using the following equation. the d-flash sector erase time on a new device is ~5ms and can extend to 20ms as the ?sh is cycled. t 350 1 f nvmbus ---------------------------- ? = t check 840 n w + () 1 f nvmbus ---------------------------- ? t dpgm 15 54 n w ? () 16 bc ? () ++ () 1 f nvmop ------------------ - ? ?? ?? 460 640 n w ? () 500 bc ? () ++ () 1 f nvmbus --------------------- ? ?? ?? + = t dpgm 15 56 n w ? () 16 bc ? () ++ () 1 f nvmop ------------------ - ? ?? ?? 460 840 n w ? () 500 bc ? () ++ () 1 f nvmbus --------------------- ? ?? ?? + = t eradf 5025 1 f nvmop ------------------------ - 700 1 f nvmbus ---------------------------- ? + ? t eradf 20100 1 f nvmop ------------------------ - 3300 1 f nvmbus ---------------------------- ? + ?
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 741 table a-16. nvm timing characteristics a.3.2 nvm reliability parameters the reliability of the nvm blocks is guaranteed by stress test during quali?ation, constant process monitors and burn-in to screen early life failures. the data retention and program/erase cycling failure rates are speci?d at the operating conditions noted. the program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. the standard shipping condition for both the d-flash and p-flash memory is erased with security disabled. however it is recommended that each block or sector is erased before factory programming to ensure that the full data retention capability is achieved. data retention time is measured from the last erase operation. conditions are as shown in table a-4 , with 40mhz bus and f nvmop = 1mhz unless otherwise noted. num c rating symbol min typ max unit 1 d external oscillator clock f nvmosc 240 1 1 restrictions for oscillator in crystal mode apply. mhz 2 d bus frequency for programming or erase operations f nvmbus 1 40 mhz 3 d operating frequency f nvmop 800 1050 khz 4 d p-flash phrase programming t bwpgm 171 183 s 6 p p-flash sector erase time t era ?021ms 7 p erase all blocks (mass erase) time t mass 101 102 ms 7a d unsecure flash t uns 101 102 ms 8 d p-flash erase verify (blank check) time 2 2 valid for both ?rase verify all?or ?rase verify block?on 256k block without failing locations t check 33500 2 t cyc 9a d d-flash word programming 1 word t dpgm 97 104 s 9b d d-flash word programming 2 words t dpgm 167 181 s 9c d d-flash word programming 3 words t dpgm 237 258 s 9d d d-flash word programming 4 words t dpgm 307 335 s 9e d d-flash word programming 4 words crossing row boundary t dpgm 335 363 s 10 d d-flash sector erase time t eradf 5.2 3 3 this is a typical value for a new device 21 ms 11 d d-flash erase verify (blank check) time t check 17500 t cyc
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 742 freescale semiconductor table a-17. nvm reliability characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit p-flash array 1 c data retention at an average junction temperature of t javg = 85 c 1 after up to 10,000 program/erase cycles 1 t javg does not exceed 85 c in a typical temperature pro?e over the lifetime of a consumer, industrial or automotive application. t pnvmret 15 100 2 2 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale de?es typical data retention, please refer to engineering bulletin eb618 years 2 c data retention at an average junction temperature of t javg = 85 c 3 after less than 100 program/erase cycles 3 t javg does not exceed 85 c in a typical temperature pro?e over the lifetime of a consumer, industrial or automotive application. t pnvmret 20 100 2 years 3 c p-flash number of program/erase cycles (-40 c tj 150 c ) n pflpe 10k 100k 3 cycles d-flash array 4 c data retention at an average junction temperature of t javg = 85 c 3 after up to 50,000 program/erase cycles t dnvmret 5 100 2 years 5 c data retention at an average junction temperature of t javg = 85 c 3 after less than 10,000 program/erase cycles t dnvmret 10 100 2 years 6 c data retention at an average junction temperature of t javg = 85 c 3 after less than 100 program/erase cycles t dnvmret 20 100 2 years 7 c d-flash number of program/erase cycles (-40 c tj 150 c ) n dflpe 50k 500k 3 cycles
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 743 a.4 voltage regulator table a-18. voltage regulator electrical characteristics conditions are shown in table a-4 unless otherwise noted num c characteristic symbol min typical max unit 1 p input voltages v vddr,a 3.13 5.50 v 2p output voltage core full performance mode reduced power mode (mcu stop mode) v dd 1.72 1.84 1.60 1.98 v v 3p output voltage flash full performance mode reduced power mode (mcu stop mode) v ddf 2.60 2.82 2.20 2.90 v v 4p output voltage pll full performance mode reduced power mode (mcu stop mode) v ddpll 1.72 1.84 1.60 1.98 v v 5p low voltage interrupt 1 assert level deassert level 1 monitors vdda, active only in full performance mode. indicates i/o & adc performance degradation due to low supply voltage. v lvia v lvid 4.04 4.19 4.23 4.38 4.40 4.49 v v 6p vddx low voltage reset 23 assert level deassert level 2 device functionality is guaranteed on power down to the lvr assert level 3 monitors vddx, active only in full performance mode. mcu is monitored by the por in rpm (see figure a-2 ) v lvrxa v lvrxd 3.02 3.13 v v 7c trimmed api internal clock 4 ? f / f nominal 4 the api trimming bits must be set that the minimum period equals to 0.2 ms. df api -5 +5 % 8d the first period after enabling the counter by apife might be reduced by api start up delay t sdel 100 s 9 t temperature sensor slope dv ts 5.05 5.25 5.45 mv/ o c 10 t high temperature interrupt assert 5 assert (vreghttr=$88) deassert (vreghttr=$88) 5 a hysteresis is guaranteed by design t htia t htid 120 110 132 122 144 134 o c o c 11 p bandgap reference voltage v bg 1.13 1.21 1.32 v
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 744 freescale semiconductor a.5 output loads a.5.1 resistive loads the voltage regulator is intended to supply the internal logic and oscillator. it allows no external dc loads. a.5.2 capacitive loads the capacitive loads are speci?d in table a-19 . ceramic capacitors with x7r dielectricum are required. a.5.3 chip power-up and voltage drops lvi (low voltage interrupt), por (power-on reset) and lvrs (low voltage reset) handle chip power-up or drops of the supply voltage. their function is shown in figure a-2 . figure a-2. 9s12xhy family - chip power-up and voltage drops (not scaled) table a-19. 9s12xhy family - capacitive loads num characteristic symbol min recommended max unit 1 vdd/vddf external capacitive load c ddext 176 220 264 nf 3 vddpll external capacitive load c ddpllext 80 220 264 nf v lvid v lvia v lvrxd v lvrxa v pord lvi por lvrx t v v ddx lvi enabled lvi disabled due to lvr v dd
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 745 freescale semiconductor figure a-3. 9s12xhy family power sequencing during power sequencing v dda can be powered up before v ddr , v ddx . v ddr and v ddx must be powered up together adhering to the operating conditions differential. v rh power up must follow v dda to avoid current injection. v ddr, v dda t v v ddx >= 0
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 746 freescale semiconductor a.6 reset, oscillator and pll this section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked loop (pll). a.6.1 startup table a-20 summarizes several startup characteristics explained in this section. detailed description of the startup behavior can be found in the clock and reset generator (crg) block description a.6.1.1 por the release level v porr and the assert level v pora are derived from the v dd supply. they are also valid if the device is powered externally. after releasing the por reset the oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is detected, the mcu will start using the internal self clock. the fastest startup time possible is given by n uposc . a.6.1.2 sram data retention provided an appropriate external reset signal is applied to the mcu, preventing the cpu from executing code when v dd35 is out of speci?ation limits, the sram contents integrity is guaranteed if after the reset the porf bit in the crg ?gs register has not been set. a.6.1.3 external reset when external reset is asserted for a time greater than pw rstl the crg module generates an internal reset, and the cpu starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. a.6.1.4 stop recovery out of stop the controller can be woken up by an external interrupt. a clock quality check as after por is performed before releasing the clocks to the system. if the mcu is woken-up by an interrupt and the fast wake-up feature is enabled (fstwkp = 1 and scme = 1), the system will resume operation in self-clock mode after t fws . table a-20. startup characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 d reset input pulse width, minimum input time pw rstl 2t osc 2 d startup from reset n rst 192 196 n osc 3 d wait recovery startup time t wrs 14 t cyc 4 d fast wakeup from stop 1 1 including voltage regulator startup; v dd /v ddf ?ter capacitors 220 nf, v dd35 = 5 v, t= 25 c t fws 50 100 s
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 747 a.6.1.5 pseudo stop and wait recovery the recovery from pseudo stop and wait is essentially the same since the oscillator is not stopped in both modes. the controller can be woken up by internal or external interrupts. after t wrs the cpu starts fetching the interrupt vector.
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 748 freescale semiconductor a.6.2 oscillator a.6.3 phase locked loop a.6.3.1 jitter information with each transition of the clock f cmp , the deviation from the reference clock f ref is measured and input voltage to the vco is adjusted accordingly.the adjustment is done continuously with no abrupt changes in the clock output frequency. noise, voltage, temperature and other factors cause slight variations in the table a-21. oscillator characteristics conditions are shown in table a-4. unless otherwise noted num c rating symbol min typ max unit 1a c crystal oscillator range (loop controlled pierce) f osc 4.0 16 mhz 2 p startup current i osc 100 a 3a c oscillator start-up time (lcp, 4mhz) 1 1 these values apply for carefully designed pcb layouts with capacitors that match the crystal/resonator requirements.. t uposc 2.2 10 ms 3b c oscillator start-up time (lcp, 8mhz) 1 t uposc 1.1 8 ms 3c c oscillator start-up time (lcp, 16mhz) 1 t uposc 0.75 5 ms 5 d clock quality check time-out t cqout 0.45 2.5 s 6 p clock monitor failure assert frequency f cmfa 200 400 800 khz 7 p external square wave input frequency f ext 2.0 50 mhz 8 d external square wave pulse width low t extl 9.5 ns 9 d external square wave pulse width high t exth 9.5 ns 10 d external square wave rise time t extr 1ns 11 d external square wave fall time t extf 1ns 12 d input capacitance (extal, xtal pins) c in ?pf 13 p extal pin input high voltage v ih,extal 0.75*v ddpll v t extal pin input high voltage ,2 2 only applies if extal is externally driven v ih,extal v ddpll + 0.3 v 14 p extal pin input low voltage v il,extal 0.25*v ddpll v t extal pin input low voltage ,2 v il,extal v sspll - 0.3 v 15 c extal pin input hysteresis v hys,extal 180 mv 16 c extal pin oscillation amplitude (loop controlled pierce) v pp,extal 0.9 v
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 749 control loop resulting in a clock jitter. this jitter affects the real minimum and maximum clock periods as illustrated in figure a-4 . figure a-4. jitter de?itions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n). de?ing the jitter as: for n < 1000, the following equation is a good ? for the maximum jitter: figure a-5. maximum bus clock jitter approximation 2 3 n-1 n 1 0 t nom t max1 t min1 t maxn t minn jn () max 1 t max n () nt nom ? ---------------------- - 1 t min n () nt nom ? ---------------------- - , ?? ?? ?? = jn () j 1 n -------- j 2 + = 1 5 10 20 n j(n)
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 750 freescale semiconductor note on timers and serial modules a prescaler will eliminate the effect of the jitter to a large extent. a.7 lcd driver table a-23. <> driver electrical characteristics 1) outputs measured one at a time, low impedance voltage source connected to the vlcd pin. table a-22. ipll characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1p self clock mode frequency 1 1 bus frequency is equivalent to f scm /2 f scm 1 4 mhz 2 t vco locking range f vco 32 120 mhz 3 t reference clock f ref 1 40 mhz 4 d lock detection |? lock | 0 1.5 % 2 2 % deviation from target frequency 5 d un-lock detection |? unl | 0.5 2.5 % 2 7 c time to lock t lock 214 150 + 256/f ref s 8c jitter ? parameter 1 3 3 f osc =4mhz, f bus =40mhz equivalent f pll =80mhz: refdiv=$00, refrq=01, syndiv=$09, vcofrq=01, postdiv=$00 j 1 1.2 % 9c jitter ? parameter 2 3 j 2 0% 10 c bus frequency for fm1=1, fm0=1 (frequency modulation in pllctl register of s12xe_crg) f bus 38 mhz 11 c bus frequency for fm1=1, fm0=0 (frequency modulation in pllctl register of s12xe_crg) f bus 39 mhz 12 c bus frequency for fm1=0, fm0=1 (frequency modulation in pllctl register of s12xe_crg) f bus 39 mhz characteristic symbol min. typ. max. unit lcd output impedance(bp[3:0],fp[39:0]) for outputs to charge to higher voltage level or to gnd 1) z bp/fp - - 5.0 k ? lcd output current (bp[3:0],fp[39:0]) for outputs to discharge to lower voltage level ex- cept gnd 1) i bp/fp 50 - - ua
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 751 the 1/3, 1/2 and 2/3 vlcd voltage levels are buffered internally with an asymmetric output stage, as shown in figure a-6. figure a-6. buffer con?uration (left) and buffer output stage (right) the switching matrix applies a capacitive load (lcd elements) to the buffer output. the charge excites the buffer output voltage v buf from the target output voltage which can be 1/3, 1/2 or 2/3 vlcd. after a positive spike on v buf a frontplane or backplane is discharged by an active load with a constant current. after a negative spike on v buf the output is charged through a transistor which is switched on and which behaves like a resistor. simpli?d output voltage transients are shown in figure a-7. . the shown transients emphasize the spikes and the voltage recovery. they are not to scale. the buffer output characteristic is shown in figure a-8. . the resistive output characteristic is also valid if an output is forced to gnd or vlcd. switch matrix to lcd v buf v buf vlcd vddx output mosfet active load i out
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 752 freescale semiconductor . figure a-7. v buf transients (not to scale) figure a-8. buffer output characteristic v buf t 2/3vlcd 1/2vlcd 1/3vlcd constant current resistive i out v out 1/3, 1/2 or 2/3 vlcd resistive current source region region i bp/fp z bp/fp
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 753 a.8 mscan table a-24. mscan wake-up pulse characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p mscan wakeup dominant pulse ?tered t wup 1.5 s 2 p mscan wakeup dominant pulse pass t wup 5 s
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 754 freescale semiconductor a.9 spi timing this section provides electrical parametrics and ratings for the spi. in table a-25 the measurement conditions are listed. a.9.1 master mode in figure a-9 the timing diagram for master mode with transmission format cpha = 0 is depicted. figure a-9. spi master timing (cpha = 0) table a-25. measurement conditions description value unit drive mode full drive mode load capacitance c load 1 , on all outputs 1 timing speci?d for equal load on all spi output pins. avoid asymmetric load. 50 pf thresholds for delay measurement points (20% / 80%) v ddx v thresholds for delay measurement points on motor pad (20% / 80%) v ddm v sck (output) sck (output) miso (input) mosi (output) ss (output) 1 9 5 6 msb in2 bit msb-1. . . 1 lsb in msb out2 lsb out bit msb-1. . . 1 11 4 4 2 10 (cpol = 0) (cpol = 1) 3 13 13 1. if con?ured as an output. 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, bit 2... msb. 12 12
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 755 in figure a-10 the timing diagram for master mode with transmission format cpha=1 is depicted. figure a-10. spi master timing (cpha = 1) in table a-26 the timing characteristics for master mode are listed. table a-26. spi master mode timing characteristics num c characteristic sym bol min typ max unit 1 d sck frequency f sck f bus /2048 min(16, f bus /2) 1 1 spi on non-motor pad ports (port s or por t h) mhz min(10,f bus /2) 2 2 spi on port v with slew rate control disable. all the spi pins slew rate control should be disabled. min(0.8,f bus /2) 3 3 spi on port v with slew rate control enabled. all the spi pins slew rate control should be enabled. 4. min(16, f bus /2) means select minimum frequency value from 16mhz and f bus /2mhz. same for the other min(x,y) 5. max(62.5, 2*t bus ) means select the maximum period value from 62.5ns and 2*t bus ns. same for the other max(x,y) 1 d sck period t sck max(62.5, 2*t bus ) 1 2048 ? t bus ns max(100, 2*t bus ) 2 max(1250, 2*t bus ) 3 2 d enable lead time t lead 1/2 t sck 3 d enable lag time t lag 1/2 t sck 4 d clock (sck) high or low time t wsck 1/2 t sck 5 d data setup time (inputs) t su 8ns 6 d data hold time (inputs) t hi 8ns 9 d data valid after sck edge t vsck 29 ns 10 d data valid after ss fall (cpha = 0) t vss 15 ns 11 d data hold time (outputs) t ho 20 ns 12 d rise and fall time inputs t r 8ns 13 d rise and fall time outputs t rfo 8ns sck (output) sck (output) miso (input) mosi (output) 1 5 6 msb in2 bit msb-1. . . 1 lsb in master msb out2 master lsb out bit msb-1. . . 1 4 4 9 12 13 11 port data (cpol = 0) (cpol = 1) port data ss (output) 2 12 13 3 1.if con?ured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1,bit 2... msb.
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 756 freescale semiconductor a.9.2 slave mode in figure a-11 the timing diagram for slave mode with transmission format cpha = 0 is depicted. figure a-11. spi slave timing (cpha = 0) in figure a-12 the timing diagram for slave mode with transmission format cpha = 1 is depicted. figure a-12. spi slave timing (cpha = 1) sck (input) sck (input) mosi (input) miso (output) ss (input) 1 9 5 6 msb in bit msb-1 . . . 1 lsb in slave msb slave lsb out bit msb-1. . . 1 11 4 4 2 7 (cpol = 0) (cpol = 1) 3 13 note: not de?ed 12 12 11 see 13 note 8 10 see note sck (input) sck (input) mosi (input) miso (output) 1 5 6 msb in bit msb-1 . . . 1 lsb in msb out slave lsb out bit msb-1 . . . 1 4 4 9 12 13 11 (cpol = 0) (cpol = 1) ss (input) 2 12 13 3 note: not de?ed slave 7 8 see note
electrical characteristics mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 757 in table a-27 the timing characteristics for slave mode are listed. table a-27. spi slave mode timing characteristics num c characteristic sy mb ol min typ max unit 1 d sck frequency f sck dc min(8,f bus /4) 1 1 spi on non-motor pad ports (port s or por t h), or spi on motor pad ports with all slew rate control disable mhz min(0.8,f bus /4) 2 2 spi on port v with slew rate control enabled. all the spi pins slew rate control should be enabled 1 d sck period t sck 4*t bus 1 ns max(1250, 4*t bus ) 2 2 d enable lead time t lead 4 t bus 3 d enable lag time t lag 4 t bus 4 d clock (sck) high or low time t wsc k 4 t bus 5 d data setup time (inputs) t su 8 ns 6 d data hold time (inputs) t hi 8 ns 7 d slave access time (time to data active) t a 20 ns 8 d slave miso disable time t dis 22 ns 9 d data valid after sck edge t vsc k 29 + 0.5 ? t bus 3 3 0.5 t bus added due to internal synchronization delay ns 10 d data valid after ss fall t vss 29 + 0.5 ? t bus 1 ns 11 d data hold time (outputs) t ho 20 ns 12 d rise and fall time inputs t r 8 ns 13 d rise and fall time outputs t rfo 8 ns
package and die information mc9s12xhy-family reference manual, rev. 1.01 758 freescale semiconductor appendix b package and die information this section provides the physical dimensions of the 9s12xhy family packages information.
package and die information mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 759 b.1 112-pin lqfp mechanical dimensions figure b-1. 112-pin lqfp (case no. 987) - page 1
package and die information mc9s12xhy-family reference manual, rev. 1.01 760 freescale semiconductor figure b-2. 112-pin lqfp (case no. 987) - page 2
package and die information mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 761 figure b-3. 112-pin lqfp (case no. 987) - page 3
package and die information mc9s12xhy-family reference manual, rev. 1.01 762 freescale semiconductor b.2 100-pin lqfp mechanical dimensions figure b-4. 100-pin lqfp(case no.983) -page 1
package and die information mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 763 figure b-5. 100-pin lqfp(case no.983) - page 2
package and die information mc9s12xhy-family reference manual, rev. 1.01 764 freescale semiconductor figure b-6. 100-pin lqfp(case no.983) - page 3
pcb layout guidelines mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 765 appendix c pcb layout guidelines c.1 general the pcb must be carefully laid out to ensure proper operation of the voltage regulator as well as of the mcu itself. the following rules must be observed: every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins . central point of the ground star should be the vss3 pin. use low ohmic low inductance connections between vss1, vss2 and vss3. vsspll must be directly connected to vss3. keep traces of vsspll, extal, and xtal as short as possible and occupied board area for c12,c11, and q1 as small as possible. do not place other signals or supplies underneath area occupied by c12,c11, and q1 and the connection area to the mcu. central power input should be fed in at the vdda/vssa pins. example layouts are illustrated on the following pages. table c-1. recommended decoupling capacitor choice component purpose type value c1 v ddx1 ?ter capacitor x7r/tantalum >=100 nf c2 v ddm1 ?ter capacitor x7r/tantalum >=47 uf c3 v ddm2 ?ter capacitor x7r/tantalum >=47 uf c4 v ddpll ?ter capacitor ceramic x7r 220 nf c5 v lcd ?ter capacitor ceramic x7r >=100 nf c6 v ddx2 ?ter capacitor x7r/tantalum >=100 nf c7 v dda ?ter capacitor ceramic x7r >=100 nf c8 v ddr ?ter capacitor x7r/tantalum >=100 nf c9 v dd ?ter capacitor ceramic x7r 220 nf c10 v ddf ?ter capacitor ceramic x7r 220 nf c11 osc load capacitor from crystal manufacturer c12 osc load capacitor q1 quartz
pcb layout guidelines mc9s12xhy-family reference manual, rev. 1.01 766 freescale semiconductor c.1.1 112-pin lqfp recommended pcb layout figure c-1. 112-pin lqfp recommended pcb layout (loop controlled pierce oscillator)
pcb layout guidelines mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 767 c.1.2 100-pin qfp recommended pcb layout figure c-2. 100-pin qfp recommended pcb layout (loop controlled pierce oscillator)
derivative differences mc9s12xhy-family reference manual, rev. 1.01 768 freescale semiconductor appendix d derivative differences d.1 memory sizes and package options 9s12xhy family note for the112lqfp and 100lqfp package options, several peripheral functions can be routed under software control to different pins. not all functions are available simultaneously. for details see table 1-6. appendix e detailed register address map e.1 detailed register map the following tables show the detailed register map of the 9s12xhy family table d-1. package and memory options of 9s12xhy family device package flash ram data flash 9s12xhy256 112 lqfp 256k 12k 8k 100 qfp 9s12xhy128 112 lqfp 128k 8k 8k 100 qfp table d-2. peripheral options of 9s12xhy family members device package can sci spi tim iic lcd mc a/d pwm 9s12xhy256 112 lqfp 2 2 1 2x8ch 1 40x4 4 12ch 8ch 100 qfp 2 2 1 2x8ch 1 38x4 4 8ch 8ch 9s12xhy128 112 lqfp 2 2 1 2x8ch 1 40x4 4 12ch 8ch 100 qfp 2 2 1 2x8ch 1 38x4 4 8ch 8ch 0x0000?x0009 port integration module (pim) map 1 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0000 porta r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa 0 w 0x0001 portb r pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 w 0x0002 ddra r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w 0x0003 ddrb r ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 w 0x0004 reserved r00000000 w
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 769 0x0005 reserved r00000000 w 0x0006 reserved r00000000 w 0x0007 reserved r00000000 w 0x0008 reserved r00000000 w 0x0009 reserved r00000000 w 0x000a?x000b module mapping control (s12xmmc) map 1 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000a reserved r00000000 w 0x000b mode r modc 0000000 w 0x000c?x000d port integration module (pim) map 2 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000c pucr r0 bkpur 0000 pupbe pupae w 0x000d reserved r00000000 w 0x000e?x000f reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000e reserved r00000000 w 0x000f reserved r00000000 w 0x0010?x0017 module mapping control (s12xmmc) map 2 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0010 gpage r0 gp6 gp5 gp4 gp3 gp2 gp1 gp0 w 0x0011 direct r dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 w 0x0000?x0009 port integration module (pim) map 1 of 4
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 770 freescale semiconductor 0x0012 reserved r00000000 w 0x0013 mmcctl1 r mgramo n 0 dfifron pgmifro n 0000 w 0x0014 reserved r00000000 w 0x0015 ppage r pix7 pix6 pix5 pix4 pix3 pix2 pix1 pix0 w 0x0016 rpage r rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 w 0x0017 epage r ep7 ep6 ep5 ep4 ep3 ep2 ep1 ep0 w 0x0018?x0019 reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0018 reserved r00000000 w 0x0019 reserved r00000000 w 0x001a?x001b device id register address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x001a partidh r partidh w 0x001b partidl r partidl w 0x001c?x001f port integration module (pim) map 3 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x001c eclkctl r neclk 0 div16 ediv4 ediv3 ediv2 ediv1 ediv0 w 0x001d reserved r00000000 w 0x001e irqcr r irqe irqen xirqen 00000 w 0x001f reserved r00000000 w 0x0010?x0017 module mapping control (s12xmmc) map 2 of 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 771 0x0020?x002f debug module (s12xdbg) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0020 dbgc1 r arm 0 reserved bdm dbgbrk reserved comrv w trig 0x0021 dbgsr r tbf 0 0 0 0 ssf2 ssf1 ssf0 w 0x0022 dbgtcr r reserved tsource trange trcmod talign w 0x0023 dbgc2 r0 0 0 0 cdcm abcm w 0x0024 dbgtbh r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0025 dbgtbl r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0026 dbgcnt r 0 cnt w 0x0027 dbgscrx r0 0 0 0 sc3 sc2 sc1 sc0 w 0x0027 dbgmfr r 0 0 0 0 mc3 mc2 mc1 mc0 w 0x0028 1 1 this represents the contents if the comparator a or c control register is blended into this address dbgxctl (compa/c) r0 ndb tag brk rw rwe reserved compe w 0x0028 2 2 this represents the contents if the comparator b or d control register is blended into this address dbgxctl (compb/d) r sze sz tag brk rw rwe reserved compe w 0x0029 dbgxah r0 bit 22 21 20 19 18 17 bit 16 w 0x002a dbgxam r bit 15 14 13 12 11 10 9 bit 8 w 0x002b dbgxal r bit 7 6 54321 bit 0 w 0x002c dbgxdh r bit 15 14 13 12 11 10 9 bit 8 w 0x002d dbgxdl r bit 7 6 54321 bit 0 w 0x002e dbgxdhm r bit 15 14 13 12 11 10 9 bit 8 w 0x002f dbgxdlm r bit 7 6 54321 bit 0 w
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 772 freescale semiconductor 0x0030?x0031 reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0030 reserved r00000000 w 0x0031 reserved r00000000 w 0x0032?x0033 reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0032 reserved r00000000 w 0x0033 reserved r00000000 w 0x0034?x003f clock and reset generator (crg) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0034 synr r vcofrq[1:0] syndiv[5:0] w 0x0035 refdv r reffrq[1:0] refdiv[5:0] w 0x0036 postdiv r0 0 0 postdiv[4:0] w 0x0037 crgflg r rtif porf lvrf lockif lock ilaf scmif scm w 0x0038 crgint r rtie 00 lockie 00 scmie 0 w 0x0039 clksel r pllsel pstp xclks 0 pllwai 0 rtiwai copwai w 0x003a pllctl r cme pllon fm1 fm0 fstwkp pre pce scme w 0x003b rtictl r rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 w 0x003c copctl r wcop rsbck 000 cr2 cr1 cr0 w wrtmas k 0x003d forbyp r00000000 w reserved for factory test 0x003e ctctl r0000 000 w reserved for factory test 0x003f armcop r00000000 w bit 7 6 54321 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 773 0x0040?x006f timer module (tim0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0040 tios r ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 w 0x0041 cforc r00000000 w foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 0x0042 oc7m r oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 w 0x0043 oc7d r oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 w 0x0044 tcnth r bit 15 14 13 12 11 10 9 bit 8 w 0x0045 tcntl r bit 7 6 5 4 3 2 1 bit 0 w 0x0046 tscr1 r ten tswai tsfrz tffca prnt 000 w 0x0047 ttov r tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 w 0x0048 tctl1 r om7 ol7 om6 ol6 om5 ol5 om4 ol4 w 0x0049 tctl2 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 w 0x004a tctl3 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w 0x004b tctl4 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a w 0x004c tie r c7i c6i c5i c4i c3i c2i c1i c0i w 0x004d tscr2 r toi 000 tcre pr2 pr1 pr0 w 0x004e tflg1 r c7f c6f c5f c4f c3f c2f c1f c0f w 0x004f tflg2 r tof 0000000 w 0x0050 tc0h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0051 tc0l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0052 tc1h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0053 tc1l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0054 tc2h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0055 tc2l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 774 freescale semiconductor 0x0056 tc3h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0057 tc3l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0058 tc4h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x0059 tc4l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x005a tc5h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x005b tc5l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x005c tc6h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x005d tc6l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x005e tc7h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x005f tc7l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x0060 pactl r0 paen pamod pedge clk1 clk0 paovi pai w 0x0061 paflg r000000 paovf paif w 0x0062 pacnth r pacnt15 pacnt14 pacnt13 pacnt12 pacnt11 pacnt10 pacnt9 pacnt8 w 0x0063 pacntl r pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 w 0x0064 0x006b reserved r00000000 w 0x006c ocpd r ocpd7 ocpd6 ocpd5 ocpd4 ocpd3 ocpd2 ocpd1 ocpd0 w 0x006d reserved r w 0x006e ptpsr r ptps7 ptps6 ptps5 ptps4 ptps3 ptps2 ptps1 ptps0 w 0x006f reserved r00000000 w 0x0040?x006f timer module (tim0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 775 0x0070?x09f analog to digital converter (atd) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0070 atdctl0 r reserved 000 wrap3 wrap2 wrap1 wrap0 w 0x0071 atdctl1 r etrigsel sres1 sres0 smp_dis etrigch 3 etrigch 2 etrigch 1 etrigch 0 w 0x0072 atdctl2 r0 affc iclkstp etrigle etrigp etrige ascie acmpie w 0x0073 atdctl3 r djm s8c s4c s2c s1c fifo frz1 frz0 w 0x0074 atdctl4 r smp2 smp1 smp0 prs[4:0] w 0x0075 atdctl5 r0 sc scan mult cd cc cb ca w 0x0076 atdstat0 r scf 0 etorf fifor cc3 cc2 cc1 cc0 w 0x0077 unimple- mented r00000000 w 0x0078 atdcmpeh r0 0 0 0 cmpe[11:8] w 0x0079 atdcmpel r cmpe[7:0] w 0x007a atdstat2h r 0 0 0 0 ccf[11:8] w 0x007b atdstat2l r ccf[7:0] w 0x007c atddienh r0 0 0 0 ien[11:8] w 0x007d atddienl r ien[7:0] w 0x007e atdcmphth r0 0 0 0 cmpht[11:8] w 0x007f atdcmphtl r cmpht[7:0] w 0x0080 atddr0 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0082 atddr1 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x084 atddr2 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0086 atddr3 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0088 atddr4 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x008a atddr5 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 776 freescale semiconductor 0x00a0?x00c7 pulse-width modulator 8 channels(pwm) map 0x008c atddr6 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x008e atddr7 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0090 atddr8 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0092 atddr9 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0094 atddr10 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0096 atddr11 r see section 10.3.2.12.1, ?eft justi?d result data (djm=0) and section 10.3.2.12.2, ?ight justi?d result data (djm=1) w 0x0098 - 0x009f unimple- mented r 00000000 w address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00a0 pwme r pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 w 0x00a1 pwmpol r ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 w 0x00a2 pwmclk r pclk7 pclk6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 w 0x00a3 pwmprclk r0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 w 0x00a4 pwmcae r cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 w 0x00a5 pwmctl r con67 con45 con23 con01 pswai pfrz 00 w 0x00a6 pwmtst test only r00000000 w 0x00a7 pwmprsc r00000000 w 0x00a8 pwmscla r bit 7 6 5 4 3 2 1 bit 0 w 0x00a9 pwmsclb r bit 7 6 5 4 3 2 1 bit 0 w 0x0070?x09f analog to digital converter (atd) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 777 0x00aa pwmscnta r00000000 w 0x00ab pwmscntb r00000000 w 0x00ac pwmcnt0 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x00ad pwmcnt1 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x00ae pwmcnt2 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x00af pwmcnt3 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x00b0 pwmcnt4 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x00b1 pwmcnt5 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x00b2 pwmcnt6 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x00b3 pwmcnt7 r bit 7 6 5 4 3 2 1 bit 0 w00000000 0x00b4 pwmper0 r bit 7 6 5 4 3 2 1 bit 0 w 0x00b5 pwmper1 r bit 7 6 5 4 3 2 1 bit 0 w 0x00b6 pwmper2 r bit 7 6 5 4 3 2 1 bit 0 w 0x00b7 pwmper3 r bit 7 6 5 4 3 2 1 bit 0 w 0x00b8 pwmper4 r bit 7 6 5 4 3 2 1 bit 0 w 0x00b9 pwmper5 r bit 7 6 5 4 3 2 1 bit 0 w 0x00ba pwmper6 r bit 7 6 5 4 3 2 1 bit 0 w 0x00bb pwmper7 r bit 7 6 5 4 3 2 1 bit 0 w 0x00bc pwmdty0 r bit 7 6 5 4 3 2 1 bit 0 w 0x00bd pwmdty1 r bit 7 6 5 4 3 2 1 bit 0 w address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 778 freescale semiconductor 0x00be pwmdty2 r bit 7 6 5 4 3 2 1 bit 0 w 0x00bf pwmdty3 r bit 7 6 5 4 3 2 1 bit 0 w 0x00c0 pwmdty4 r bit 7 6 5 4 3 2 1 bit 0 w 0x00c1 pwmdty5 r bit 7 6 5 4 3 2 1 bit 0 w 0x00c2 pwmdty6 r bit 7 6 5 4 3 2 1 bit 0 w 0x00c3 pwmdty7 r bit 7 6 5 4 3 2 1 bit 0 w 0x00c4 pwmsdn r pwmif pwmie 0 pwmlvl 0 pwm7in pwm7inl pwm7 ena w pwm rstrt 0x00c5 reserved r00000000 w 0x00c6 reserved r00000000 w 0x00c7 reserved r00000000 w 0x00c8?x00cf asynchronous serial interface (sci0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00c8 sci0bdh 1 r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w 0x00c9 sci0bdl 1 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w 0x00ca sci0cr1 1 r loops sciswai rsrc m wake ilt pe pt w 0x00c8 sci0asr1 2 r rxedgif 0000 berrv berrif bkdif w 0x00c9 sci0acr1 2 r rxedgie 00000 berrie bkdie w 0x00ca sci0acr2 2 r00000 berrm1 berrm0 bkdfe w 0x00cb sci0cr2 r tie tcie rie ilie te re rwu sbk w 0x00cc sci0sr1 r tdre tc rdrf idle or nf fe pf w address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 779 0x00cd sci0sr2 r amap 00 txpol rxpol brk13 txdir raf w 0x00ce sci0drh rr8 t8 000000 w 0x00cf sci0drl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 1 those registers are accessible if the amap bit in the sci0sr2 register is set to zero 2 those registers are accessible if the amap bit in the sci0sr2 register is set to one 0x00d0?x00d7 asynchronous serial interface (sci1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00d0 sci1bdh 1 1 those registers are accessible if the amap bit in the sci1sr2 register is set to zero r iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 w 0x00d1 sci1bdl 1 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w 0x00d2 sci1cr1 1 r loops sciswai rsrc m wake ilt pe pt w 0x00d0 sci1asr1 2 2 those registers are accessible if the amap bit in the sci1sr2 register is set to one r rxedgif 0000 berrv berrif bkdif w 0x00d1 sci1acr1 2 r rxedgie 00000 berrie bkdie w 0x00d2 sci1acr2 2 r00000 berrm1 berrm0 bkdfe w 0x00d3 sci1cr2 r tie tcie rie ilie te re rwu sbk w 0x00d4 sci1sr1 r tdre tc rdrf idle or nf fe pf w 0x00d5 sci1sr2 r amap 00 txpol rxpol brk13 txdir raf w 0x00d6 sci1drh rr8 t8 000000 w 0x00d7 sci1drl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 0x00d8?x00df serial peripheral interface (spi) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00d8 spicr1 r spie spe sptie mstr cpol cpha ssoe lsbfe w 0x00d9 spicr2 r0 xfrw 0 modfen bidiroe 0 spiswai spc0 w (continued)0x00c8?x00cf asynchronous serial interface (sci0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 780 freescale semiconductor 0x00e0?x00e7 inter ic bus (iic) map 0x00da spibr r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w 0x00db spisr r spif 0 sptef modf 0 0 0 0 w 0x00dc spidrh r r15 r14 r13 r12 r11 r10 r9 r8 w t15 t14 t13 t12 t11 t10 t9 t8 0x00dd spidrl rr7r6r5r4r3r2r1r0 wt7t6t5t4t3t2t1t0 0x00de reserved r00000000 w 0x00df reserved r00000000 w address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00e0 ibad r adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 w 0x00e1 ibfd r ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 w 0x00e2 ibcr r iben ibie ms/ sl tx/ rx txak 00 ibswai w rsta 0x00e3 ibsr r tcf iaas ibb ibal 0srw ibif rxak w 0x00e4 ibdr r d7 d6 d5 d4 d3 d2 d1 d 0 w 0x00e5 ibcr2 r gcen adtype 000 adr10 adr9 adr8 w 0x00e6 reserved r00000000 w 0x00e7 reserved r00000000 w 0x00e8?x00ff reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00e8- 0x00ff reserved r00000000 w 0x00d8?x00df serial peripheral interface (spi) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 781 0x0100?x0113 nvm control register (ftmr) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0100 fclkdiv r fdivld fdiv6 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 w 0x0101 fsec r keyen1 keyen0 rnv5 rnv4 rnv3 rnv2 sec1 sec0 w 0x0102 fccobix r0 0 0 0 0 ccobix2 ccobix1 ccobix0 w 0x0103 feccrix r0 0 0 0 0 eccrix2 eccrix1 eccrix0 w 0x0104 fcnfg r ccie 00 ignsf 00 fdfd fsfd w 0x0105 fercnfg r0 0 0 0 0 0 dfdie sfdie w 0x0106 fstat r ccif 0 accerr fpviol mgbusy rsvd mgstat1 mgstat0 w 0x0107 ferstat r0 0 0 0 0 0 dfdif sfdif w 0x0108 fprot r fpopen rnv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 w 0x0109 dfprot r dpopen 00 dps4 dps3 dps2 dps1 dps0 w 0x010a fccobhi r ccob15 ccob14 ccob13 ccob12 ccob11 ccob10 ccob9 ccob8 w 0x010b fccoblo r ccob7 ccob6 ccob5 ccob4 ccob3 ccob2 ccob1 ccob0 w 0x010c reserved r00000000 w 0x010d reserved r00000000 w 0x010e feccrhi r eccr15 eccr14 eccr13 eccr12 eccr11 eccr10 eccr9 eccr8 w 0x010f feccrlo r eccr7 eccr6 eccr5 eccr4 eccr3 eccr2 eccr1 eccr0 w 0x0110 fopt r nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 w 0x0111 reserved r00000000 w 0x0112 reserved r00000000 w 0x0113 reserved r00000000 w
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 782 freescale semiconductor 0x0114?x011f reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0114- 0x011f reserved r00000000 w 0x0120?x012f interrupt module (s12xint) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0120 reserved r00000000 w 0x0121 ivbr r ivb_addr[7:0] w 0x0122 reserved r00000000 w 0x0123 reserved r00000000 w 0x0124 reserved r00000000 w 0x0125 reserved r00000000 w 0x0126 int_xgprio r00000 xilvl[2:0] w 0x0127 int_cfaddr r int_cfaddr[7:4] 0000 w 0x0128 int_cfdata0 r rqst 0000 priolvl[2:0] w 0x0129 int_cfdata1 r rqst 0000 priolvl[2:0] w 0x012a int_cfdata2 r rqst 0000 priolvl[2:0] w 0x012b int_cfdata3 r rqst 0000 priolvl[2:0] w 0x012c int_cfdata4 r rqst 0000 priolvl[2:0] w 0x012d int_cfdata5 r rqst 0000 priolvl[2:0] w 0x012e int_cfdata6 r rqst 0000 priolvl[2:0] w 0x012f int_cfdata7 r rqst 0000 priolvl[2:0] w
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 783 0x00130?x013f reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0130- 0x013f reserved r00000000 w 0x0140?x017f mscan (can0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0140 can0ctl0 r rxfrm rxact cswai synch time wupe slprq initrq w 0x0141 can0ctl1 r cane clksrc loopb listen borm wupm slpak initak w 0x0142 can0btr0 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 w 0x0143 can0btr1 r samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 w 0x0144 can0rflg r wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf w 0x0145 can0rier r wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie w 0x0146 can0tflg r00000 txe2 txe1 txe0 w 0x0147 can0tier r00000 txeie2 txeie1 txeie0 w 0x0148 can0tarq r00000 abtrq2 abtrq1 abtrq0 w 0x0149 can0taak r 0 0 0 0 0 abtak2 abtak1 abtak0 w 0x014a can0tbsel r00000 tx2 tx1 tx0 w 0x014b can0idac r0 0 idam1 idam0 0 idhit2 idhit1 idhit0 w 0x014c reserved r00000000 w 0x014d can0misc r0000000 bohold w 0x014e can0rxerr r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 w 0x014f can0txerr r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 w 0x0150- 0x0153 can0idar0- can0idar3 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x0154- 0x0157 can0idmr0- can0idmr3 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0158- 0x015b can0idar4- can0idar7 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 784 freescale semiconductor 0x015c- 0x015f can0idmr4- can0idmr7 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0160- 0x016f can0rxfg r foreground receive buffer (see detailed mscan foreground receive and transmit buffer layout ) w 0x0170- 0x017f can0txfg r foreground transmit buffer (see detailed mscan foreground receive and transmit buffer layout ) w detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0xxxx0 extended id r id28 id27 id26 id25 id24 id23 id22 id21 standard id r id10 id9 id8 id7 id6 id5 id4 id3 canxridr0 w 0xxxx1 extended id r id20 id19 id18 srr=1 ide=1 id17 id16 id15 standard id r id2 id1 id0 rtr ide=0 canxridr1 w 0xxxx2 extended id r id14 id13 id12 id11 id10 id9 id8 id7 standard id r canxridr2 w 0xxxx3 extended id r id6 id5 id4 id3 id2 id1 id0 rtr standard id r canxridr3 w 0xxxx4- 0xxxxb canxrdsr0- canxrdsr7 r db7 db6 db5 db4 db3 db2 db1 db0 w 0xxxxc canrxdlr r dlc3 dlc2 dlc1 dlc0 w 0xxxxd reserved r w 0xxxxe canxrtsrh r tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 w 0xxxxf canxrtsrl r tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 w 0xxx10 extended id r id28 id27 id26 id25 id24 id23 id22 id21 canxtidr0 w standard id r id10 id9 id8 id7 id6 id5 id4 id3 w 0xxx0x xx10 extended id r id20 id19 id18 srr=1 ide=1 id17 id16 id15 canxtidr1 w standard id r id2 id1 id0 rtr ide=0 w 0xxx12 extended id r id14 id13 id12 id11 id10 id9 id8 id7 canxtidr2 w standard id r w 0x0140?x017f mscan (can0) map (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 785 0xxx13 extended id r id6 id5 id4 id3 id2 id1 id0 rtr canxtidr3 w standard id r w 0xxx14- 0xxx1b canxtdsr0 canxtdsr7 r db7 db6 db5 db4 db3 db2 db1 db0 w 0xxx1c canxtdlr r dlc3 dlc2 dlc1 dlc0 w 0xxx1d canxttbpr r prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 w 0xxx1e canxttsrh r tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 w 0xxx1f canxttsrl r tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 w 0x0180?x01bf mscan (can1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0180 can1ctl0 r rxfrm rxact cswai synch time wupe slprq initrq w 0x0181 can1ctl1 r cane clksrc loopb listen borm wupm slpak initak w 0x0182 can1btr0 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 w 0x0183 can1btr1 r samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 w 0x0184 can1rflg r wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf w 0x0185 can1rier r wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie w 0x0186 can1tflg r00000 txe2 txe1 txe0 w 0x0187 can1tier r00000 txeie2 txeie1 txeie0 w 0x0188 can1tarq r00000 abtrq2 abtrq1 abtrq0 w 0x0189 can1taak r 0 0 0 0 0 abtak2 abtak1 abtak0 w 0x018a can1tbsel r00000 tx2 tx1 tx0 w 0x018b can1idac r0 0 idam1 idam0 0 idhit2 idhit1 idhit0 w 0x018c reserved r00000000 w detailed mscan foreground receive and transmit buffer layout (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 786 freescale semiconductor 0x01c0-0x01ff motor controller 10-bit 8-channels(mc) map 0x018d can1misc r0000000 bohold w 0x018e can1rxerr r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 w 0x018f can1txerr r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 w 0x0190- 0x0193 can1idar0- can1idar3 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x0194- 0x0197 can1idmr0- can1idmr3 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x0198- 0x019b can1idar4- can1idar7 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w 0x019c- 0x019f can1idmr4- can1idmr7 r am7 am6 am5 am4 am3 am2 am1 am0 w 0x01a0- 0x01af can1rxfg r foreground receive buffer (see detailed mscan foreground receive and transmit buffer layout ) w 0x01b0- 0x01bf can1txfg r foreground transmit buffer (see detailed mscan foreground receive and transmit buffer layout ) w address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x01c0 mcctl0 r0 mcpre1 mcpre0 mcswai fast dith 0 mctoif w 0x01c1 mcctl1 r recirc 000000 mctoie w 0x01c2 mcper (hi) r00000 p10 p9 p8 w 0x01c3 mcper (lo) r p7 p6 p5 p4 p3 p2 p1 p0 w 0x01c4 0x01cf reserved r00000000 w 0x01d0 mccc0 r mcom1 mcom0 mcam1 mcam0 00 cd1 cd0 w 0x01d1 mccc1 r mcom1 mcom0 mcam1 mcam0 00 cd1 cd0 w 0x01d2 mccc2 r mcom1 mcom0 mcam1 mcam0 00 cd1 cd0 w 0x01d3 mccc3 r mcom1 mcom0 mcam1 mcam0 00 cd1 cd0 w 0x01d4 mccc4 r mcom1 mcom0 mcam1 mcam0 00 cd1 cd0 w 0x0180?x01bf mscan (can1) map (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 787 0x01d5 mccc5 r mcom1 mcom0 mcam1 mcam0 00 cd1 cd0 w 0x01d6 mccc6 r mcom1 mcom0 mcam1 mcam0 00 cd1 cd0 w 0x01d7 mccc7 r mcom1 mcom0 mcam1 mcam0 00 cd1 cd0 w 0x01d8 0x01df reserved r00000000 w 0x01e0 mcdc0 (hi) r s ssss d10 d9 d8 w 0x01e1 mcdc0 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01e2 mcdc1 (hi) r s ssss d10 d9 d8 w 0x01e3 mcdc1 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01e4 mcdc2 (hi) r s ssss d10 d9 d8 w 0x01e5 mcdc2 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01e6 mcdc3 (hi) r s ssss d10 d9 d8 w 0x01e7 mcdc3 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01e8 mcdc4 (hi) r s ssss d10 d9 d8 w 0x01e9 mcdc4 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01ea mcdc5 (hi) r s ssss d10 d9 d8 w 0x01eb mcdc5 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01ec mcdc6 (hi) r s ssss d10 d9 d8 w 0x01ed mcdc6 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w 0x01ee mcdc7 (hi) r s ssss d10 d9 d8 w 0x01ef mcdc7 (lo) r d7 d6 d5 d4 d3 d2 d1 d0 w address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 788 freescale semiconductor 0x0200-0x021f liquid crystal display 40x4(lcd) map 0x01f0 0x01ff reserved r00000000 w address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0200 lcdcr0 r lcden 0 lclk2 lclk1 lclk0 bias duty1 duty0 w 0x0201 lcdcr1 r000000 lcdswai lcdrpst p w 0x0202 fpenr0 r fp7en fp6en fp5en fp4en fp3en fp2en fp1en fp0en w 0x0203 fpenr1 r fp15en fp14en fp13en fp12en fp11en fp10en fp9en fp8en w 0x0204 fpenr2 r fp23en fp22en fp21en fp20en fp19en fp18en fp17en fp16en w 0x0205 fpenr3 r fp31en fp30en fp29en fp28en fp27en fp26en fp25en fp24en w 0x0206 fpenr4 r fp39en fp38en fp37en fp36en fp35en fp34en fp33en fp32en w 0x0207 reserved r00000000 w 0x0208 lcdram0 r fp1bp3 fp1bp2 fp1bp1 fp1bp0 fp0bp3 fp0bp2 fp0bp1 fp0bp0 w 0x0209 lcdram1 r fp3bp3 fp3bp2 fp3bp1 fp3bp0 fp2bp3 fp2bp2 fp2bp1 fp2bp0 w 0x020a lcdram2 r fp5bp3 fp5bp2 fp5bp1 fp5bp0 fp4bp3 fp4bp2 fp4bp1 fp4bp0 w 0x020b lcdram3 r fp7bp3 fp7bp2 fp7bp1 fp7bp0 fp6bp3 fp6bp2 fp6bp1 fp6bp0 w 0x020c lcdram4 r fp9bp3 fp9bp2 fp9bp1 fp9bp0 fp8bp3 fp8bp2 fp8bp1 fp8bp0 w 0x020d lcdram5 r fp11bp3 fp11bp2 fp11bp1 fp11bp0 fp10bp3 fp10bp2 fp10bp1 fp10bp0 w 0x020e lcdram6 r fp13bp3 fp13bp2 fp13bp1 fp13bp0 fp12bp3 fp12bp2 fp12bp1 fp12bp0 w 0x020f lcdram7 r fp15bp3 fp15bp2 fp15bp1 fp15bp0 fp14bp3 fp14bp2 fp14bp1 fp14bp0 w 0x0210 lcdram8 r fp17bp3 fp17bp2 fp17bp1 fp17bp0 fp16bp3 fp16bp2 fp16bp1 fp16bp0 w address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 789 0x0211 lcdram9 r fp19bp3 fp19bp2 fp19bp1 fp19bp0 fp18bp3 fp18bp2 fp18bp1 fp18bp0 w 0x0212 lcdram10 r fp21bp3 fp21bp2 fp21bp1 fp21bp0 fp20bp3 fp20bp2 fp20bp1 fp20bp0 w 0x0213 lcdram11 r fp23bp3 fp23bp2 fp23bp1 fp23bp0 fp22bp3 fp22bp2 fp22bp1 fp22bp0 w 0x0214 lcdram12 r fp25bp3 fp25bp2 fp25bp1 fp25bp0 fp24bp3 fp24bp2 fp24bp1 fp24bp0 w 0x0215 lcdram13 r fp27bp3 fp27bp2 fp27bp1 fp27bp0 fp26bp3 fp26bp2 fp26bp1 fp26bp0 w 0x0216 lcdram14 r fp29bp3 fp29bp2 fp29bp1 fp29bp0 fp28bp3 fp28bp2 fp28bp1 fp28bp0 w 0x0217 lcdram15 r fp31bp3 fp31bp2 fp31bp1 fp31bp0 fp30bp3 fp30bp2 fp30bp1 fp30bp0 w 0x0218 lcdram16 r fp33bp3 fp33bp2 fp33bp1 fp33bp0 fp32bp3 fp32bp2 fp32bp1 fp32bp0 w 0x0219 lcdram17 r fp35bp3 fp35bp2 fp35bp1 fp35bp0 fp34bp3 fp34bp2 fp34bp1 fp34bp0 w 0x021a lcdram18 r fp37bp3 fp37bp2 fp37bp1 fp37bp0 fp36bp3 fp36bp2 fp36bp1 fp36bp0 w 0x021b lcdram19 r fp39bp3 fp39bp2 fp39bp1 fp39bp0 fp38bp3 fp38bp2 fp38bp1 fp38bp0 w 0x021c- 0x021f reserved r00000000 w 0x0220?x0227 stepper stall detector 0 (ssd0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0220 rtz0ctl r itg dcoil rcir pol 0 sms step w 0x0221 mdc0ctl r mczie modmc rdmcl pre 0 mcen 0 aovie w flmc 0x0222 ssd0ctl r rtze sdcpu ssdwai ftst 00 aclks w 0x0223 ssd0flg r mczif 000000 aovif w 0x0224 mdc0cnth r mdccnt[15:8] w address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 790 freescale semiconductor 0x0225 mdc0cntl r mdccnt[7:0] w 0x0226 itg0acch r itgacc[15:8] w 0x0227 itg0accl r itgacc[7:0] w 0x0228?x022f stepper stall detector 1 (ssd1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0228 rtz1ctl r itg dcoil rcir pol 0 sms step w 0x0229 mdc1ctl r mczie modmc rdmcl pre 0 mcen 0 aovie w flmc 0x022a ssd1ctl r rtze sdcpu ssdwai ftst 00 aclks w 0x022b ssd1flg r mczif 000000 aovif w 0x022c mdc1cnth r mdccnt[15:8] w 0x022d mdc1cntl r mdccnt[7:0] w 0x022e itg1acch r itgacc[15:8] w 0x022f itg1accl r itgacc[7:0] w 0x0230?x0237 stepper stall detector 2 (ssd2) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0230 rtz2ctl r itg dcoil rcir pol 0 sms step w 0x0231 mdc2ctl r mczie modmc rdmcl pre 0 mcen 0 aovie w flmc 0x0232 ssd2ctl r rtze sdcpu ssdwai ftst 00 aclks w 0x0233 ssd2flg r mczif 000000 aovif w 0x0234 mdc2cnth r mdccnt[15:8] w 0x0220?x0227 stepper stall detector 0 (ssd0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 791 0x0235 mdc2cntl r mdccnt[7:0] w 0x0236 itg2acch r itgacc[15:8] w 0x0237 itg2accl r itgacc[7:0] w 0x0238?x023f stepper stall detector 3 (ssd3) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0238 rtz3ctl r itg dcoil rcir pol 0 sms step w 0x0239 mdc3ctl r mczie modmc rdmcl pre 0 mcen 0 aovie w flmc 0x023a ssd3ctl r rtze sdcpu ssdwai ftst 00 aclks w 0x023b ssd3flg r mczif 000000 aovif w 0x023c mdc3cnth r mdccnt[15:8] w 0x023d mdc3cntl r mdccnt[7:0] w 0x023e itg3acch r itgacc[15:8] w 0x023f itg3accl r itgacc[7:0] w 0x0240?x029f port integration module (pim) map 4 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0240 ptt r ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 w 0x0241 ptit r ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 w 0x0242 ddrt r ddrt7 ddrt6 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 w 0x0243 reserved r00000000 w 0x0244 pert r pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 w 0x0245 ppst r ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 w 0x0246 reserved r00000000 w 0x0230?x0237 stepper stall detector 2 (ssd2) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 792 freescale semiconductor 0x0247 pttrr r pttrr7 pttrr6 pttrr5 pttrr4 pttrr3 pttrr2 pttrr1 pttrr0 w 0x0248 pts r pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 w 0x0249 ptis r ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 w 0x024a ddrs r ddrs7 ddrs6 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 w 0x024b reserved r00000000 w 0x024c pers r pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 w 0x024d ppss r ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 w 0x024e woms r woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 w 0x024f ptsrr r0 0 ptsrr5 ptsrr4 00 ptsrr1 ptsrr0 w 0x0250 ptm r0 0 0 0 ptm3 ptm2 ptm1 ptm0 w 0x0251 ptim r 0 0 0 0 ptim3 ptim2 ptim1 ptim0 w 0x0252 ddrm r0 0 0 0 ddrm3 ddrm2 ddrm1 ddrm0 w 0x0253 reserved r00000000 w 0x0254 perm r0 0 0 0 perm3 perm2 perm1 perm0 w 0x0255 ppsm r0 0 0 0 ppsm3 ppsm2 ppsm1 ppsm0 w 0x0256 womm r000000 womm1 womm0 w 0x0257 reserved r00000000 w 0x0258 ptp r ptp7 ptp6 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 w 0x0259 ptip r ptip7 ptip6 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 w 0x025a ddrp r ddrp7 ddrp6 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 w 0x025c perp r perp7 perp6 perp5 perp4 perp3 perp2 perp1 perp0 w 0x025d ppsp r ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppss0 w 0x025e ptprrh r ptprrh7 ptprrh6 ptprrh5 ptprrh4 ptprrh3 ptprrh2 ptprrh1 ptprrh0 w 0x025f ptprrl r0 0 0 0 ptprrl3 ptprrl2 ptprrl1 ptprrl0 w 0x0240?x029f port integration module (pim) map 4 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 793 0x0260 pth r pth7 pth6 pth5 pth4 pth3 pth2 pth1 pth0 w 0x0261 ptih r ptih7 ptih6 ptih5 ptih4 ptih3 ptih2 ptih1 ptih0 w 0x0262 ddrh r ddrh7 ddrh6 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 w 0x0263 reserved r00000000 w 0x0264 perh r perh7 perh6 perh5 perh4 perh3 perh2 perh1 perh0 w 0x0265 ppsh r ppsh7 ppsh6 ppsh5 ppsh4 ppsh3 ppsh2 ppsh1 ppsh0 w 0x0266 womh r womh7 womh6 womh5 womh4 womh3 womh2 womh1 womh0 w 0x0267 pthrr r0000000 pthrr0 w 0x0268- 0x26f reserved r00000000 w 0x0270 pt0ad r 0 0 0 0 pt0ad 3 pt0ad 2 pt0ad 1 pt0ad 0 w 0x0271 pt1ad r pt1ad 7 pt1ad 6 pt1ad 5 pt1ad 4 pt1ad 3 pt1ad 2 pt1ad 1 pt1ad 0 w 0x0272 ddr0ad r 0 0 0 0 ddr0ad 3 ddr0ad 2 ddr0ad 1 ddr0ad 0 w 0x0273 ddr1ad r ddr1ad 7 ddr1ad 6 ddr1ad 5 ddr1ad 4 ddr1ad 3 ddr1ad 2 ddr1ad 1 ddr1ad 0 w 0x0274 reserved r00000000 w 0x0275 reerved r00000000 w 0x0276 per0ad r 0 0 0 0 per0ad 3 per0ad 2 per0ad 1 per0ad 0 w 0x0277 per1ad r per1ad 7 per1ad 6 per1ad 5 per1ad 4 per1ad 3 per1ad 2 per1ad 1 per1ad 0 w 0x0278- 0x027f reserved r00000000 w 0x0280 ptr r ptr7 ptr6 ptr5 ptr4 ptr3 ptr2 ptr1 ptr0 w 0x0281 ptir r ptir7 ptir6 ptir5 ptir4 ptir3 ptir2 ptir1 ptir0 w 0x0282 ddrr r ddrr7 ddrr6 ddrr5 ddrr4 ddrr3 ddrr2 ddrr1 ddrr0 w 0x0283 reserved r 0 0 000000 w 0x0284 perr r perr7 perr6 perr5 perr4 perr3 perr2 perr1 perr0 w 0x0240?x029f port integration module (pim) map 4 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 794 freescale semiconductor 0x0285 ppsr r ppsr7 ppsr6 ppsr5 ppsr4 ppsr3 ppsr2 ppsr1 ppsr0 w 0x0286 womr r womr7 womr6 womr5 womr4 womr3 womr2 womr1 womr0 w 0x0287 reserved r00000000 w 0x0288 piet r piet7 piet6 piet5 piet4 piet3 piet2 piet1 piet0 w 0x0289 pift r pift7 pift6 pift5 pift4 pift3 pift2 pift1 pift0 w 0x028a pies r0 pies6 pies5 0 pies3 pies2 00 w 0x028b pifs r0 pifs6 pifs5 0 pifs3 pifs2 00 w 0x028c pie1ad r pie1ad7 pie1ad6 pie1ad5 pie1ad4 pie1ad3 pie1ad2 pie1ad1 pie1ad0 w 0x028d pif1ad r pif1ad7 pif1ad6 pif1ad5 pif1ad4 pif1ad3 pif1ad2 pif1ad1 pif1ad0 w 0x028e pier r0 0 0 pier4 pier3 pier2 pier1 pier0 w 0x028f pifr r0 0 0 pifr4 pifr3 pifr2 pifr1 pifr0 w 0x0290 ptu r ptu7 ptu6 ptu5 ptu4 ptu3 ptu2 ptu1 ptu0 w 0x0291 ptiu r ptiu7 ptiu6 ptiu5 ptiu4 ptiu3 ptiu2 ptiu1 ptiu0 w 0x0292 ddru r ddru7 ddru6 ddru5 ddru4 ddru3 ddru2 ddru1 ddru0 w 0x0293 reserved r00000000 w 0x0294 peru r peru7 peru6 peru5 peru4 peru3 peru2 peru1 peru0 w 0x0295 ppsu r ppsu7 ppsu6 ppsu5 ppsu4 ppsu3 ppsu2 ppsu1 ppsu0 w 0x0296 srru r srru7 srru6 srru5 srru4 srru3 srru2 srru1 srru0 w 0x0297 pturr r0 0 0 0 pturr3 pturr2 00 w 0x0298 ptv r ptv7 ptv6 ptv5 ptv4 ptv3 ptv2 ptv1 ptv0 w 0x0299 ptiv r ptiv7 ptiv6 ptiv5 ptiv4 ptiv3 ptiv2 ptiv1 ptiv0 w 0x029a ddrv r ddrv7 ddrv6 ddrv5 ddrv4 ddrv3 ddrv2 ddrv1 ddrv0 w 0x029b reserved r00000000 w 0x0240?x029f port integration module (pim) map 4 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 795 0x029c perv r perv7 perv6 perv5 perv4 perv3 perv2 perv1 perv0 w 0x029d ppsv r ppsv7 ppsv6 ppsv5 ppsv4 ppsv3 ppsv2 ppsv1 ppsv0 w 0x029e srrv r srrv7 srrv6 srrv5 srrv4 srrv3 srrv2 srrv1 srrv0 w 0x029f ptvrr r0 0 0 0 ptvrr3 ptvrr2 00 w 0x02a0?x02cf timer module (tim1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02a0 tios r ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 w 0x02a1 cforc r00000000 w foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 0x02a2 oc7m r oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 w 0x02a3 oc7d r oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 w 0x02a4 tcnth r tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 w 0x02a5 tcntl r tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 w 0x02a6 tscr1 r ten tswai tsfrz tffca prnt 000 w 0x02a7 ttov r tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 w 0x02a8 tctl1 r om7 ol7 om6 ol6 om5 ol5 om4 ol4 w 0x02a9 tctl2 r om3 ol3 om2 ol2 om1 ol1 om0 ol0 w 0x02aa tctl3 r edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a w 0x02ab tctl4 r edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a w 0x02ac tie r c7i c6i c5i c4i c3i c2i c1i c0i w 0x02ad tscr2 r toi 000 tcre pr2 pr1 pr0 w 0x02ae tflg1 r c7f c6f c5f c4f c3f c2f c1f c0f w 0x02af tflg2 r tof 0000000 w 0x0240?x029f port integration module (pim) map 4 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 796 freescale semiconductor 0x02b0 tc0h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x02b1 tc0l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x02b2 tc1h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x02b3 tc1l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x02b4 tc2h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x02b5 tc2l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x02b6 tc3h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x02b7 tc3l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x02b8 tc4h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x02b9 tc4l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x02ba tc5h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x02bb tc5l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x02bc tc6h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x02bd tc6l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x02be tc7h r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w 0x02bf tc7l r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0x02c0 pactl r0 paen pamod pedge clk1 clk0 paovi pai w 0x02c1 paflg r000000 paovf paif w 0x02c2 pacnth r pacnt15 pacnt14 pacnt13 pacnt12 pacnt11 pacnt10 pacnt9 pacnt8 w 0x02c3 pacntl r pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 w 0x02c4 0x02cb reserved r00000000 w 0x02cc ocpd r ocpd7 ocpd6 ocpd5 ocpd4 ocpd3 ocpd2 ocpd1 ocpd0 w 0x02a0?x02cf timer module (tim1) map
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 797 0x02cd reserved r00000000 w 0x02ce ptpsr r ptpsr7 ptpsr6 ptpsr5 ptpsr4 ptpsr3 ptpsr2 ptpsr1 ptpsr0 w 0x02cf reserved r00000000 w 0x02d0?x02ef reserved register space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02d0- 0x02ef reserved r00000000 w 0x02f0?x02f7 voltage regulator (vreg_3v3) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02f0 vreghtcl r0 0 vsel vae hten htds htie htif w 0x02f1 vregctrl r00000lvds lvie lvif w 0x02f2 vregapicl r apiclk 00 apifes apiea apife apie apif w 0x02f3 vregapitr r apitr5 apitr4 apitr3 apitr2 apitr1 apitr0 00 w 0x02f4 vregapirh r apir15 apir14 apir13 apir12 apir11 apir10 apir9 apir8 w 0x02f5 vregapirl r apir7 apir6 apir5 apir4 apir3 apir2 apir1 apir0 w 0x02f6 reserved r00000000 w 0x02f7 vreghttr r htoen 000 httr3 httr2 httr1 httr0 w 0x02f8?x02ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02f8 0x02ff reserved r00000000 w 0x0300?x03ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0300 pwme r00000000 w 0x02a0?x02cf timer module (tim1) map
detailed register address map mc9s12xhy-family reference manual, rev. 1.01 798 freescale semiconductor 0x0400?x07ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0400- 0x07ff reserved r00000000 w
ordering information mc9s12xhy-family reference manual, rev. 1.01 freescale semiconductor 799 appendix f ordering information f.1 ordering information the following ?ure provides an ordering part number example for the devices covered by this data book. there are two options when ordering a device. customers must choose between ordering either the mask- speci? part number or the generic / mask-independent part number. ordering the mask-speci? part number enables the customer to specify which particular maskset they will receive whereas ordering the generic maskset means that fsl will ship the currently preferred maskset (which may change over time). in either case, the marking on the device will always show the generic / mask-independent peritoneums and the mask set number. note the mask identi?r suf? and the tape & reel suf? are always both omitted from the part number which is actually marked on the device. for speci? part numbers to order, please contact your local sales of?e. the below ?ure illustrates the structure of a typical mask-speci? ordering number for the mc9s12xhy-family devices. figure f-1. order part number example s 9 s12x hy256 f0 m lm r package option: temperature option: device title controller family c = -40?c to 85?c v = -40?c to 105?c m = -40?c to 125?c lm = 112 lqfp ll = 100lqfp status / partnumber type: s or sc = maskset specific part number mc = generic / mask-independent part number p or pc = prototype status (pre qualification) main memory type: 9 = flash maskset identifier suffix: first digit usually references wafer fab second digit usually differentiates mask rev (this suffix is omitted in generic part numbers) tape & reel: r = tape & reel no r = no tape & reel
ordering information mc9s12xhy-family reference manual, rev. 1.01 800 freescale semiconductor

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